forked from u-boot/u-boot
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathdwc_eth_qos.c
1685 lines (1385 loc) · 42.8 KB
/
dwc_eth_qos.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* Portions based on U-Boot's rtl8169.c.
*/
/*
* This driver supports the Synopsys Designware Ethernet QOS (Quality Of
* Service) IP block. The IP supports multiple options for bus type, clocking/
* reset structure, and feature list.
*
* The driver is written such that generic core logic is kept separate from
* configuration-specific logic. Code that interacts with configuration-
* specific resources is split out into separate functions to avoid polluting
* common code. If/when this driver is enhanced to support multiple
* configurations, the core code should be adapted to call all configuration-
* specific functions through function pointers, with the definition of those
* function pointers being supplied by struct udevice_id eqos_ids[]'s .data
* field.
*
* The following configurations are currently supported:
* tegra186:
* NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
* AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
* supports a single RGMII PHY. This configuration also has SW control over
* all clock and reset signals to the HW block.
*/
#define LOG_CATEGORY UCLASS_ETH
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <eth_phy.h>
#include <log.h>
#include <malloc.h>
#include <memalign.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
#include <phy.h>
#include <reset.h>
#include <wait_bit.h>
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/io.h>
#ifdef CONFIG_ARCH_IMX8M
#include <asm/arch/clock.h>
#include <asm/mach-imx/sys_proto.h>
#endif
#include <linux/delay.h>
#include "dwc_eth_qos.h"
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
* maintenance on CPUs where the cache-line size exceeds the size of these
* descriptors. What will happen is that when the driver receives a packet
* it will be immediately requeued for the hardware to reuse. The CPU will
* therefore need to flush the cache-line containing the descriptor, which
* will cause all other descriptors in the same cache-line to be flushed
* along with it. If one of those descriptors had been written to by the
* device those changes (and the associated packet) will be lost.
*
* To work around this, we make use of non-cached memory if available. If
* descriptors are mapped uncached there's no need to manually flush them
* or invalidate them.
*
* Note that this only applies to descriptors. The packet data buffers do
* not have the same constraints since they are 1536 bytes large, so they
* are unlikely to share cache-lines.
*/
static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num)
{
eqos->desc_size = ALIGN(sizeof(struct eqos_desc),
(unsigned int)ARCH_DMA_MINALIGN);
return memalign(eqos->desc_size, num * eqos->desc_size);
}
static void eqos_free_descs(void *descs)
{
free(descs);
}
static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos,
unsigned int num, bool rx)
{
return eqos->descs +
((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size;
}
void eqos_inval_desc_generic(void *desc)
{
unsigned long start = (unsigned long)desc;
unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
}
void eqos_flush_desc_generic(void *desc)
{
unsigned long start = (unsigned long)desc;
unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
}
void eqos_inval_buffer_tegra186(void *buf, size_t size)
{
unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
}
void eqos_inval_buffer_generic(void *buf, size_t size)
{
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
}
static void eqos_flush_buffer_tegra186(void *buf, size_t size)
{
flush_cache((unsigned long)buf, size);
}
void eqos_flush_buffer_generic(void *buf, size_t size)
{
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
}
static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
{
return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
EQOS_MAC_MDIO_ADDRESS_GB, false,
1000000, true);
}
static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
int mdio_reg)
{
struct eqos_priv *eqos = bus->priv;
u32 val;
int ret;
debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
mdio_reg);
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
pr_err("MDIO not idle at entry");
return ret;
}
val = readl(&eqos->mac_regs->mdio_address);
val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
EQOS_MAC_MDIO_ADDRESS_C45E;
val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
(eqos->config->config_mac_mdio <<
EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
(EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
EQOS_MAC_MDIO_ADDRESS_GB;
writel(val, &eqos->mac_regs->mdio_address);
udelay(eqos->config->mdio_wait);
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
pr_err("MDIO read didn't complete");
return ret;
}
val = readl(&eqos->mac_regs->mdio_data);
val &= EQOS_MAC_MDIO_DATA_GD_MASK;
debug("%s: val=%x\n", __func__, val);
return val;
}
static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
int mdio_reg, u16 mdio_val)
{
struct eqos_priv *eqos = bus->priv;
u32 val;
int ret;
debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
mdio_addr, mdio_reg, mdio_val);
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
pr_err("MDIO not idle at entry");
return ret;
}
writel(mdio_val, &eqos->mac_regs->mdio_data);
val = readl(&eqos->mac_regs->mdio_address);
val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
EQOS_MAC_MDIO_ADDRESS_C45E;
val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
(mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
(eqos->config->config_mac_mdio <<
EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
(EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
EQOS_MAC_MDIO_ADDRESS_GB;
writel(val, &eqos->mac_regs->mdio_address);
udelay(eqos->config->mdio_wait);
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
pr_err("MDIO read didn't complete");
return ret;
}
return 0;
}
static int eqos_start_clks_tegra186(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
ret = clk_enable(&eqos->clk_slave_bus);
if (ret < 0) {
pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
goto err;
}
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
pr_err("clk_enable(clk_master_bus) failed: %d", ret);
goto err_disable_clk_slave_bus;
}
ret = clk_enable(&eqos->clk_rx);
if (ret < 0) {
pr_err("clk_enable(clk_rx) failed: %d", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_ptp_ref);
if (ret < 0) {
pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
goto err_disable_clk_rx;
}
ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
if (ret < 0) {
pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
goto err_disable_clk_ptp_ref;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
pr_err("clk_enable(clk_tx) failed: %d", ret);
goto err_disable_clk_ptp_ref;
}
#endif
debug("%s: OK\n", __func__);
return 0;
#ifdef CONFIG_CLK
err_disable_clk_ptp_ref:
clk_disable(&eqos->clk_ptp_ref);
err_disable_clk_rx:
clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err_disable_clk_slave_bus:
clk_disable(&eqos->clk_slave_bus);
err:
debug("%s: FAILED: %d\n", __func__, ret);
return ret;
#endif
}
static int eqos_start_clks_stm32(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
pr_err("clk_enable(clk_master_bus) failed: %d", ret);
goto err;
}
ret = clk_enable(&eqos->clk_rx);
if (ret < 0) {
pr_err("clk_enable(clk_rx) failed: %d", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
pr_err("clk_enable(clk_tx) failed: %d", ret);
goto err_disable_clk_rx;
}
if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
ret = clk_enable(&eqos->clk_ck);
if (ret < 0) {
pr_err("clk_enable(clk_ck) failed: %d", ret);
goto err_disable_clk_tx;
}
eqos->clk_ck_enabled = true;
}
#endif
debug("%s: OK\n", __func__);
return 0;
#ifdef CONFIG_CLK
err_disable_clk_tx:
clk_disable(&eqos->clk_tx);
err_disable_clk_rx:
clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
debug("%s: FAILED: %d\n", __func__, ret);
return ret;
#endif
}
static int eqos_stop_clks_tegra186(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clk_disable(&eqos->clk_tx);
clk_disable(&eqos->clk_ptp_ref);
clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
clk_disable(&eqos->clk_slave_bus);
#endif
debug("%s: OK\n", __func__);
return 0;
}
static int eqos_stop_clks_stm32(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clk_disable(&eqos->clk_tx);
clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
#endif
debug("%s: OK\n", __func__);
return 0;
}
static int eqos_start_resets_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
return ret;
}
udelay(2);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
return ret;
}
ret = reset_assert(&eqos->reset_ctl);
if (ret < 0) {
pr_err("reset_assert() failed: %d", ret);
return ret;
}
udelay(2);
ret = reset_deassert(&eqos->reset_ctl);
if (ret < 0) {
pr_err("reset_deassert() failed: %d", ret);
return ret;
}
debug("%s: OK\n", __func__);
return 0;
}
static int eqos_stop_resets_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
reset_assert(&eqos->reset_ctl);
dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
return 0;
}
static int eqos_calibrate_pads_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
udelay(1);
setbits_le32(&eqos->tegra186_regs->auto_cal_config,
EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
if (ret) {
pr_err("calibrate didn't start");
goto failed;
}
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
if (ret) {
pr_err("calibrate didn't finish");
goto failed;
}
ret = 0;
failed:
clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
debug("%s: returns %d\n", __func__, ret);
return ret;
}
static int eqos_disable_calibration_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
EQOS_AUTO_CAL_CONFIG_ENABLE);
return 0;
}
static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
return clk_get_rate(&eqos->clk_slave_bus);
#else
return 0;
#endif
}
static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
return clk_get_rate(&eqos->clk_master_bus);
#else
return 0;
#endif
}
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
return 0;
}
static int eqos_set_half_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
/* WAR: Flush TX queue when switching to half-duplex */
setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
return 0;
}
static int eqos_set_gmii_speed(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clrbits_le32(&eqos->mac_regs->configuration,
EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
return 0;
}
static int eqos_set_mii_speed_100(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
setbits_le32(&eqos->mac_regs->configuration,
EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
return 0;
}
static int eqos_set_mii_speed_10(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clrsetbits_le32(&eqos->mac_regs->configuration,
EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
return 0;
}
static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
{
#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
ulong rate;
int ret;
debug("%s(dev=%p):\n", __func__, dev);
switch (eqos->phy->speed) {
case SPEED_1000:
rate = 125 * 1000 * 1000;
break;
case SPEED_100:
rate = 25 * 1000 * 1000;
break;
case SPEED_10:
rate = 2.5 * 1000 * 1000;
break;
default:
pr_err("invalid speed %d", eqos->phy->speed);
return -EINVAL;
}
ret = clk_set_rate(&eqos->clk_tx, rate);
if (ret < 0) {
pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
return ret;
}
#endif
return 0;
}
static int eqos_adjust_link(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
bool en_calibration;
debug("%s(dev=%p):\n", __func__, dev);
if (eqos->phy->duplex)
ret = eqos_set_full_duplex(dev);
else
ret = eqos_set_half_duplex(dev);
if (ret < 0) {
pr_err("eqos_set_*_duplex() failed: %d", ret);
return ret;
}
switch (eqos->phy->speed) {
case SPEED_1000:
en_calibration = true;
ret = eqos_set_gmii_speed(dev);
break;
case SPEED_100:
en_calibration = true;
ret = eqos_set_mii_speed_100(dev);
break;
case SPEED_10:
en_calibration = false;
ret = eqos_set_mii_speed_10(dev);
break;
default:
pr_err("invalid speed %d", eqos->phy->speed);
return -EINVAL;
}
if (ret < 0) {
pr_err("eqos_set_*mii_speed*() failed: %d", ret);
return ret;
}
if (en_calibration) {
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
pr_err("eqos_calibrate_pads() failed: %d",
ret);
return ret;
}
} else {
ret = eqos->config->ops->eqos_disable_calibration(dev);
if (ret < 0) {
pr_err("eqos_disable_calibration() failed: %d",
ret);
return ret;
}
}
ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
if (ret < 0) {
pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
return ret;
}
return 0;
}
static int eqos_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
uint32_t val;
/*
* This function may be called before start() or after stop(). At that
* time, on at least some configurations of the EQoS HW, all clocks to
* the EQoS HW block will be stopped, and a reset signal applied. If
* any register access is attempted in this state, bus timeouts or CPU
* hangs may occur. This check prevents that.
*
* A simple solution to this problem would be to not implement
* write_hwaddr(), since start() always writes the MAC address into HW
* anyway. However, it is desirable to implement write_hwaddr() to
* support the case of SW that runs subsequent to U-Boot which expects
* the MAC address to already be programmed into the EQoS registers,
* which must happen irrespective of whether the U-Boot user (or
* scripts) actually made use of the EQoS device, and hence
* irrespective of whether start() was ever called.
*
* Note that this requirement by subsequent SW is not valid for
* Tegra186, and is likely not valid for any non-PCI instantiation of
* the EQoS HW block. This function is implemented solely as
* future-proofing with the expectation the driver will eventually be
* ported to some system where the expectation above is true.
*/
if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
return 0;
/* Update the MAC address */
val = (plat->enetaddr[5] << 8) |
(plat->enetaddr[4]);
writel(val, &eqos->mac_regs->address0_high);
val = (plat->enetaddr[3] << 24) |
(plat->enetaddr[2] << 16) |
(plat->enetaddr[1] << 8) |
(plat->enetaddr[0]);
writel(val, &eqos->mac_regs->address0_low);
return 0;
}
static int eqos_read_rom_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
ret = eqos->config->ops->eqos_get_enetaddr(dev);
if (ret < 0)
return ret;
return !is_valid_ethaddr(pdata->enetaddr);
}
static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
int reg;
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("Failed to find phy-handle");
return -ENODEV;
}
priv->phy_of_node = phandle_args.node;
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
}
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret, i;
ulong rate;
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
debug("%s(dev=%p):\n", __func__, dev);
eqos->tx_desc_idx = 0;
eqos->rx_desc_idx = 0;
ret = eqos->config->ops->eqos_start_resets(dev);
if (ret < 0) {
pr_err("eqos_start_resets() failed: %d", ret);
goto err;
}
udelay(10);
eqos->reg_access_ok = true;
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
if (ret) {
pr_err("EQOS_DMA_MODE_SWR stuck");
goto err_stop_resets;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
pr_err("eqos_calibrate_pads() failed: %d", ret);
goto err_stop_resets;
}
rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
val = (rate / 1000000) - 1;
writel(val, &eqos->mac_regs->us_tic_counter);
/*
* if PHY was already connected and configured,
* don't need to reconnect/reconfigure again
*/
if (!eqos->phy) {
int addr = -1;
addr = eqos_get_phy_addr(eqos, dev);
eqos->phy = phy_connect(eqos->mii, addr, dev,
eqos->config->interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
}
if (eqos->max_speed) {
ret = phy_set_supported(eqos->phy, eqos->max_speed);
if (ret) {
pr_err("phy_set_supported() failed: %d", ret);
goto err_shutdown_phy;
}
}
eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
goto err_shutdown_phy;
}
}
ret = phy_startup(eqos->phy);
if (ret < 0) {
pr_err("phy_startup() failed: %d", ret);
goto err_shutdown_phy;
}
if (!eqos->phy->link) {
pr_err("No link");
goto err_shutdown_phy;
}
ret = eqos_adjust_link(dev);
if (ret < 0) {
pr_err("eqos_adjust_link() failed: %d", ret);
goto err_shutdown_phy;
}
/* Configure MTL */
/* Enable Store and Forward mode for TX */
/* Program Tx operating mode */
setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
(EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
/* Transmit Queue weight */
writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
/* Enable Store and Forward mode for RX, since no jumbo frame */
setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
val = readl(&eqos->mac_regs->hw_feature1);
tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
/*
* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
* r/tqs is encoded as (n / 256) - 1.
*/
tqs = (128 << tx_fifo_sz) / 256 - 1;
rqs = (128 << rx_fifo_sz) / 256 - 1;
clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
/* Flow control used only if each channel gets 4KB or more FIFO */
if (rqs >= ((4096 / 256) - 1)) {
u32 rfd, rfa;
setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
/*
* Set Threshold for Activating Flow Contol space for min 2
* frames ie, (1500 * 1) = 1500 bytes.
*
* Set Threshold for Deactivating Flow Contol for space of
* min 1 frame (frame size 1500bytes) in receive fifo
*/
if (rqs == ((4096 / 256) - 1)) {
/*
* This violates the above formula because of FIFO size
* limit therefore overflow may occur inspite of this.
*/
rfd = 0x3; /* Full-3K */
rfa = 0x1; /* Full-1.5K */
} else if (rqs == ((8192 / 256) - 1)) {
rfd = 0x6; /* Full-4K */
rfa = 0xa; /* Full-6K */
} else if (rqs == ((16384 / 256) - 1)) {
rfd = 0x6; /* Full-4K */
rfa = 0x12; /* Full-10K */
} else {
rfd = 0x6; /* Full-4K */
rfa = 0x1E; /* Full-16K */
}
clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
(EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
(EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
(rfd <<
EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
(rfa <<
EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
}
/* Configure MAC */
clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
eqos->config->config_mac <<
EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
/* Multicast and Broadcast Queue Enable */
setbits_le32(&eqos->mac_regs->unused_0a4,
0x00100000);
/* enable promise mode */
setbits_le32(&eqos->mac_regs->unused_004[1],
0x1);
/* Set TX flow control parameters */
/* Set Pause Time */
setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
/* Assign priority for TX flow control */
clrbits_le32(&eqos->mac_regs->txq_prty_map0,
EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
/* Assign priority for RX flow control */
clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
/* Enable flow control */
setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
EQOS_MAC_RX_FLOW_CTRL_RFE);
clrsetbits_le32(&eqos->mac_regs->configuration,
EQOS_MAC_CONFIGURATION_GPSLCE |
EQOS_MAC_CONFIGURATION_WD |
EQOS_MAC_CONFIGURATION_JD |
EQOS_MAC_CONFIGURATION_JE,
EQOS_MAC_CONFIGURATION_CST |
EQOS_MAC_CONFIGURATION_ACS);
eqos_write_hwaddr(dev);
/* Configure DMA */
/* Enable OSP mode */
setbits_le32(&eqos->dma_regs->ch0_tx_control,
EQOS_DMA_CH0_TX_CONTROL_OSP);
/* RX buffer size. Must be a multiple of bus width */
clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
EQOS_MAX_PACKET_SIZE <<
EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) /
eqos->config->axi_bus_width;
setbits_le32(&eqos->dma_regs->ch0_control,
EQOS_DMA_CH0_CONTROL_PBLX8 |
(desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT));
/*
* Burst length must be < 1/2 FIFO size.
* FIFO size in tqs is encoded as (n / 256) - 1.
* Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
* Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
*/
pbl = tqs + 1;
if (pbl > 32)
pbl = 32;
clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
/* DMA performance configuration */
val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
writel(val, &eqos->dma_regs->sysbus_mode);