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WRITE_DATA = 0x55
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TXD2 = "LA1"
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RXD2 = "SQ1"
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- PWM_FERQUENCY = UART ._baudrate
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+ PWM_FERQUENCY = UART ._baudrate // 2
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MICROSECONDS = 1e-6
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RELTOL = 0.05
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# Number of expected logic level changes.
@@ -59,13 +59,14 @@ def test_configure(la: LogicAnalyzer, uart: UART):
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uart .write_byte (WRITE_DATA )
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la .stop ()
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(txd2 ,) = la .fetch_data ()
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- start_to_stop = 1 + 8 + 1
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+ start_to_stop = 9
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period = (txd2 [- 1 ] - txd2 [0 ]) / start_to_stop
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+
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assert (period * MICROSECONDS ) ** - 1 == pytest .approx (baudrate , rel = RELTOL )
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def test_write_byte (la : LogicAnalyzer , uart : UART ):
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- la .capture (3 , block = False )
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+ la .capture (1 , block = False )
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uart .write_byte (WRITE_DATA )
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la .stop ()
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(txd2 ,) = la .fetch_data ()
@@ -74,7 +75,7 @@ def test_write_byte(la: LogicAnalyzer, uart: UART):
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def test_write_int (la : LogicAnalyzer , uart : UART ):
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- la .capture (3 , block = False )
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+ la .capture (1 , block = False )
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uart .write_int ((WRITE_DATA << 8 ) | WRITE_DATA )
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la .stop ()
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(txd2 ,) = la .fetch_data ()
@@ -85,10 +86,10 @@ def test_write_int(la: LogicAnalyzer, uart: UART):
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def test_read_byte (pwm : PWMGenerator , uart : UART ):
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value = uart .read_byte ()
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- assert value in (0 , 0xFF )
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+ assert value in (0x55 , 0xAA )
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def test_read_int (pwm : PWMGenerator , uart : UART ):
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value = uart .read_int ()
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- assert value in (0 , 0xFFFF )
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+ assert value in (0x5555 , 0x55AA , 0xAA55 , 0xAAAA )
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