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testes.cr.mti
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C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux10_5.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux10_5.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux10_5
Top level modules:
mux10_5
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_8.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_8.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Sign_extend_8
Top level modules:
Sign_extend_8
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux14_2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux14_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux14_2
Top level modules:
mux14_2
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux4_3.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux4_3.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux4_3
Top level modules:
mux4_3
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux2_5.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux2_5.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux2_5
Top level modules:
mux2_5
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/shift_left2_25.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/shift_left2_25.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module shift_left2_25
Top level modules:
shift_left2_25
} {} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Memoria.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Memoria.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Compiling package ram_constants
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package LPM_COMPONENTS
-- Loading package ram_constants
-- Compiling entity Memoria
-- Compiling architecture behavioral_arch of Memoria
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux1_7.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux1_7.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux1_7
Top level modules:
mux1_7
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux6_2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux6_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux6_2
Top level modules:
mux6_2
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux13_5.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux13_5.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux13_5
Top level modules:
mux13_5
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux7_2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux7_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux7_2
Top level modules:
mux7_2
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/shift_left2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/shift_left2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module shift_left2
Top level modules:
shift_left2
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/div.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/div.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module div
Top level modules:
div
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/SH.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/SH.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module SH
Top level modules:
SH
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux5_5.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux5_5.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux5_5
Top level modules:
mux5_5
} {} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Registrador.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Registrador.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity Registrador
-- Compiling architecture behavioral_arch of Registrador
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux3_8.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux3_8.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux3_8
Top level modules:
mux3_8
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux8_4.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux8_4.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux8_4
Top level modules:
mux8_4
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux9_3.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux9_3.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux9_3
Top level modules:
mux9_3
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_16.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_16.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Sign_extend_16
Top level modules:
Sign_extend_16
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/load_decider.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/load_decider.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module load_decider
Top level modules:
load_decider
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_1.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/Sign_extend_1.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Sign_extend_1
Top level modules:
Sign_extend_1
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/cpu1.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/cpu1.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module cpu1
Top level modules:
cpu1
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mult.v {0 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mult.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mult
** Error: C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mult.v(26): (vlog-2110) Illegal reference to net "stop_operation".
** Error: C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mult.v(33): (vlog-2110) Illegal reference to net "start_operation".
** Error: C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mult.v(56): (vlog-2110) Illegal reference to net "stop_operation".
} {4.0 7.0} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Instr_Reg.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Instr_Reg.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity Instr_Reg
-- Compiling architecture behavioral_arch of Instr_Reg
} {} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/ula32.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/ula32.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity Ula32
-- Compiling architecture behavioral of Ula32
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/SB.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/SB.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module SB
Top level modules:
SB
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux11_2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux11_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux11_2
Top level modules:
mux11_2
} {} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/RegDesloc.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/RegDesloc.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RegDesloc
-- Compiling architecture behavioral_arch of RegDesloc
} {} {}} {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Banco_reg.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes dadas/Banco_reg.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity Banco_reg
-- Compiling architecture behavioral_arch of Banco_reg
} {} {}} C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux12_2.v {1 {vlog -work work -stats=none C:/Users/davim/Desktop/infra-hard/ProjetoHW-2021.2/partes_feitas/mux12_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mux12_2
Top level modules:
mux12_2
} {} {}}