PicoRV32 - A Size-Optimized RISC-V CPU

RTL, Cmodel, and testbench for NVDLA

Open source FPGA-based NIC and platform for in-network compute

A small, light weight, RISC CPU soft core

RISC-V CPU Core (RV32IM)

Verilog PCI express components

An Open-source FPGA IP Generator

synthesiseable ieee 754 floating point library in verilog

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

repository for Vidor FPGA IP blocks and projects

Source code to accompany https://timetoexplore.net

Multi-cycle pipelined ARM-LEGv8 CPU with Forwarding and Hazard Detection.

Implementation of a circular queue in hardware using verilog.

This repository holds the source code, benchmarks and results of the work presented in the paper entitled "Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits".