hw5.txt

CS 61C Homework 5
Name:Fei Liu

Login:cs61c-ew


P1 - Pipelining
1) 0.9523809 GHz (This is 1/maximum_delay_critical_path, 105 in total) 
2) 1.8181818 GHz (This is 1/max-delay-between-registers, 55 in this case)
3) 105 ns in the non-pipelined version. For the first signal, it takes \
165=55*3 ns for the first change to output in the piplined version. 
4) 3 (105*3=315 ns for non-pipelined version, while 55*3+55+55=275 ns for pipelined version )



P2 - Waveform Diagrams
1) 5 times 
2) 3 times
3) A is 0 during the periods that lasts from 5 to 35, from 65 to 95, and from 125 to 155. 
4) C is 1 during the periods that lasts from  65 to 95 and from 125 to 155. 



P3 - Clock Frequency
1) No, the adder with Yi will change the input the value before the \
  before the hold time register passes.  
2) the critical path delay is 2 ns and the max clock frequncy is 1.42857142\
  Hz (which is 1/(7*10^(-9))) 
3) add Xi and Yi first and add with the S_i-1 will reduce the max period\
to be 6 ns instead of 7ns so the 1.666666Gflops/s (which is 1/(6*10^(-9))

P4 - Simple FSM and Truth Tables

CurState	| Input	| NextState	| Output
 seen0  	| 0   	| seen0 		| 0     
 seen0  	| 1   	| seen1 		| 0     
 seen1  	| 0   	| seen0 		| 0     
 seen1  	| 1   	| seen11		| 1     
 seen11 	| 0   	| seen0 		| 1     
 seen11 	| 1   	| seem11		| 1     
		| 	| 		|  

//you can add more rows if necessary


P5 - Truth Tables, Boolean Algebra, FSMs, Logic Circuits
1)

Out = CS0 * Input'  

Next1 =CS1' * Input 

Next0 = Input' 

2) hw5fsm.circ
3) A==0&&B==0  


P6
1) For Jal:
Jaltype signal is generated by Control subcircuit. At the same
time the output of the PC adder is directed to Write Data port of Registers\
subcircuit.(Since this is a single pipeline, I didn't follow the PC+8 in the\
green sheet because it if is not pipelined PC+4 is good)\
There is another MUX before data is entered into the WriteData port\
of the Registers subcircuit. If the Jaltype signal is 1, enter the PC+8 value\
if 0 enter the previous wire. The MUX that controls input to WriteReg port of Register is \
expanded to accomodate the expanded RegDst signal from Control. The \ 
expanded option is constant input 31 that will be connected if it is JalType is\
1. From Instruction Memory branch out a wire with [25-0] 26 data bits address\
and under Sign Extension subcircuit, we add Address modification\
sub-circuit. The circuit takes 26 bits of address from the Jal type\
instruction and the old PC value, and pad two 0's behind and the first 4 bits of previous PC \
in the front. The result is passed to WriteData port of the Registers \
subcircuit. A third new MUX decided by JalType will connect this output if 1, \
old wire if 0.
Ori: zero extension is used so at the place hold by Sign extension subcircuit\
we place both zero and sign extension circuit and controled by zeroExtend signal \
controller. If zeroExtend signal is 0, use the sign extension , while use zero \
extension if zeroExtend signal is 1.


2)
Instruction | RegDst | ALUSrc | MemToReg | RegWrite | MemRead | MemWrite |Branch| JalType| zeroExtend  //add more columns here if you need to
R-format    | 1	     | 0      | 0        | 1	      | 0	      | 0	       | 0    |  0     | X  
lw	        | 0	     | 1      | 1	       | 1	      | 1	      | 0	       | 0    |  0     | 0  
sw	        | X	     | 1      | X	       | 0        | 0	      | 1     	 | 0    |  0     | 0  
beq	        | X	     | 0      | X	       | 0        | 0	      | 0	       | 1    |  0     | 0  
jal	     | 10(state) | X      | 0      	 | 1   	    | X       | 0      	 | 0    |  1     | X  
ori	        | 0	     | 1      |	0	       | 1   	    | X	      | 0        | 0    |  0     | 1  

3)
Yes, replacing is fine in this case. As long as the memory is supposed to be
read, it is surely to be written to the register in someway. So, these two
signals are interchangable.