diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md
index 98770c533..ca0c12108 100644
--- a/doc/axi_xbar.md
+++ b/doc/axi_xbar.md
@@ -49,6 +49,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
 | `LatencyMode`        | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. |
 | `AxiIdWidthSlvPorts` | `int unsigned`     | The AXI ID width of the slave ports. |
 | `AxiIdUsedSlvPorts`  | `int unsigned`     | The number of slave port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below).  This value has to be less or equal than `AxiIdWidthSlvPorts`. |
+| `UniqueIds`          | `bit`              | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar.  See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. |
 | `AxiAddrWidth`       | `int unsigned`     | The AXI address width. |
 | `AxiDataWidth`       | `int unsigned`     | The AXI data width. |
 | `NoAddrRules`        | `int unsigned`     | The number of address map rules. |
diff --git a/scripts/axi_intercon_gen.py b/scripts/axi_intercon_gen.py
index 8f6b02544..af5b3a209 100644
--- a/scripts/axi_intercon_gen.py
+++ b/scripts/axi_intercon_gen.py
@@ -351,6 +351,7 @@ def write(self):
     LatencyMode:        axi_pkg::CUT_ALL_AX,
     AxiIdWidthSlvPorts: AxiIdWidthMasters,
     AxiIdUsedSlvPorts:  AxiIdUsed,
+    UniqueIds:          1'b0,
     AxiAddrWidth:       AxiAddrWidth,
     AxiDataWidth:       AxiDataWidth,
     NoAddrRules:        NoSlaves
diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv
index 712e4ca34..92ede558c 100644
--- a/src/axi_pkg.sv
+++ b/src/axi_pkg.sv
@@ -401,6 +401,7 @@ package axi_pkg;
     xbar_latency_e LatencyMode;
     int unsigned   AxiIdWidthSlvPorts;
     int unsigned   AxiIdUsedSlvPorts;
+    bit            UniqueIds;
     int unsigned   AxiAddrWidth;
     int unsigned   AxiDataWidth;
     int unsigned   NoAddrRules;
diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv
index ae1e6ecad..d66cd97d5 100644
--- a/src/axi_xbar.sv
+++ b/src/axi_xbar.sv
@@ -141,6 +141,7 @@ module axi_xbar #(
       .NoMstPorts     ( Cfg.NoMstPorts + 1     ),
       .MaxTrans       ( Cfg.MaxMstTrans        ),
       .AxiLookBits    ( Cfg.AxiIdUsedSlvPorts  ),
+      .UniqueIds      ( Cfg.UniqueIds          ),
       .FallThrough    ( Cfg.FallThrough        ),
       .SpillAw        ( Cfg.LatencyMode[9]     ),
       .SpillW         ( Cfg.LatencyMode[8]     ),
diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv
index b1acd3abc..595bd6ad3 100644
--- a/test/tb_axi_xbar.sv
+++ b/test/tb_axi_xbar.sv
@@ -55,6 +55,7 @@ module tb_axi_xbar #(
     LatencyMode:        axi_pkg::CUT_ALL_AX,
     AxiIdWidthSlvPorts: AxiIdWidthMasters,
     AxiIdUsedSlvPorts:  AxiIdUsed,
+    UniqueIds:          1'b0,
     AxiAddrWidth:       AxiAddrWidth,
     AxiDataWidth:       AxiDataWidth,
     NoAddrRules:        8