From e940d76f28f320260b5433400239d0885b922ff9 Mon Sep 17 00:00:00 2001 From: Nate DeSimone Date: Wed, 9 Sep 2020 14:08:16 -0700 Subject: [PATCH 1/4] Create legacy FSP branch Signed-off-by: Nate DeSimone --- AmberLakeFspBinPkg/AmberLakeFspBinPkg.dec | 19 - .../Docs/Amberlake_FSP_Integration_Guide.chm | Bin 1232443 -> 0 bytes .../Docs/Amberlake_FSP_Integration_Guide.pdf | Bin 1755367 -> 0 bytes AmberLakeFspBinPkg/Fsp.bsf | 3327 ----- AmberLakeFspBinPkg/Fsp.fd | Bin 618496 -> 0 bytes AmberLakeFspBinPkg/FspPcds.dsc | 40 - .../Include/ConfigBlock/CpuConfigFspData.h | 84 - AmberLakeFspBinPkg/Include/FspUpd.h | 49 - AmberLakeFspBinPkg/Include/FspmUpd.h | 1722 --- AmberLakeFspBinPkg/Include/FspsUpd.h | 3021 ---- AmberLakeFspBinPkg/Include/FsptUpd.h | 133 - AmberLakeFspBinPkg/Include/GpioConfig.h | 354 - AmberLakeFspBinPkg/Include/GpioSampleDef.h | 382 - AmberLakeFspBinPkg/Include/MemInfoHob.h | 278 - .../Include/SmbiosCacheInfoHob.h | 52 - .../Include/SmbiosProcessorInfoHob.h | 68 - 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AmberLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2019, Intel Corporation. All rights reserved.
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All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "KBLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gSiPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - Skip 6 bytes - $gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gSiPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - - Find "KBLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x440000 - $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gKabylakeFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gKabylakeFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gKabylakeFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0xC8,0x00,0x51,0x00,0xA2,0x00 - $gKabylakeFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x64,0x00,0x28,0x00,0x28,0x00,0x17,0x00,0x28,0x00 - $gKabylakeFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - Skip 2 bytes - $gKabylakeFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gKabylakeFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gKabylakeFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_EnableTraceHub 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DpSscMarginEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 59 bytes - $gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - Skip 105 bytes - $gKabylakeFspPkgTokenSpaceGuid_MmaTestContentPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MmaTestContentSize 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MmaTestConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_MmaTestConfigSize 4 bytes $_DEFAULT_ = 0x00000000 - Skip 19 bytes - $gKabylakeFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CmdTriStateDis 1 bytes $_DEFAULT_ = 0x00 - Skip 14 bytes - $gKabylakeFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gKabylakeFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gKabylakeFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gKabylakeFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - Skip 115 bytes - $gKabylakeFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gKabylakeFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gKabylakeFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 4 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 4 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EndPointHint 4 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 2 bytes $_DEFAULT_ = 0x03,0x03 - $gKabylakeFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 8 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - $gKabylakeFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_PegGpioData 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_PegRootPortHPE 3 bytes $_DEFAULT_ = 0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xDF000000 - $gKabylakeFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gKabylakeFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_RootPortDev 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_RootPortFun 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_GtsMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtsExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_EdramRatio 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RingMinOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_CpuRatioOverride 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gKabylakeFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gSkylakeFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_FlashWearOutProtection 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_ReservedSecurityPreMem 7 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHpetEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchHpetBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHpetBase 4 bytes $_DEFAULT_ = 0xFED00000 - $gKabylakeFspPkgTokenSpaceGuid_PchHpetBusNumber 1 bytes $_DEFAULT_ = 0xF0 - $gKabylakeFspPkgTokenSpaceGuid_PchHpetDeviceNumber 1 bytes $_DEFAULT_ = 0x1F - $gKabylakeFspPkgTokenSpaceGuid_PchHpetFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchAcpiBase 2 bytes $_DEFAULT_ = 0x1800 - $gKabylakeFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gKabylakeFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_TraceHubMemReg0Size 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_TraceHubMemReg1Size 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gSiPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x12 - $gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gSiPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - $gKabylakeFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gKabylakeFspPkgTokenSpaceGuid_EvLoader 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00 - Skip 7 bytes - $gKabylakeFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DmiVc1 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DmiVcm 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - Skip 6 bytes - $gKabylakeFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3RootPortPreset 16 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3EndPointPreset 16 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gKabylakeFspPkgTokenSpaceGuid_PegGen3EndPointHint 16 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gKabylakeFspPkgTokenSpaceGuid_SaPreMemTestRsvd 4 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_BiosAcmBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gSkylakeFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gSkylakeFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gSkylakeFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gSkylakeFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gSkylakeFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2000 - $gKabylakeFspPkgTokenSpaceGuid_PchDciEn 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchDciAutoDetect 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ChipsetInitMessage 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_BypassPhySyncReset 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_DisableHeciRetry 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_IderDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - - Find "KBLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 23 bytes - $gKabylakeFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchCio2Enable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SpiFlashCfgLockDown 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SsicPortEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoDevMode 11 bytes $_DEFAULT_ = 0x02, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x04 - $gKabylakeFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gKabylakeFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gKabylakeFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gKabylakeFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gKabylakeFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gKabylakeFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DelayUsbPdoProgramming 1 bytes $_DEFAULT_ = 0x00 - Skip 23 bytes - $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqSupport 24 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqNumber 24 bytes $_DEFAULT_ = 0x02, 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x05, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 5 bytes - $gKabylakeFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - Skip 9 bytes - $gKabylakeFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_WatchDog 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_AsfEnabled 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkSrcNumber 24 bytes $_DEFAULT_ = 0x02, 0x1f, 0x1f, 0x1f, 0x03, 0x01, 0x1f, 0x1f, 0x05, 0x04, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f - $gKabylakeFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 115 bytes - $gKabylakeFspPkgTokenSpaceGuid_DefaultSvid 2 bytes $_DEFAULT_ = 0x8086 - $gKabylakeFspPkgTokenSpaceGuid_DefaultSid 2 bytes $_DEFAULT_ = 0x2015 - $gKabylakeFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 6 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PegDeEmphasis 3 bytes $_DEFAULT_ = 0x01,0x01,0x01 - $gKabylakeFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 3 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B - $gKabylakeFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 3 bytes $_DEFAULT_ = 0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gKabylakeFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_SaImguEnable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_GmmEnable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_VtdBaseAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - Skip 18 bytes - $gKabylakeFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 15 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - Skip 9 bytes - $gKabylakeFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - Skip 4 bytes - $gKabylakeFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SendVrMbxCmd1 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeMtrrData 4 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_AesEnable 1 bits $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_EnableRsr 1 bits $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_EnableDts 2 bits $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_SmmbaseSwSmiNumber 8 bits $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_TxtEnable 1 bits $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SkipMpInit 1 bits $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_RsvdBits 18 bits $_DEFAULT_ = 0x1 - Skip 4 bytes - $gKabylakeFspPkgTokenSpaceGuid_MicrocodePatchAddress 8 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeMtrrDataSize 2 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortATermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortATrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortAClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCClkTrimValue 1 bytes $_DEFAULT_ = 0x09 - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortADataTrimValue 2 bytes $_DEFAULT_ = 0xBBBB - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBDataTrimValue 2 bytes $_DEFAULT_ = 0xBBBB - $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDDataTrimValue 2 bytes $_DEFAULT_ = 0xCCCC - $gKabylakeFspPkgTokenSpaceGuid_PchDmiAspm 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferVoltage 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointDmic 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointBluetooth 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspFeatureMask 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspPpModuleMask 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointI2s 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicBusNumber 1 bytes $_DEFAULT_ = 0xF0 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicDeviceNumber 1 bytes $_DEFAULT_ = 0x1F - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PchIoApicRangeSelect 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchLanK1OffEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLanClkReqSupported 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLanClkReqNumber 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchLockDownSpiEiss 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSubSystemVendorId 2 bytes $_DEFAULT_ = 0x8086 - $gKabylakeFspPkgTokenSpaceGuid_PchSubSystemId 2 bytes $_DEFAULT_ = 0x7270 - $gKabylakeFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - Skip 5 bytes - $gKabylakeFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpDeviceResetPadActiveHigh 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpDeviceResetPad 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gKabylakeFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x04, 0x08, 0x02, 0x0A - $gKabylakeFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieAllowNoLtrIccPllShutdown 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieDetectTimeoutMs 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS0VmEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 5 bytes - $gKabylakeFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - Skip 6 bytes - $gKabylakeFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmCapsuleResetType 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_PchPort61hEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - $gKabylakeFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gKabylakeFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstRaidAlternateId 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoGpio 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoI2cVoltage 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoUartHwFlowCtrl 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_SerialIoEnableDebugUartAfterPost 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchThermalDeviceEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gKabylakeFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gKabylakeFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gKabylakeFspPkgTokenSpaceGuid_PchDisableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gKabylakeFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gKabylakeFspPkgTokenSpaceGuid_Early8254ClockGatingEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_HybridStorageMode 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gKabylakeFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gSkylakeFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - Skip 5 bytes - $gSkylakeFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gSkylakeFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gSkylakeFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gSkylakeFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - $gSkylakeFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - Skip 3 bytes - $gSkylakeFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gSkylakeFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gKabylakeFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_MeUnconfigIsValid 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - Skip 9 bytes - $gKabylakeFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gKabylakeFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PegMaxPayload 3 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF - $gKabylakeFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gKabylakeFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0A - $gKabylakeFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gKabylakeFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gKabylakeFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gKabylakeFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gKabylakeFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gKabylakeFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gKabylakeFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gKabylakeFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_ApHandoffManner 1 bytes $_DEFAULT_ = 0x02 - Skip 2 bytes - $gKabylakeFspPkgTokenSpaceGuid_ProcTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ProcTraceEnable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ProcTraceMemSize 1 bytes $_DEFAULT_ = 0xFF - Skip 1 bytes - $gKabylakeFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gKabylakeFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_MaxRatio 2 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_StateRatio 80 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4E - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gKabylakeFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gKabylakeFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeDataSize 2 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeData 4 bytes $_DEFAULT_ = 0 - $gKabylakeFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 1 bytes $_DEFAULT_ = 0x00 - $gSkylakeFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gKabylakeFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gKabylakeFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - $gKabylakeFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gKabylakeFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchLockDownRtcLock 1 bytes $_DEFAULT_ = 0x01 - $gKabylakeFspPkgTokenSpaceGuid_PchSbiUnlock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gKabylakeFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gKabylakeFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_PchPmPmcReadDisable 1 bytes $_DEFAULT_ = 0x00 - $gKabylakeFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 2 , "L1" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_GtPllVoltageOffset - Selection 0x0 , "0xFF" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_RefClk - Selection 0 , "Auto" - Selection 1 , "133MHz" - Selection 2 , "100MHz" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership - Selection 0 , "HD-A Link" - Selection 1 , "Shared HD-A Link and I2S Port" - Selection 3 , "I2S Ports" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SaPllVoltageOffset - Selection 0x0 , "0xFF" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLevel - Selection 0 , "TDP Nominal" - Selection 1 , "TDP Down" - Selection 2 , "TDP Up" - Selection 0xFF , "Deactivate" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PkgCStateDemotion - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 0 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ApHandoffManner - Selection 1 , "HALT loop" - Selection 2 , "MWAIT loop" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gSiPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_EnableDts - Selection 0 , "EC" - Selection 1 , "DTS SMM" - Selection 2 , "EC and DTS SMM" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_McPllVoltageOffset - Selection 0x0 , "0xFF" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_GtsVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ProcTraceOutputScheme - Selection 0 , "Single Range Output" - Selection 1 , "ToPA Output" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PkgCStateUnDemotion - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_RingPllVoltageOffset - Selection 0x0 , "0xFF" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SkipMpInit - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_EnableRsr - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_AesEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SataRstRaidAlternateId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_EndOfPostMessage - Selection 0 , "Disable" - Selection 1 , "Send in PEI" - Selection 2 , "Send in DXE" - Selection 3 , "Reserved" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1100 , "1.10 Volts" - Selection 1150 , "1.15 Volts" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 2 , "512 MB" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gSiPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , "HALT loop" - Selection 2 , "MWAIT loop" - Selection 3 , "RUN loop" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_TxtEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gKabylakeFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "KabyLake Platform" -EndInfoBlock - -Page "Memory Reference Code" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gKabylakeFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RcompResistor, "RcompResister settings", HEX, - Help "Indicates RcompReister settings: Board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gKabylakeFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gKabylakeFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gKabylakeFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gKabylakeFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gKabylakeFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gKabylakeFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gKabylakeFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gKabylakeFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gKabylakeFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gKabylakeFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - Combo $gKabylakeFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_EnableTraceHub, "Enable Trace Hub", &EN_DIS, - Help "Enable/disable Trace Hub function." - Combo $gKabylakeFspPkgTokenSpaceGuid_DpSscMarginEnable, "DpSscMarginEnable", &EN_DIS, - Help "Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used on systems that exceeds allowed SSC modulation range as defined in VESA's spec" - Combo $gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gKabylakeFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gKabylakeFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gKabylakeFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gKabylakeFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gKabylakeFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gKabylakeFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto." - Combo $gKabylakeFspPkgTokenSpaceGuid_UserBd, "Board Type", &gKabylakeFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmaTestContentPtr, "MMA Test Content Pointer", HEX, - Help "Pointer to MMA Test Content in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmaTestContentSize, "MMA Test Content Size", HEX, - Help "Size of MMA Test Content in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmaTestConfigPtr, "MMA Test Config Pointer", HEX, - Help "Pointer to MMA Test Config in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmaTestConfigSize, "MMA Test Config Size", HEX, - Help "Size of MMA Test Config in Memory" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gKabylakeFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gKabylakeFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gKabylakeFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gKabylakeFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gKabylakeFspPkgTokenSpaceGuid_RefClk, - Help "Automatic, 100MHz, 133MHz." - Combo $gKabylakeFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gKabylakeFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gKabylakeFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 20" - "Valid range: 0x00 ~ 0x14" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gKabylakeFspPkgTokenSpaceGuid_tWR, "tWR", &gKabylakeFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24" - EditNum $gKabylakeFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gKabylakeFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - Combo $gKabylakeFspPkgTokenSpaceGuid_CmdTriStateDis, "Command Tristate Support", &EN_DIS, - Help "Enable/Disable Command Tristate; 0: Enable; 1: Disable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gKabylakeFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gKabylakeFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gKabylakeFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gKabylakeFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gKabylakeFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gKabylakeFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gKabylakeFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gKabylakeFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gKabylakeFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gKabylakeFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gKabylakeFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gKabylakeFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 3 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gKabylakeFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gKabylakeFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - Combo $gKabylakeFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gKabylakeFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RootPortDev, "PEG root port Device number for Switchable Graphics dGPU", HEX, - Help "Device number to indicate which PEG root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RootPortFun, "PEG root port Function number for Switchable Graphics dGPU", HEX, - Help "Function number to indicate which PEG root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageMode, "GT slice Voltage Mode", &gKabylakeFspPkgTokenSpaceGuid_GtsVoltageMode, - Help "0(Default): Adaptive, 1: Override" - Combo $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gKabylakeFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtsMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0 ~ 60" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtsVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtsExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_EdramRatio, "EDRAM ratio override", HEX, - Help "EdramRatio is deprecated on Kabylake" - "Valid range: 0 ~ 30" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gKabylakeFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This feature is not supported. BIOS is required to disable. 0: Disable" - Combo $gKabylakeFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", DEC, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0 ~ 255" - Combo $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - EditNum $gKabylakeFspPkgTokenSpaceGuid_RingMinOcRatio, "Minimum clr turbo ratio override", DEC, - Help "Minimum clr turbo ratio override. 0: Hardware defaults. Range: 0-255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", DEC, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0 ~ 255" - Combo $gKabylakeFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_CpuRatioOverride, "Enable or Disable CPU Ratio Override", &EN_DIS, - Help "Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. @note If disabled, BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting." - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", DEC, - Help "CPU ratio value. Valid Range 0 to 63" - "Valid range: 0 ~ 63" - Combo $gKabylakeFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gKabylakeFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gKabylakeFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gKabylakeFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gKabylakeFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gKabylakeFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gKabylakeFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Power JTAG in C10 and deeper power states", &EN_DIS, - Help "Power JTAG in C10 and deeper power states; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0 ~ 31" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", DEC, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", DEC, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0 ~ 2000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", DEC, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0 ~ 1000" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", DEC, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0 ~ 63" - Combo $gKabylakeFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio. 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - Combo $gSkylakeFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gSkylakeFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable" - Combo $gSkylakeFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - EditNum $gSkylakeFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gSkylakeFspPkgTokenSpaceGuid_FlashWearOutProtection, "FlashWearOutProtection", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gKabylakeFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gKabylakeFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gKabylakeFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHpetEnable, "PCH HPET Enabled", &EN_DIS, - Help "Enable/disable PCH HPET." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHpetBdfValid, "PCH HPET BDF valid", &EN_DIS, - Help "Whether the BDF value is valid. 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHpetBase, "The HPET Base Address", HEX, - Help "The HPET base address. Default is 0xFED00000." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHpetBusNumber, "PCH HPET Bus Number", HEX, - Help "Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHpetDeviceNumber, "PCH HPET Device Number", HEX, - Help "Device Number HPETn used as Requestor / Completer ID. Default is 0x1F." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHpetFunctionNumber, "PCH HPET Function Number", HEX, - Help "Function Number HPETn used as Requestor / Completer ID. Default is 0x00." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, - Help "Enable PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, - Help "PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, - Help "Original LPC only decodes one byte of port 80h." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchAcpiBase, "PCH Acpi Base", HEX, - Help "Power management I/O base address. Default is 0x1800." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, - Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." - Combo $gKabylakeFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, - Help "Enable SMBus ARP support." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, - Help "SMBUS Base Address (IO space)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, - Help "The number of elements in the RsvdSmbusAddressTable." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TraceHubMemReg0Size, "Trace Hub Memory Region 0", HEX, - Help "Trace Hub Memory Region 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TraceHubMemReg1Size, "Trace Hub Memory Region 1", HEX, - Help "Trace Hub Memory Region 1." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, - Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" -EndPage - -Page "Sunrise Point PCH" - Combo $gKabylakeFspPkgTokenSpaceGuid_AesEnable, "AesEnable", &gKabylakeFspPkgTokenSpaceGuid_AesEnable, - Help "Enable or Disable Advanced Encryption Standard (AES) feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_EnableRsr, "EnableRsr", &gKabylakeFspPkgTokenSpaceGuid_EnableRsr, - Help "Enable or Disable RSR feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_EnableDts, "EnableDts", &gKabylakeFspPkgTokenSpaceGuid_EnableDts, - Help "Policies to obtain CPU temperature. 0: ACPI thermal management uses EC reported temperature values. 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values. 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SmmbaseSwSmiNumber, "SmmbaseSwSmiNumber", HEX, - Help "Software SMI number for handler to save CPU information in SMRAM." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_TxtEnable, "TxtEnable", &gKabylakeFspPkgTokenSpaceGuid_TxtEnable, - Help "Enable or Disable Trusted Execution Technology (TXT) feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_SkipMpInit, "SkipMpInit", &gKabylakeFspPkgTokenSpaceGuid_SkipMpInit, - Help "Silicon Initialization will skip MP Initialization (including BSP) if enabled." - EditNum $gKabylakeFspPkgTokenSpaceGuid_RsvdBits, "RsvdBits", HEX, - Help "Reserved for future use." - "Valid range: 0x0 ~ 0x7FFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, - Help "Enable/disable Azalia controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership, "Select HDAudio IoBuffer Ownership", &gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership, - Help "Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchCio2Enable, "Enable CIO2 Controller", &EN_DIS, - Help "Enable/disable SKYCAM CIO2 Controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS, - Help "Enable/disable eMMC Controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS, - Help "Enable eMMC HS400 Mode." - Combo $gKabylakeFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS, - Help "Enable/disable SD Card Controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "Enable/disable ISH Controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS, - Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post." - EditNum $gKabylakeFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gSiPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gSiPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. " - Combo $gKabylakeFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber", &gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express " - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSiPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express " - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_SsicPortEnable, "Enable XHCI SSIC Enable", &EN_DIS, - Help "Enable/disable XHCI SSIC port." - EditNum $gKabylakeFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoDevMode, "Enable SerialIo Device Mode", HEX, - Help "0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", HEX, - Help "Enable/disable TCO IRQ" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gKabylakeFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gKabylakeFspPkgTokenSpaceGuid_DelayUsbPdoProgramming, "Delay USB PDO Programming", &EN_DIS, - Help "Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: disable, 1: enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqSupport, "Enable PCIE RP CLKREQ Support", HEX, - Help "Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqNumber, "Configure CLKREQ Number", HEX, - Help "Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gKabylakeFspPkgTokenSpaceGuid_WatchDog, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer." - Combo $gKabylakeFspPkgTokenSpaceGuid_AsfEnabled, "ASF Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality." - Combo $gKabylakeFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gKabylakeFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events." - Combo $gKabylakeFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", &EN_DIS, - Help "16 bits Value, Set OS watchdog timer." - Combo $gKabylakeFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", &EN_DIS, - Help "16 bits Value, Set BIOS watchdog timer." - Combo $gKabylakeFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkSrcNumber, "Configure CLKSRC Number", HEX, - Help "Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable, "Force Disable clock ", HEX, - Help "Disables clock even if link is inactive default value is 0" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DefaultSvid, "Subsystem Vendor ID for SA devices", HEX, - Help "Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DefaultSid, "Subsystem Device ID for SA devices", HEX, - Help "Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gKabylakeFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 2(Default)=L1" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gKabylakeFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gKabylakeFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz" - Combo $gKabylakeFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaImguEnable, "Enable/Disable SA IMGU(SKYCAM)", &EN_DIS, - Help "Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM)" - Combo $gKabylakeFspPkgTokenSpaceGuid_GmmEnable, "Enable or disable GMM device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gKabylakeFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Pointer for CpuMpPpi" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled" - Combo $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gKabylakeFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. Default Value = 20A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. Default Value = 5A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. Default Value = 1A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gKabylakeFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gKabylakeFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SendVrMbxCmd1, "Select VR specific mailbox command to send", HEX, - Help "VR specific mailbox commands. 000b - no VR specific command sent. 001b - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue." - "Valid range: 0x0 ~ 0x7" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeMtrrData, "CpuS3ResumeMtrrData", HEX, - Help "Pointer to CPU S3 Resume MTRR Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MicrocodePatchAddress, "MicrocodePatchAddress", HEX, - Help "Pointer to microcode patch that is suitable for this processor." - "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeMtrrDataSize, "CpuS3ResumeMtrrDataSize", HEX, - Help "Size of S3 resume MTRR data." - "Valid range: 0x0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortATermOvrEnable, "Enable SkyCam PortA Termination override", &EN_DIS, - Help "Enable/disable PortA Termination override." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBTermOvrEnable, "Enable SkyCam PortB Termination override", &EN_DIS, - Help "Enable/disable PortB Termination override." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCTermOvrEnable, "Enable SkyCam PortC Termination override", &EN_DIS, - Help "Enable/disable PortC Termination override." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDTermOvrEnable, "Enable SkyCam PortD Termination override", &EN_DIS, - Help "Enable/disable PortD Termination override." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortATrimEnable, "Enable SkyCam PortA Clk Trim", &EN_DIS, - Help "Enable/disable PortA Clk Trim." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBTrimEnable, "Enable SkyCam PortB Clk Trim", &EN_DIS, - Help "Enable/disable PortB Clk Trim." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCTrimEnable, "Enable SkyCam PortC Clk Trim", &EN_DIS, - Help "Enable/disable PortC Clk Trim." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDTrimEnable, "Enable SkyCam PortD Clk Trim", &EN_DIS, - Help "Enable/disable PortD Clk Trim." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleEnable, "Enable SkyCam PortA Ctle", &EN_DIS, - Help "Enable/disable PortA Ctle." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleEnable, "Enable SkyCam PortB Ctle", &EN_DIS, - Help "Enable/disable PortB Ctle." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleEnable, "Enable SkyCam PortCD Ctle", &EN_DIS, - Help "Enable/disable PortCD Ctle." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleCapValue, "Enable SkyCam PortA Ctle Cap Value", HEX, - Help "Enable/disable PortA Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleCapValue, "Enable SkyCam PortB Ctle Cap Value", HEX, - Help "Enable/disable PortB Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleCapValue, "Enable SkyCam PortCD Ctle Cap Value", HEX, - Help "Enable/disable PortCD Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortACtleResValue, "Enable SkyCam PortA Ctle Res Value", HEX, - Help "Enable/disable PortA Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBCtleResValue, "Enable SkyCam PortB Ctle Res Value", HEX, - Help "Enable/disable PortB Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleResValue, "Enable SkyCam PortCD Ctle Res Value", HEX, - Help "Enable/disable PortCD Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortAClkTrimValue, "Enable SkyCam PortA Clk Trim Value", HEX, - Help "Enable/disable PortA Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBClkTrimValue, "Enable SkyCam PortB Clk Trim Value", HEX, - Help "Enable/disable PortB Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCClkTrimValue, "Enable SkyCam PortC Clk Trim Value", HEX, - Help "Enable/disable PortC Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortDClkTrimValue, "Enable SkyCam PortD Clk Trim Value", HEX, - Help "Enable/disable PortD Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortADataTrimValue, "Enable SkyCam Port A Data Trim Value", HEX, - Help "Enable/disable Port A Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortBDataTrimValue, "Enable SkyCam Port B Data Trim Value", HEX, - Help "Enable/disable Port B Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSkyCamPortCDDataTrimValue, "Enable SkyCam C/D Data Trim Value", HEX, - Help "Enable/disable C/D Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchDmiAspm, "Enable DMI ASPM", &EN_DIS, - Help "ASPM on PCH side of the DMI Link." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaIoBufferVoltage, "IO Buffer Voltage", HEX, - Help "I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", HEX, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", HEX, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", HEX, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", HEX, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointDmic, "DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum)", HEX, - Help "0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointBluetooth, "DSP Bluetooth enablement", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspFeatureMask, "Bitmask of supported DSP features", HEX, - Help "[BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspPpModuleMask, "Bitmask of supported DSP Pre/Post-Processing Modules", HEX, - Help "Deprecated: Specific pre/post-processing module bit position must be coherent with the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchHdaDspEndpointI2s, "DSP I2S enablement", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIoApicBdfValid, "Enable PCH Io Apic", &EN_DIS, - Help "Set to 1 if BDF value is valid." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchIoApicBusNumber, "PCH Io Apic Bus Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchIoApicDeviceNumber, "PCH Io Apic Device Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchIoApicFunctionNumber, "PCH Io Apic Function Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0x00." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchIoApicRangeSelect, "PCH Io Apic Range Select", HEX, - Help "Define address bits 19:12 for the IOxAPIC range. Default is 0." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLanK1OffEnable, "Enable PCH Lan use CLKREQ for GbE power management", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLanClkReqSupported, "Indicate whether dedicated CLKREQ# is supported", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchLanClkReqNumber, "CLKREQ# used by GbE", HEX, - Help "Valid if ClkReqSupported is TRUE." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLockDownSpiEiss, "Enable LOCKDOWN SPI Eiss", &EN_DIS, - Help "Enable InSMM.STS (EISS) in SPI." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSubSystemVendorId, "PCH Sub system vendor ID", HEX, - Help "Default Subsystem Vendor ID of the PCH devices. Default is 0x8086." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchSubSystemId, "PCH Sub system ID", HEX, - Help "Default Subsystem ID of the PCH devices. Default is 0x7270." - "Valid range: 0x0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "todo" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpDeviceResetPadActiveHigh, "PCIE RP Device Reset Pad Active High", HEX, - Help "Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gSiPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber, "SerialIo Uart Number Selection", &gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug." - Combo $gSiPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gSiPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, - Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose" - Combo $gKabylakeFspPkgTokenSpaceGuid_EvLoader, "Enable or Disable EV Loader", &EN_DIS, - Help "Enable or Disable EV Loader; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", &gKabylakeFspPkgTokenSpaceGuid_GtPllVoltageOffset, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - Combo $gKabylakeFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", &gKabylakeFspPkgTokenSpaceGuid_RingPllVoltageOffset, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", &gKabylakeFspPkgTokenSpaceGuid_SaPllVoltageOffset, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - Combo $gKabylakeFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", &gKabylakeFspPkgTokenSpaceGuid_McPllVoltageOffset, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - Combo $gKabylakeFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gKabylakeFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - EditNum $gKabylakeFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0 ~ 31" - Combo $gKabylakeFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - EditNum $gKabylakeFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gKabylakeFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gKabylakeFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gKabylakeFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiVc1, "Enable/Disable DmiVc1", &EN_DIS, - Help "Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiVcm, "Enable/Disable DmiVcm", &EN_DIS, - Help "Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gKabylakeFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gKabylakeFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gKabylakeFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gKabylakeFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gKabylakeFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PPCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpDeviceResetPad, "PCIE RP Device Reset Pad", HEX, - Help "The PCH pin assigned to device PERST# signal if available, zero otherwise. See also DeviceResetPadActiveHigh." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gKabylakeFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gKabylakeFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchDciEn, "PCH Dci Enable", &EN_DIS, - Help "Enable/disable PCH Dci." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchDciAutoDetect, "PCH Dci Auto Detect", &EN_DIS, - Help "Deprecated" - Combo $gKabylakeFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, - Help "Disable or Enable Smbus dynamic power gating." - Combo $gKabylakeFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, - Help "Set 1 to clear WDT status, then disable and lock WDT registers." - Combo $gKabylakeFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, - Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." - Combo $gKabylakeFspPkgTokenSpaceGuid_ChipsetInitMessage, "ChipsetInit HECI message", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. If disabled, it prevents from sending ChipsetInit HECI message. " - Combo $gKabylakeFspPkgTokenSpaceGuid_BypassPhySyncReset, "Bypass ChipsetInit sync reset.", &EN_DIS, - Help "0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message." - Combo $gKabylakeFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, - Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4: Memory not preserved across reset, Set ME DID init stat value" - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" - Combo $gKabylakeFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)" - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableHeciRetry, "Retry mechanism for HECI APIs", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable HECI retry." - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable message check." - Combo $gKabylakeFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, - Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." - Combo $gKabylakeFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable KT device." - Combo $gKabylakeFspPkgTokenSpaceGuid_IderDeviceEnable, "Enable IDEr", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable IDEr." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieAllowNoLtrIccPllShutdown, "PCIE Allow No Ltr Icc PLL Shutdown", &EN_DIS, - Help "Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched." - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieDetectTimeoutMs, "PCIE Rp Detect Timeout Ms", HEX, - Help "Will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x0 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS0VmEnable, "PCH Pm Slp S0 Voltage Margining Enable", &EN_DIS, - Help "Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmCapsuleResetType, "PCH Pm Capsule Reset Type", &EN_DIS, - Help "Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPort61hEnable, "PCH Port 61h Config Enable/Disable", &EN_DIS, - Help "Used for the emulation feature for Port61h read. The port is trapped and the SMI handler will toggle bit4 according to the handler's internal state." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gKabylakeFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstRaidAlternateId, "PCH Sata Rst Raid Alternate Id", &gKabylakeFspPkgTokenSpaceGuid_SataRstRaidAlternateId, - Help "Enable RAID Alternate ID." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS, - Help "Determine if HS400 Training is required." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS, - Help "Set if HS400 Tuning Data Valid." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX, - Help "Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX, - Help "Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", HEX, - Help "I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SerialIoGpio, "Enable Pch Serial IO GPIO", &EN_DIS, - Help "Determines if enable Serial IO GPIO." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoI2cVoltage, "IO voltage for I2C controllers", HEX, - Help "Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. Note: I2C 2/3/4/5 does not support 3.3V (only 1.8V), due to GPIO GPP_F limitation" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity, "SPI ChipSelect signal polarity", HEX, - Help "Selects SPI ChipSelect signal polarity." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoUartHwFlowCtrl, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS linesh." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", HEX, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoEnableDebugUartAfterPost, "Enable Debug UART Controller", HEX, - Help "Enable debug UART controller after post." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", HEX, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchThermalDeviceEnable, "Enable Thermal Device", &EN_DIS, - Help "Enable Thermal Device." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gKabylakeFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gKabylakeFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", HEX, - Help "Thermal Sensor 0 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", HEX, - Help "Thermal Sensor 1 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", HEX, - Help "Thermal Sensor 2 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", HEX, - Help "Thermal Sensor 3 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gKabylakeFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchDisableComplianceMode, "Disable XHCI Compliance Mode", &EN_DIS, - Help "This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled." - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_Early8254ClockGatingEnable, "Enable 8254 Static Clock Gating in early POST time", &EN_DIS, - Help "Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this." - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH SATA RST CPU attached storage", &EN_DIS, - Help "RST CPU attached storage" - Combo $gKabylakeFspPkgTokenSpaceGuid_HybridStorageMode, "Hybrid Storage Mode", &EN_DIS, - Help "Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - EditNum $gSkylakeFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "Enable/Disable ME Unconfig on RTC clear", &EN_DIS, - Help "Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear" - Combo $gKabylakeFspPkgTokenSpaceGuid_MeUnconfigIsValid, "Check if MeUnconfigOnRtcClear is valid", &EN_DIS, - Help "The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear." - EditNum $gKabylakeFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0x7" - Combo $gKabylakeFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7 ", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gKabylakeFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gKabylakeFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gKabylakeFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gKabylakeFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gKabylakeFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gKabylakeFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gKabylakeFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled)" - Combo $gKabylakeFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gKabylakeFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gKabylakeFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", DEC, - Help "1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", DEC, - Help "2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", DEC, - Help "3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", DEC, - Help "4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - Combo $gKabylakeFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gKabylakeFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy in milliseconds. Valid values are 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", DEC, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0 ~ 100" - Combo $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is 10, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gKabylakeFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gKabylakeFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128" - "Valid range: 0x00 ~ 0x80" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128" - "Valid range: 0x00 ~ 0x80" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128" - "Valid range: 0x00 ~ 0x80" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Enable or Disable processor debug features", &EN_DIS, - Help "Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gKabylakeFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gKabylakeFspPkgTokenSpaceGuid_ApHandoffManner, "Settings for AP Handoff to OS", &gKabylakeFspPkgTokenSpaceGuid_ApHandoffManner, - Help "Settings for AP Handoff to OS; 1: HALT loop; 2: MWAIT loop." - Combo $gKabylakeFspPkgTokenSpaceGuid_ProcTraceOutputScheme, "Control on Processor Trace output scheme", &gKabylakeFspPkgTokenSpaceGuid_ProcTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gKabylakeFspPkgTokenSpaceGuid_ProcTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_ProcTraceMemSize, "Memory region allocation for Processor Trace", HEX, - Help "Memory region allocation for Processor Trace, Total Memory required is up to requested value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace, PcdFspReservedMemoryLength must be increased by the total memory required, and PlatformMemorySize policy must also be increased by the total memory required over 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &EN_DIS, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package C-State Demotion", &gKabylakeFspPkgTokenSpaceGuid_PkgCStateDemotion, - Help "Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake)" - Combo $gKabylakeFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package C-State UnDemotion", &gKabylakeFspPkgTokenSpaceGuid_PkgCStateUnDemotion, - Help "Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake)" - Combo $gKabylakeFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gKabylakeFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - Combo $gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", &gKabylakeFspPkgTokenSpaceGuid_ConfigTdpLevel, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up; 0xFF: Deactivate" - Combo $gKabylakeFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gKabylakeFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio , Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gKabylakeFspPkgTokenSpaceGuid_StateRatio, "Maximum P-state ratio to use in the custom P-state table", HEX, - Help "Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates) , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF, Default is 0x4E, Server Platform is 0x4B" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF, Default is 0x76, Server Platform is 0x6B" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", DEC, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", DEC, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", DEC, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", DEC, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", DEC, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", DEC, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", DEC, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", DEC, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", DEC, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", DEC, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", DEC, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", DEC, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0 ~ 4095875" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeDataSize, "CpuS3ResumeDataSize", HEX, - Help "Size of CPU S3 Resume Data" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_CpuS3ResumeData, "CpuS3ResumeData", HEX, - Help "Pointer to CPU S3 Resume Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", DEC, - Help "5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", DEC, - Help "6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", DEC, - Help "7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - EditNum $gKabylakeFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", DEC, - Help "8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0 ~ 255" - Combo $gKabylakeFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gKabylakeFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gKabylakeFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gSkylakeFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &gKabylakeFspPkgTokenSpaceGuid_EndOfPostMessage, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI" - Combo $gKabylakeFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, - Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX, - Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, - Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchLockDownRtcLock, "RTC CMOS RAM LOCK", &EN_DIS, - Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSbiUnlock, "PCH Sbi lock bit", &EN_DIS, - Help "This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Psf lock bit", &EN_DIS, - Help "The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 5." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, - Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." - EditNum $gKabylakeFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, - Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." - "Valid range: 0x0 ~ 0xFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Pm Disable Energy Report", &EN_DIS, - Help "Disable/Enable PCH to CPU enery report feature." - Combo $gKabylakeFspPkgTokenSpaceGuid_PchPmPmcReadDisable, "PCH Pm Pmc Read Disable", &EN_DIS, - Help "Deprecated" - Combo $gKabylakeFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, - Help "Allow entrance to the PCH SATA test modes." -EndPage - -Page "Kabylake System Agent" - EditNum $gKabylakeFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gKabylakeFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gKabylakeFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "Enable/disable Device 4" - Combo $gKabylakeFspPkgTokenSpaceGuid_SaGv, "SA GV", &gKabylakeFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." -EndPage - diff --git a/AmberLakeFspBinPkg/Fsp.fd b/AmberLakeFspBinPkg/Fsp.fd deleted file mode 100644 index 9aefb199e48f6a08bf1531754e9a254b09d4a271..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 618496 zcmeFZ2Ut^0wq_d_5y8d_WI z+sDMZ8I53LN8$JDn}Rm{DlJnC6au9f&WbE&|!c^Y_M}OMWQ$}keWaY z65w~2G0A|(-39Z*>`Q>VD7bGYd4`a{ePj&|fm($JO@9;#1mf8CBZo+bK#Mo{!DFM= z?%?)E(M2Gtwg-56`+BU-0na4?dg1$@i!K78pAV~NNB~^&;oc!wBqJ+j%)fP@SWwE* zS_b$f5_>+NC~8FLAcKU*ThOxs`;>AFWe!1NqZ;5v50xFF%%MmebYU2aCVY7b)Kr%Q z;OK1Nky0!QA4pK%jSR@zT zhAsd|q?TimqIfXjq1%94aV3{W&*&+4(>1vwsJfG zrBqx7u%n4omVCetqU_I&e`*WlgQ2J_pgV9KRUf?y3$X*FY^N$wL($X@rDk_G=Q8VyE_jTc%8Wg< zdmplKC2Em{EE>ZgaZ?x!5++&)*t7x3{w=Iycc=ouM=herqM(yJ0u$wha-?ek)?Y3R$4E26(9#Rq>rJRV9IQvQOFDj5x7*EXD2Km0%mpsGUNNoLS66VS_X*uzq7!8 zAVE1vIaT?w@?R+wO8W3MHZkbHE4Q0ZZN3@!ZUcT!l?yQ^%7xen3lYfA`mbaD_8Eyp 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--- a/AmberLakeFspBinPkg/FspPcds.dsc +++ /dev/null @@ -1,40 +0,0 @@ -## @file -# FSP description for DynamicEx PCDs. -# -# @copyright -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xE0000000 - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000 - - ## Specifies the base address of the first microcode Patch in the microcode Region. - # @Prompt Microcode Region base address. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - - ## Specifies the AP target C-state for Mwait during POST phase. - # The default value 0 means C1 state. - # The value is defined as below.

- # @Prompt The specified AP target C-state for Mwait. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 - diff --git a/AmberLakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h b/AmberLakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h deleted file mode 100644 index 6c5d331..0000000 --- a/AmberLakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h +++ /dev/null @@ -1,84 +0,0 @@ -/** @file - FSP CPU Data Config Block. - - @copyright - Copyright (c) 2016, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _CPU_CONFIG_FSP_DATA_H_ -#define _CPU_CONFIG_FSP_DATA_H_ - -#pragma pack (push,1) -typedef union { - struct { - /** - Enable or Disable Advanced Encryption Standard (AES) feature. - For some countries, this should be disabled for legal reasons. - - 0: Disable - - 1: Enable - **/ - UINT32 AesEnable : 1; - /** - Processor Early Power On Configuration FCLK setting. - - 0: 800 MHz (ULT/ULX). - - 1: 1 GHz (DT/Halo). Not supported on ULT/ULX. - - 2: 400 MHz. - - 3: Reserved. - **/ - UINT32 FClkFrequency : 2; - UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; 1: Enable - /** - Policies to obtain CPU temperature. - - 0: ACPI thermal management uses EC reported temperature values. - - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values. - - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition. - **/ - UINT32 EnableDts : 2; - UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM. - /** - Enable or Disable Virtual Machine Extensions (VMX) feature. - - 0: Disable - - 1: Enable - **/ - UINT32 VmxEnable : 1; - /** - Enable or Disable Trusted Execution Technology (TXT) feature. - - 0: Disable - - 1: Enable - **/ - UINT32 TxtEnable : 1; - UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. - UINT32 RsvdBits : 15; ///< Reserved for future use - UINT32 Reserved; - } Bits; - UINT32 Uint32[2]; - } CPU_CONFIG_FSP_DATA; - -#pragma pack (pop) - -#endif // _CPU_CONFIG_FSP_DATA_H_ diff --git a/AmberLakeFspBinPkg/Include/FspUpd.h b/AmberLakeFspBinPkg/Include/FspUpd.h deleted file mode 100644 index c296011..0000000 --- a/AmberLakeFspBinPkg/Include/FspUpd.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - - @copyright - Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C424B /* 'KBLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C424B /* 'KBLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C424B /* 'KBLUPD_S' */ - -#pragma pack() - -#endif diff --git a/AmberLakeFspBinPkg/Include/FspmUpd.h b/AmberLakeFspBinPkg/Include/FspmUpd.h deleted file mode 100644 index 9afb7b0..0000000 --- a/AmberLakeFspBinPkg/Include/FspmUpd.h +++ /dev/null @@ -1,1722 +0,0 @@ -/** @file - - @copyright - Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; - UINT8 Rsvd[3]; - UINT16 MeChipInitCrc; - UINT16 BiosChipInitCrc; -} SI_CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data in Memory -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data in Memory -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data in Memory -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data in Memory -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResister settings - Indicates RcompReister settings: Board-dependent -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: board-dependent -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0096 -**/ - UINT8 UnusedUpdSpace0[2]; - -/** Offset 0x0098 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x009C - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A0 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A2 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A3 -**/ - UINT8 UnusedUpdSpace1[2]; - -/** Offset 0x00A5 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x00A6 - Enable Trace Hub - Enable/disable Trace Hub function. - $EN_DIS -**/ - UINT8 EnableTraceHub; - -/** Offset 0x00A7 - DpSscMarginEnable - Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down - spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used - on systems that exceeds allowed SSC modulation range as defined in VESA's spec - $EN_DIS -**/ - UINT8 DpSscMarginEnable; - -/** Offset 0x00A8 -**/ - UINT8 UnusedUpdSpace2[59]; - -/** Offset 0x00E3 - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00E4 - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00E5 - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00E6 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00E7 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00E8 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, - 2133, 2400 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00EA - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00EB -**/ - UINT8 UnusedUpdSpace3[105]; - -/** Offset 0x0154 - MMA Test Content Pointer - Pointer to MMA Test Content in Memory -**/ - UINT32 MmaTestContentPtr; - -/** Offset 0x0158 - MMA Test Content Size - Size of MMA Test Content in Memory -**/ - UINT32 MmaTestContentSize; - -/** Offset 0x015C - MMA Test Config Pointer - Pointer to MMA Test Config in Memory -**/ - UINT32 MmaTestConfigPtr; - -/** Offset 0x0160 - MMA Test Config Size - Size of MMA Test Config in Memory -**/ - UINT32 MmaTestConfigSize; - -/** Offset 0x0164 -**/ - UINT8 UnusedUpdSpace4[19]; - -/** Offset 0x0177 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x0178 - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1100:1.10 Volts, 1150:1.15 Volts, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 - Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 - Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x017A - Memory Reference Clock - Automatic, 100MHz, 133MHz. - 0:Auto, 1:133MHz, 2:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x017B - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x017C - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x017D - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x017E - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x0180 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x0182 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 20 -**/ - UINT8 tCWL; - -/** Offset 0x0183 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x0184 - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x0186 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x0188 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x0189 - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x018A - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24 -**/ - UINT8 tWR; - -/** Offset 0x018B - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x018C - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x018D - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x018E - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x018F - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x0190 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x0191 - Command Tristate Support - Enable/Disable Command Tristate; 0: Enable; 1: Disable. - $EN_DIS -**/ - UINT8 CmdTriStateDis; - -/** Offset 0x0192 -**/ - UINT8 UnusedUpdSpace5[14]; - -/** Offset 0x01A0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x01A4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x01A8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x01AC - HECI Timeouts - Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x01AD -**/ - UINT8 UnusedUpdSpace6[115]; - -/** Offset 0x0220 - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x0222 - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x0224 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x0227 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x0228 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x0229 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x022A - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x022B - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x022C - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x022D - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x022E - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x022F - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x0230 - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0231 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0232 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0234 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0235 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[4]; - -/** Offset 0x0239 - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[4]; - -/** Offset 0x023D - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[4]; - -/** Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 3 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[2]; - -/** Offset 0x0243 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0244 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[8]; - -/** Offset 0x024C - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0250 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[16]; - -/** Offset 0x0260 -**/ - UINT8 UnusedUpdSpace7[1]; - -/** Offset 0x0261 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[3]; - -/** Offset 0x0264 - Temporary MMIO address for GTTMMADR - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT32 GttMmAdr; - -/** Offset 0x0268 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x026A - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x026B - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0283 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x029B - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU - Device number to indicate which PEG root port has dGPU -**/ - UINT8 RootPortDev; - -/** Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU - Function number to indicate which PEG root port has dGPU -**/ - UINT8 RootPortFun; - -/** Offset 0x02B5 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x02B6 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x02B7 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtsVoltageMode; - -/** Offset 0x02B8 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x02B9 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtsMaxOcRatio; - -/** Offset 0x02BA - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtsVoltageOffset; - -/** Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtsVoltageOverride; - -/** Offset 0x02BE - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtsExtraTurboVoltage; - -/** Offset 0x02C0 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x02C4 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x02C6 - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x02C8 - EDRAM ratio override - EdramRatio is deprecated on Kabylake -**/ - UINT8 EdramRatio; - -/** Offset 0x02C9 - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x02CA - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x02CB - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x02CC - C6DRAM power gating feature - This feature is not supported. BIOS is required to disable. 0: Disable - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x02CD - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x02CE - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x02CF - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x02D0 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x02D1 - Minimum clr turbo ratio override - Minimum clr turbo ratio override. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMinOcRatio; - -/** Offset 0x02D2 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x02D3 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x02D4 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. @note If disabled, - BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. - $EN_DIS -**/ - UINT8 CpuRatioOverride; - -/** Offset 0x02D5 - CPU ratio value - CPU ratio value. Valid Range 0 to 63 -**/ - UINT8 CpuRatio; - -/** Offset 0x02D6 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x02D7 - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x02D8 - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x02D9 - Power JTAG in C10 and deeper power states - Power JTAG in C10 and deeper power states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x02DA - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x02DB - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x02DC - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x02DE - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x02E0 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x02E2 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x02E3 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x02E4 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x02E5 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x02E6 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable - $EN_DIS -**/ - UINT8 EnableSgx; - -/** Offset 0x02E7 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x02E8 - PrmrrSize - Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable -**/ - UINT32 PrmrrSize; - -/** Offset 0x02EC - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x02F0 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x02F8 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x02FC - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0300 - FlashWearOutProtection - Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable - $EN_DIS -**/ - UINT8 FlashWearOutProtection; - -/** Offset 0x0301 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0302 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0303 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[7]; - -/** Offset 0x030A - PCH HPET Enabled - Enable/disable PCH HPET. - $EN_DIS -**/ - UINT8 PchHpetEnable; - -/** Offset 0x030B - PCH HPET BDF valid - Whether the BDF value is valid. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchHpetBdfValid; - -/** Offset 0x030C - The HPET Base Address - The HPET base address. Default is 0xFED00000. -**/ - UINT32 PchHpetBase; - -/** Offset 0x0310 - PCH HPET Bus Number - Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchHpetBusNumber; - -/** Offset 0x0311 - PCH HPET Device Number - Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchHpetDeviceNumber; - -/** Offset 0x0312 - PCH HPET Function Number - Function Number HPETn used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchHpetFunctionNumber; - -/** Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x032B - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0343 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x035B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x0373 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x038B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x03A3 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x03BB - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x03D3 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x03EB - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0403 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x041B - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0433 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x044B - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x0463 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x046B - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x0473 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x047B - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x0483 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x048B - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x0493 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x049B - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x04A3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x04AB - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x04B3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x04BB - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x04C3 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x04CB - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x04D3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x04DB - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x04E3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x04EB - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x04F4 - PCH Acpi Base - Power management I/O base address. Default is 0x1800. -**/ - UINT16 PchAcpiBase; - -/** Offset 0x04F6 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x04F7 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x04F8 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x04FA - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x04FB -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x04FC - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0500 - Trace Hub Memory Region 0 - Trace Hub Memory Region 0. -**/ - UINT32 TraceHubMemReg0Size; - -/** Offset 0x0504 - Trace Hub Memory Region 1 - Trace Hub Memory Region 1. -**/ - UINT32 TraceHubMemReg1Size; - -/** Offset 0x0508 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x050C - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x050D - SerialIo Uart Number Selection - Select SerialIo Uart Controller for debug. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x050E - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x050F - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0510 - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x0511 - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x0512 - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x0513 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x0514 - Enable or Disable EV Loader - Enable or Disable EV Loader; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 EvLoader; - -/** Offset 0x0515 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 - 0x0:0xFF -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0516 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 - 0x0:0xFF -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0517 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 - 0x0:0xFF -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0518 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 - 0x0:0xFF -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0519 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x051A - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x051B - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x051C - TjMax Offset - TjMax offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x051D -**/ - UINT8 ReservedFspmUpd[3]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0520 -**/ - UINT32 Signature; - -/** Offset 0x0524 - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x0525 - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0527 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0528 - Enable/Disable DmiVc1 - Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0 - $EN_DIS -**/ - UINT8 DmiVc1; - -/** Offset 0x0529 - Enable/Disable DmiVcm - Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0 - $EN_DIS -**/ - UINT8 DmiVcm; - -/** Offset 0x052A - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x052B - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x052C - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0539 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x053A -**/ - UINT8 UnusedUpdSpace9[6]; - -/** Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0541 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0542 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0543 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x0544 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[16]; - -/** Offset 0x0554 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[16]; - -/** Offset 0x0564 - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[16]; - -/** Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x057C - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[4]; - -/** Offset 0x0580 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT64 BiosAcmBase; - -/** Offset 0x0588 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x058C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0590 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0598 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x05A0 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x05A2 - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x05A4 - PCH Dci Enable - Enable/disable PCH Dci. - $EN_DIS -**/ - UINT8 PchDciEn; - -/** Offset 0x05A5 - PCH Dci Auto Detect - Deprecated - $EN_DIS -**/ - UINT8 PchDciAutoDetect; - -/** Offset 0x05A6 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x05A7 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x05A8 - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x05A9 - ChipsetInit HECI message - Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. - If disabled, it prevents from sending ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x05AA - Bypass ChipsetInit sync reset. - 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x05AB - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4: - Memory not preserved across reset, Set ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05AC - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05AD - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05AE - Retry mechanism for HECI APIs - Test, 0: disable, 1: enable, Enable/Disable HECI retry. - $EN_DIS -**/ - UINT8 DisableHeciRetry; - -/** Offset 0x05AF - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05B0 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05B1 - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05B2 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05B3 - Enable IDEr - Test, 0: disable, 1: enable, Enable or Disable IDEr. - $EN_DIS -**/ - UINT8 IderDeviceEnable; - -/** Offset 0x05B4 -**/ - UINT8 ReservedFspmTestUpd[12]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0520 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x05C0 -**/ - UINT8 UnusedUpdSpace10[134]; - -/** Offset 0x0646 -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/AmberLakeFspBinPkg/Include/FspsUpd.h b/AmberLakeFspBinPkg/Include/FspsUpd.h deleted file mode 100644 index 2ceba58..0000000 --- a/AmberLakeFspBinPkg/Include/FspsUpd.h +++ /dev/null @@ -1,3021 +0,0 @@ -/** @file - - @copyright - Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -#include -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D - Enable Intel HD Audio (Azalia) - Enable/disable Azalia controller. - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x002E - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x002F - Select HDAudio IoBuffer Ownership - Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / - I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link - owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 - of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports - own all the I/O buffers. - 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports -**/ - UINT8 PchHdaIoBufferOwnership; - -/** Offset 0x0030 - Enable CIO2 Controller - Enable/disable SKYCAM CIO2 Controller. - $EN_DIS -**/ - UINT8 PchCio2Enable; - -/** Offset 0x0031 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0032 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0033 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0034 - Enable PCH ISH Controller - Enable/disable ISH Controller. - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0035 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x0036 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x0037 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0038 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x003C - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0040 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0041 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0042 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x004A - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0052 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0062 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x006C - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x006D - Enable XHCI SSIC Enable - Enable/disable XHCI SSIC port. - $EN_DIS -**/ - UINT8 SsicPortEnable; - -/** Offset 0x006E -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x006F - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0074 - Enable SerialIo Device Mode - 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable - SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode - respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. -**/ - UINT8 SerialIoDevMode[11]; - -/** Offset 0x007F - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0087 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0088 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0089 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x008A - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x008B - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x008C - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x0090 -**/ - UINT8 UnusedUpdSpace2; - -/** Offset 0x0091 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x0092 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0093 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x00A3 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x00FB - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x00FC - Delay USB PDO Programming - Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: - disable, 1: enable - $EN_DIS -**/ - UINT8 DelayUsbPdoProgramming; - -/** Offset 0x00FD -**/ - UINT8 UnusedUpdSpace3[23]; - -/** Offset 0x0114 - Enable PCIE RP CLKREQ Support - Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for - each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqSupport[24]; - -/** Offset 0x012C - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can - be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqNumber[24]; - -/** Offset 0x0144 -**/ - UINT8 UnusedUpdSpace4[5]; - -/** Offset 0x0149 - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x014A -**/ - UINT8 UnusedUpdSpace5[9]; - -/** Offset 0x0153 - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x0154 - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. - $EN_DIS -**/ - UINT8 WatchDog; - -/** Offset 0x0155 - ASF Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. - $EN_DIS -**/ - UINT8 AsfEnabled; - -/** Offset 0x0156 - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x0157 - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0158 - OS Timer - 16 bits Value, Set OS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x015A - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x015C - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x015D - Configure CLKSRC Number - Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid - clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for - port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkSrcNumber[24]; - -/** Offset 0x0175 - Force Disable clock - Disables clock even if link is inactive default value is 0 -**/ - UINT8 PcieRpForceClkDisableWhenRpDisable[24]; - -/** Offset 0x018D -**/ - UINT8 UnusedUpdSpace6[115]; - -/** Offset 0x0200 - Subsystem Vendor ID for SA devices - Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086 -**/ - UINT16 DefaultSvid; - -/** Offset 0x0202 - Subsystem Device ID for SA devices - Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015 -**/ - UINT16 DefaultSid; - -/** Offset 0x0204 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x0205 - DMI ASPM - 0=Disable, 2(Default)=L1 - 0:Disable, 2:L1 -**/ - UINT8 DmiAspm; - -/** Offset 0x0206 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[3]; - -/** Offset 0x020C - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[3]; - -/** Offset 0x020F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[3]; - -/** Offset 0x0212 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[3]; - -/** Offset 0x0215 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0216 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) - Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) - $EN_DIS -**/ - UINT8 SaImguEnable; - -/** Offset 0x0219 - Enable or disable GMM device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GmmEnable; - -/** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x021B -**/ - UINT8 UnusedUpdSpace7[1]; - -/** Offset 0x021C - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[2]; - -/** Offset 0x0224 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0225 -**/ - UINT8 UnusedUpdSpace8[18]; - -/** Offset 0x0237 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[15]; - -/** Offset 0x0246 - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x024A - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x024E - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x0253 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x0258 - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x025D - Imon offset correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x0262 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x0267 - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x026C - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x0271 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x0276 - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x0277 - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x0278 - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x027D -**/ - UINT8 UnusedUpdSpace9[9]; - -/** Offset 0x0286 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x0290 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0294 -**/ - UINT8 UnusedUpdSpace10[4]; - -/** Offset 0x0298 - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x02A2 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x02AC - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is - 0-128A. Default Value = 20A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x02B6 - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is - 0-128A. Default Value = 5A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x02C0 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is - 0-128A. Default Value = 1A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x02CA - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x02D4 - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x02DE -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x02E1 -**/ - UINT8 UnusedUpdSpace12; - -/** Offset 0x02E2 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x02E3 - Select VR specific mailbox command to send - VR specific mailbox commands. 000b - no VR specific command sent. 001b - - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific - command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue. -**/ - UINT8 SendVrMbxCmd1; - -/** Offset 0x02E4 - CpuS3ResumeMtrrData - Pointer to CPU S3 Resume MTRR Data -**/ - UINT32 CpuS3ResumeMtrrData; - -/** Offset 0x02E8 - Cpu Configuration - Cpu Configuration data. -**/ - CPU_CONFIG_FSP_DATA CpuConfig; - -/** Offset 0x02F0 - MicrocodePatchAddress - Pointer to microcode patch that is suitable for this processor. - 0:Disable, 1:Enable -**/ - UINT64 MicrocodePatchAddress; - -/** Offset 0x02F8 - CpuS3ResumeMtrrDataSize - Size of S3 resume MTRR data. -**/ - UINT16 CpuS3ResumeMtrrDataSize; - -/** Offset 0x02FA -**/ - UINT8 UnusedUpdSpace13; - -/** Offset 0x02FB - Enable SkyCam PortA Termination override - Enable/disable PortA Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortATermOvrEnable; - -/** Offset 0x02FC - Enable SkyCam PortB Termination override - Enable/disable PortB Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortBTermOvrEnable; - -/** Offset 0x02FD - Enable SkyCam PortC Termination override - Enable/disable PortC Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortCTermOvrEnable; - -/** Offset 0x02FE - Enable SkyCam PortD Termination override - Enable/disable PortD Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortDTermOvrEnable; - -/** Offset 0x02FF - Enable SkyCam PortA Clk Trim - Enable/disable PortA Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortATrimEnable; - -/** Offset 0x0300 - Enable SkyCam PortB Clk Trim - Enable/disable PortB Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortBTrimEnable; - -/** Offset 0x0301 - Enable SkyCam PortC Clk Trim - Enable/disable PortC Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortCTrimEnable; - -/** Offset 0x0302 - Enable SkyCam PortD Clk Trim - Enable/disable PortD Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortDTrimEnable; - -/** Offset 0x0303 - Enable SkyCam PortA Ctle - Enable/disable PortA Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortACtleEnable; - -/** Offset 0x0304 - Enable SkyCam PortB Ctle - Enable/disable PortB Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortBCtleEnable; - -/** Offset 0x0305 - Enable SkyCam PortCD Ctle - Enable/disable PortCD Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortCDCtleEnable; - -/** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value - Enable/disable PortA Ctle Cap Value. -**/ - UINT8 PchSkyCamPortACtleCapValue; - -/** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value - Enable/disable PortB Ctle Cap Value. -**/ - UINT8 PchSkyCamPortBCtleCapValue; - -/** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value - Enable/disable PortCD Ctle Cap Value. -**/ - UINT8 PchSkyCamPortCDCtleCapValue; - -/** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value - Enable/disable PortA Ctle Res Value. -**/ - UINT8 PchSkyCamPortACtleResValue; - -/** Offset 0x030A - Enable SkyCam PortB Ctle Res Value - Enable/disable PortB Ctle Res Value. -**/ - UINT8 PchSkyCamPortBCtleResValue; - -/** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value - Enable/disable PortCD Ctle Res Value. -**/ - UINT8 PchSkyCamPortCDCtleResValue; - -/** Offset 0x030C - Enable SkyCam PortA Clk Trim Value - Enable/disable PortA Clk Trim Value. -**/ - UINT8 PchSkyCamPortAClkTrimValue; - -/** Offset 0x030D - Enable SkyCam PortB Clk Trim Value - Enable/disable PortB Clk Trim Value. -**/ - UINT8 PchSkyCamPortBClkTrimValue; - -/** Offset 0x030E - Enable SkyCam PortC Clk Trim Value - Enable/disable PortC Clk Trim Value. -**/ - UINT8 PchSkyCamPortCClkTrimValue; - -/** Offset 0x030F - Enable SkyCam PortD Clk Trim Value - Enable/disable PortD Clk Trim Value. -**/ - UINT8 PchSkyCamPortDClkTrimValue; - -/** Offset 0x0310 - Enable SkyCam Port A Data Trim Value - Enable/disable Port A Data Trim Value. -**/ - UINT16 PchSkyCamPortADataTrimValue; - -/** Offset 0x0312 - Enable SkyCam Port B Data Trim Value - Enable/disable Port B Data Trim Value. -**/ - UINT16 PchSkyCamPortBDataTrimValue; - -/** Offset 0x0314 - Enable SkyCam C/D Data Trim Value - Enable/disable C/D Data Trim Value. -**/ - UINT16 PchSkyCamPortCDDataTrimValue; - -/** Offset 0x0316 - Enable DMI ASPM - ASPM on PCH side of the DMI Link. - $EN_DIS -**/ - UINT8 PchDmiAspm; - -/** Offset 0x0317 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0318 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x031D - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x0322 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x032C - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0336 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0337 - IO Buffer Voltage - I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V. -**/ - UINT8 PchHdaIoBufferVoltage; - -/** Offset 0x0338 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0339 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz. -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x033A - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x033B - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x033D - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) - 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array. -**/ - UINT8 PchHdaDspEndpointDmic; - -/** Offset 0x033F - DSP Bluetooth enablement - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchHdaDspEndpointBluetooth; - -/** Offset 0x0340 - Bitmask of supported DSP features - [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation. -**/ - UINT32 PchHdaDspFeatureMask; - -/** Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules - Deprecated: Specific pre/post-processing module bit position must be coherent with - the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing - Module Support. -**/ - UINT32 PchHdaDspPpModuleMask; - -/** Offset 0x0348 - DSP I2S enablement - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchHdaDspEndpointI2s; - -/** Offset 0x0349 - Enable PCH Io Apic - Set to 1 if BDF value is valid. - $EN_DIS -**/ - UINT8 PchIoApicBdfValid; - -/** Offset 0x034A - PCH Io Apic Bus Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchIoApicBusNumber; - -/** Offset 0x034B - PCH Io Apic Device Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchIoApicDeviceNumber; - -/** Offset 0x034C - PCH Io Apic Function Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchIoApicFunctionNumber; - -/** Offset 0x034D - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x034E - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x034F - PCH Io Apic Range Select - Define address bits 19:12 for the IOxAPIC range. Default is 0. -**/ - UINT8 PchIoApicRangeSelect; - -/** Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x035E - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanK1OffEnable; - -/** Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanClkReqSupported; - -/** Offset 0x0362 - CLKREQ# used by GbE - Valid if ClkReqSupported is TRUE. -**/ - UINT8 PchLanClkReqNumber; - -/** Offset 0x0363 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x0364 - Enable LOCKDOWN SPI Eiss - Enable InSMM.STS (EISS) in SPI. - $EN_DIS -**/ - UINT8 PchLockDownSpiEiss; - -/** Offset 0x0365 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x0366 - PCH Sub system vendor ID - Default Subsystem Vendor ID of the PCH devices. Default is 0x8086. -**/ - UINT16 PchSubSystemVendorId; - -/** Offset 0x0368 - PCH Sub system ID - Default Subsystem ID of the PCH devices. Default is 0x7270. -**/ - UINT16 PchSubSystemId; - -/** Offset 0x036A - PCH Legacy IO Low Latency Enable - todo - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x036B -**/ - UINT8 UnusedUpdSpace14[5]; - -/** Offset 0x0370 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x0388 - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03A0 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x03D0 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x03E8 - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0400 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x0418 - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0430 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x0448 - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x0460 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x0490 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04A8 - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x04C0 - PCIE RP Device Reset Pad Active High - Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad. -**/ - UINT8 PcieRpDeviceResetPadActiveHigh[24]; - -/** Offset 0x04D8 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; - 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x0508 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0520 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x0538 - PCIE RP Device Reset Pad - The PCH pin assigned to device PERST# signal if available, zero otherwise. See - also DeviceResetPadActiveHigh. -**/ - UINT32 PcieRpDeviceResetPad[24]; - -/** Offset 0x0598 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x05B0 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05C8 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05E0 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x0628 - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x062D - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0632 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0633 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown - Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable - or leaving untouched. - $EN_DIS -**/ - UINT8 PcieAllowNoLtrIccPllShutdown; - -/** Offset 0x0635 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0636 - PCIE Rp Detect Timeout Ms - Will wait for link to exit Detect state for enabled ports before assuming there - is no device and potentially disabling the port. -**/ - UINT16 PcieDetectTimeoutMs; - -/** Offset 0x0638 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0639 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable - Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. - $EN_DIS -**/ - UINT8 PchPmSlpS0VmEnable; - -/** Offset 0x063B -**/ - UINT8 UnusedUpdSpace15[5]; - -/** Offset 0x0640 - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x0641 - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x0642 - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0643 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0644 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0645 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0646 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0647 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0648 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0649 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x064A -**/ - UINT8 UnusedUpdSpace16[6]; - -/** Offset 0x0650 - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x0651 - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x0652 - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x0653 - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0655 - PCH Pm Capsule Reset Type - Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset. - $EN_DIS -**/ - UINT8 PchPmCapsuleResetType; - -/** Offset 0x0656 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0657 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0658 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0659 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x065A - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x065B -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x065C - PCH Port 61h Config Enable/Disable - Used for the emulation feature for Port61h read. The port is trapped and the SMI - handler will toggle bit4 according to the handler's internal state. - $EN_DIS -**/ - UINT8 PchPort61hEnable; - -/** Offset 0x065D - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x065E - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x065F - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0660 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0668 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0670 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0678 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0680 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0688 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0690 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0698 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x06A8 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidAlternateId; - -/** Offset 0x06B1 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x06B2 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x06B3 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x06B4 - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x06B5 - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x06B6 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x06B7 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x06B8 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x06B9 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x06BA - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x06BB - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x06BF - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x06C5 - Enable eMMC HS400 Training - Determine if HS400 Training is required. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06C6 - Set HS400 Tuning Data Valid - Set if HS400 Tuning Data Valid. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06C7 - Rx Strobe Delay Control - Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06C8 - Tx Data Delay Control - Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06C9 - I/O Driver Strength - I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm. -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06CA - Enable Pch Serial IO GPIO - Determines if enable Serial IO GPIO. - $EN_DIS -**/ - UINT8 SerialIoGpio; - -/** Offset 0x06CB - IO voltage for I2C controllers - Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. - Note: I2C 2/3/4/5 does not support 3.3V (only 1.8V), due to GPIO GPP_F limitation -**/ - UINT8 SerialIoI2cVoltage[6]; - -/** Offset 0x06D1 - SPI ChipSelect signal polarity - Selects SPI ChipSelect signal polarity. -**/ - UINT8 SerialIoSpiCsPolarity[2]; - -/** Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS linesh. -**/ - UINT8 SerialIoUartHwFlowCtrl[3]; - -/** Offset 0x06D6 - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x06D7 - Enable Debug UART Controller - Enable debug UART controller after post. -**/ - UINT8 SerialIoEnableDebugUartAfterPost; - -/** Offset 0x06D8 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06D9 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06DA - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06DB - Enable Thermal Device - Enable Thermal Device. - $EN_DIS -**/ - UINT8 PchThermalDeviceEnable; - -/** Offset 0x06DC - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06DE - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06E0 - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06E2 - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06E3 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06E4 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06E5 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x06E6 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x06E7 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x06E9 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x06EA - Thermal Sensor 0 Target Width - Thermal Sensor 0 Target Width. -**/ - UINT8 DmiTS0TW; - -/** Offset 0x06EB - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. -**/ - UINT8 DmiTS1TW; - -/** Offset 0x06EC - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. -**/ - UINT8 DmiTS2TW; - -/** Offset 0x06ED - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. -**/ - UINT8 DmiTS3TW; - -/** Offset 0x06EE - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x06EF - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x06F0 - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x06F1 - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x06F2 - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x06F3 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x06F4 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x06F5 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x06F6 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x06F8 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x06FA - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x06FB - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x06FC - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x06FE - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x0700 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x0702 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x0704 - Disable XHCI Compliance Mode - This policy will disable XHCI compliance mode on all ports. Complicance Mode should - be default enabled. - $EN_DIS -**/ - UINT8 PchDisableComplianceMode; - -/** Offset 0x0705 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0715 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x071F - Enable 8254 Static Clock Gating in early POST time - Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might - fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy - OS boot before enabling this. - $EN_DIS -**/ - UINT8 Early8254ClockGatingEnable; - -/** Offset 0x0720 - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x0721 - PCH SATA RST CPU attached storage - RST CPU attached storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x0722 - Hybrid Storage Mode - Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. - Default is 0: Disabled - $EN_DIS -**/ - UINT8 HybridStorageMode; - -/** Offset 0x0723 -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x0724 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x0728 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0729 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x072A - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x072B -**/ - UINT8 UnusedUpdSpace19[5]; - -/** Offset 0x0730 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0738 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0758 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0760 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0764 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x0765 -**/ - UINT8 UnusedUpdSpace20[3]; - -/** Offset 0x0768 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x0770 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear - Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear - $EN_DIS -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid - The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. - $EN_DIS -**/ - UINT8 MeUnconfigIsValid; - -/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x077B -**/ - UINT8 ReservedFspsUpd[5]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0780 -**/ - UINT32 Signature; - -/** Offset 0x0784 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x0785 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x0786 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x0787 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x0788 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x0789 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[3]; - -/** Offset 0x078C - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x078D - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x078E - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x078F - Disable VT-d - 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x0790 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x0791 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x079C - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x079D - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x079E - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x079F - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07A0 -**/ - UINT8 UnusedUpdSpace21; - -/** Offset 0x07A1 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07A2 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07A3 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) - 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07A4 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07A5 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07A6 - Package PL3 time window - Package PL3 time window range for this policy in milliseconds. Valid values are - 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64 -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07A7 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07A8 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07A9 - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07AA - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For SKL Y SKU, the recommended default for this policy is - 10, For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07AB - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07AC - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07AD - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07AE - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07AF - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07B0 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07B1 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07B2 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07B3 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07B4 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07B5 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07B6 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07B7 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07B8 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07B9 - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07BA - PL1 timewindow - PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 - , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07BB - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07BC -**/ - UINT8 UnusedUpdSpace22[2]; - -/** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x07C1 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x07C2 - Enable or Disable processor debug features - Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x07C3 - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x07C4 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1:HALT loop, 2:MWAIT loop, 3:RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x07C5 - Settings for AP Handoff to OS - Settings for AP Handoff to OS; 1: HALT loop; 2: MWAIT loop. - 1:HALT loop, 2:MWAIT loop -**/ - UINT8 ApHandoffManner; - -/** Offset 0x07C6 -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x07C8 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0:Single Range Output, 1:ToPA Output -**/ - UINT8 ProcTraceOutputScheme; - -/** Offset 0x07C9 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcTraceEnable; - -/** Offset 0x07CA - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, Total Memory required is up to requested - value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace, - PcdFspReservedMemoryLength must be increased by the total memory required, and - PlatformMemorySize policy must also be increased by the total memory required over - 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB - , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , - 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable -**/ - UINT8 ProcTraceMemSize; - -/** Offset 0x07CB -**/ - UINT8 UnusedUpdSpace24; - -/** Offset 0x07CC - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x07CD - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x07CE - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x07CF - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x07D0 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x07D3 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x07D4 - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x07D5 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x07D6 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x07D7 - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x07D8 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x07D9 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x07DA - Enable or Disable Package C-State Demotion - Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto - (Auto: Enabled for Skylake; Disabled for Kabylake) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion - Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto - (Auto: Enabled for Skylake; Disabled for Kabylake) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x07DC - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x07DD - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x07DE - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x07DF - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x07E0 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x07E1 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x07E2 - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x07E3 - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x07E4 - TimeUnit for C-State Latency Control4 - TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x07E5 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x07E6 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x07E7 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x07E8 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up; 0xFF: Deactivate - 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x07E9 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x07EA - Max P-State Ratio - Max P-State Ratio , Valid Range 0 to 0x7F -**/ - UINT16 MaxRatio; - -/** Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table - Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has - valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates) - , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F -**/ - UINT16 StateRatio[40]; - -/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF, - Default is 0x4E, Server Platform is 0x4B -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF, - Default is 0x76, Server Platform is 0x6B -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0848 - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x084C - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0850 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0854 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x0858 - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x085C - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0860 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0864 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0868 - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x086C - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x0870 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x0874 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x0878 - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x087C - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x087E - CpuS3ResumeDataSize - Size of CPU S3 Resume Data -**/ - UINT16 CpuS3ResumeDataSize; - -/** Offset 0x0880 - CpuS3ResumeData - Pointer to CPU S3 Resume Data -**/ - UINT32 CpuS3ResumeData; - -/** Offset 0x0884 - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x0885 - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x0886 - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x0887 - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x0888 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x0889 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[1]; - -/** Offset 0x088A - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x088B - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x088C - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x088D - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x088E - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x0890 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x0891 - RTC CMOS RAM LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcLock; - -/** Offset 0x0892 - PCH Sbi lock bit - This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchSbiUnlock; - -/** Offset 0x0893 - PCH Psf lock bit - The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x0894 - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x08F4 - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x090C - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x0924 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09B4 - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x09CC - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A2C - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A2D - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A2E - PCH Pm Disable Energy Report - Disable/Enable PCH to CPU enery report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A2F - PCH Pm Pmc Read Disable - Deprecated - $EN_DIS -**/ - UINT8 PchPmPmcReadDisable; - -/** Offset 0x0A30 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A31 -**/ - UINT8 ReservedFspsTestUpd[15]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0780 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0A40 -**/ - UINT8 UnusedUpdSpace25[470]; - -/** Offset 0x0C16 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/AmberLakeFspBinPkg/Include/FsptUpd.h b/AmberLakeFspBinPkg/Include/FsptUpd.h deleted file mode 100644 index 719b09b..0000000 --- a/AmberLakeFspBinPkg/Include/FsptUpd.h +++ /dev/null @@ -1,133 +0,0 @@ -/** @file - - @copyright - Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 -**/ - UINT8 UnusedUpdSpace0[2]; - -/** Offset 0x0044 -**/ - UINT32 PcdSerialIoUartInputClock; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 -**/ - UINT8 ReservedFsptUpd1[12]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0060 -**/ - UINT8 UnusedUpdSpace1[6]; - -/** Offset 0x0066 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/AmberLakeFspBinPkg/Include/GpioConfig.h b/AmberLakeFspBinPkg/Include/GpioConfig.h deleted file mode 100644 index aa6c88e..0000000 --- a/AmberLakeFspBinPkg/Include/GpioConfig.h +++ /dev/null @@ -1,354 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - - @copyright - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 2; - UINT32 RsvdBits : 17; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9 -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - - - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /// - /// Deprecated settings. Maintained only for compatibility. - /// - GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood") - GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset") - GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" ) - GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" ) - - /// - /// New GPIO reset configuration options - /// - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Set GPIO termination and Pad Tolerance (applicable only for some pads) - Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F, - GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance - GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value -#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioLockPadConfig and GpioLockOutputState can be OR'ed. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controllable - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. -**/ -typedef enum { - GpioLockDefault = 0x0, ///< Leave lock setting unmodified - GpioPadConfigLock = 0x3, ///< Lock Pad Configuration - GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/AmberLakeFspBinPkg/Include/GpioSampleDef.h b/AmberLakeFspBinPkg/Include/GpioSampleDef.h deleted file mode 100644 index 74b4966..0000000 --- a/AmberLakeFspBinPkg/Include/GpioSampleDef.h +++ /dev/null @@ -1,382 +0,0 @@ -/** @file - @copyright -Copyright (c) 2015, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/AmberLakeFspBinPkg/Include/MemInfoHob.h b/AmberLakeFspBinPkg/Include/MemInfoHob.h deleted file mode 100644 index 2ab0ea1..0000000 --- a/AmberLakeFspBinPkg/Include/MemInfoHob.h +++ /dev/null @@ -1,278 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -// @todo remove and use the MdePkg\Include\Pi\PiHob.h -#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) -#ifndef __HOB__H__ -typedef struct _EFI_HOB_GENERIC_HEADER { - UINT16 HobType; - UINT16 HobLength; - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -typedef struct _EFI_HOB_GUID_TYPE { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Name; - /// - /// Guid specific data goes here - /// -} EFI_HOB_GUID_TYPE; -#endif -#endif - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/AmberLakeFspBinPkg/Include/SmbiosCacheInfoHob.h b/AmberLakeFspBinPkg/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index e04e66a..0000000 --- a/AmberLakeFspBinPkg/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - @copyright - Copyright (c) 2015, Intel Corporation. All rights reserved.
- - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -@par Specification Reference: - System Management BIOS (SMBIOS) Reference Specification v3.0.0 - dated 2015-Feb-12 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -extern EFI_GUID gSmbiosCacheInfoHobGuid; - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/AmberLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h b/AmberLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index 521aab2..0000000 --- a/AmberLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - @copyright - Copyright (c) 2015, Intel Corporation. All rights reserved.
- - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -@par Specification Reference: - System Management BIOS (SMBIOS) Reference Specification v3.0.0 - dated 2015-Feb-12 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -extern EFI_GUID gSmbiosProcessorInfoHobGuid; - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.0 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.0 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.0 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/AmberLakeFspBinPkg/README.md b/AmberLakeFspBinPkg/README.md deleted file mode 100644 index 8eff820..0000000 --- a/AmberLakeFspBinPkg/README.md +++ /dev/null @@ -1,14 +0,0 @@ -# AmberLakeFspBinPkg -This FSP binary is intended to be used with 10th, 8th and 7th Generation Intel® Core™ processors and chipsets formerly known as Comet Lake Y-Series, Amber Lake, Kaby Lake Refresh, and Kaby Lake. It is generally not intended to be used with 8th Generation Intel® Core™ processors and chipsets formerly known as Coffee Lake or Whiskey Lake. - -In rare circumstances, this FSP binary is also used with 9th and 8th Generation Intel® Core™ processors and chipsets formerly known as Coffee Lake. Specifically, this FSP binary is only used with Coffee Lake desktop processors when installed in a motherboard that utilizes a 22nm Platform Controller Hub (PCH). This FSP binary is never used with mobile Coffee Lake or Whiskey Lake processors. The following Intel® 300 Series Chipsets use 22nm fabrication: - -* Intel® Z370 Chipset -* Intel® B365 Chipset -* Intel® H310C Chipset - -For all other Intel® 300 Series Chipsets, please use CoffeeLakeFspBinPkg. - -Comet Lake Y-Series support has been added starting with FSP release 3.7.6, previous versions of AmberLakeFspBinPkg do not support Comet Lake Y-Series. For all other Comet Lake processors, please use CometLakeFspBinPkg. - -AmberLakeFspBinPkg is the initial Intel® FSP to implement Intel® FSP External Architecture Specification v2.1. KabyLakeFspBinPkg supports similar Intel® Core™ processors and chipsets, however it implements Intel® FSP External Architecture Specification v2.0 instead of v2.1. diff --git a/AmberLakeFspBinPkg/SampleCode/Vbt/Vbt.bin b/AmberLakeFspBinPkg/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index 5eab2cced44471484b69066fe8780ad5b16ce1e2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKZ){Ul6hE)8e_ro*++B@}R*f{~J`^N*&2`b|?|+j}3LC((xYr2_At7 z|BcH4d5&w4BAOOS9-Jr?Lw#X_P2skY-NVJg`b1%T|HQ~BX5vYV?b%Z(7RGi>6!MrI zcqWDhrp!7fhl_dKK6zkwVXO@aNTc2u+1RpSBVuHIEB&;{CaP*}k!ahdCuNrCjHkC{ zlBrmKGQAzseV9mQW7%xywvNubKnf6a5D)|foH{rW zoC@d&x&o+x0N@1B0T4hjj8MR_g>#T@jR5X|p_wCs=gqoqbhe4m;6e@*MNqw#$^+ms zYYK;CibXUWd}DT7Wp{I!0~>ESq`E~&$QD}E?nc6GzSB6gMyD3qrYg{FcN1*@z?-_w zY45A#$?NMc(~!3J9B>8!_&5!YdK)3lhu|>pfYwac48AA6 zM0|z#8nMgGppLkKcqMT&@e{-`;vV81#6!fx#O_JBUU8IwR)VO++0t)GP@Hfy45bsc z{)Daf{zi*V#B3?r(p1(^R4N`1+^BpNfJ#N!VpyOP0=dm4Y@}{mrcBB68N1z2(wM73 zyIrYxbJTRubMH#_B~U2a;LB`Cl1oIre$;jGN zh)`#2;5$&Lk-*1q>2R9JQihKKzmMTtOg+ii#|*z_>W_^5%Fr*WD@E2UVpdcOA{!C$ zZBhMDWS@%oov8jIvfo8)kkqvj+a%$$l6pX5FG={mq<$i?&n5gpQm;ttnuN<`b%V^d z$hb#VCuKG*<0)DFOlDumcu7|OkQwj8uupx;$2xtu->1IfW3T(APT;xiApP3X1 zV-lTDgAU1*S2=~Gt8NY5gtsnCbea+Z!#N50LC4|h@k}O>n#yG+i65pSOYjXw;=CSFk38 zDeMg@y7D&!u52cXH6nbpe(GXxaJ4>oylMkiHj_h1cb}=jhVG|zZTFd0T|Zkza9dfD zG~lXbCigBMINb}4T36X#3u7kB=KV^h)G`l;TgtP!V56>~y%w~Z&a#=sN+nM%UWD39 zv!iEL5<*jTEy`vtBh9*IYKVvT!n5alXI5yLcbCp1@L;CUG?TR;XifUL+)Q2z^jbM1 zkQY3KqY)2x8IvZ0Y$3R?1}`oLVK#$HHA#zCy(rUuBpXVe&1O6pL4NzFcC?iOFKlks z2b-&F!9$&81AYB0zAwT$h2r*I2MYg#hUMU$%C)b8 zd+RyM<4@nava*023us*w-s~bHla$@>pbIPy>$rE|XP%B?gADU6>0UrB8V5(_>A|R4 Ui!t}{a^K|!`{Ua(OV diff --git a/AmberLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf b/AmberLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index 004abf0..0000000 --- a/AmberLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11669 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Skylake/Kabylake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from SKL/KBL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for SKL/KBL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for SKL/KBL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" - Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" - Selection 0x06, "Integrated HDMI-D DDC GPIO Pins" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Skylake/Kabylake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if there’s no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel® Rapid Memory Power Management (RMPM)\r\n" - "2. Intel® Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel® Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel® Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop SKL/KBL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/ApolloLakeFspBinPkg/Docs/Apollo_Lake_FSP_Integration_Guide.pdf b/ApolloLakeFspBinPkg/Docs/Apollo_Lake_FSP_Integration_Guide.pdf deleted file mode 100644 index 811dcda2791b2bc64105d88a461984b29bda5abb..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1170245 zcmdR%2_Tef`~RnqvL;C)6eTH)nXyFXlp+;EQp6-X+4sV@0`}99g zfA$tsj!sh$zcxiidZDHume3UNv%&U&?giTeN(+1ql-t3djgp}!b6KiJEvR$ZUmFE} z(mC=gCgg+5&%+PlfemmVzidiAxRDQbe2N!cw zS8E4*Nm=Rum02(%z?Msr-<~Q~X>|yNf$>byA$S4Uou~gi2a56}`JKT22A_h_{-6FP zp8y~Ixc(6N74Rxhzm%)Mi2Ko3paa1^a3)_5_7&J`;A=mw0&f9(&w_jv_z1ind<6C= zc#}D$_ZEv>7q_#&bRcyX!WIl*nlAinXM(1IEdd)1x)t;&C=&358M)a%tf5>FY6omN zXbpIiBl%MBjTTY`Y_Vvkv5P8K!WInrh3t~~wVfJ2`x;d5*`H6r#!^{Bkuvy*>fHZ2 z5@3s^6^bLN%!MzQSSaRF8TmhmgymH>e6f5+r2rXfWy2RwYoMONE?Hh>!|CTcs?ios zC*Q$-mGUB91{MAzVX2UB08^eO`4M;vm=M8{_=lu_SHglXDPh5=-HM=-u)sc8UbiBa zl(1luR1u7zldvduQN{AVC1D}xCoHO>OqNcXDoH__(>Et%B_m(#ZWa;NNs?u1NPHy|#BKgmHjViZMyiF0rzr^KB z%6kZEm&?(~dtm=8ugm2Y&3iw~cdChp9G#R0mM=dBp+$x>a9#vf+n~R}I0uWBAFc*p z1~1r8P6EBR}%P*R+etKE%*XgA^om>UZ!hSeo5if&2`r*;#En4Ik&1=89RgOA%<>@3hun(3u zc;%Orl;o(376m#r76qc0R>upWPIGl>}6pPI^=LZ#4l9STu#~za#ZQrI(cZ6lmQ}C;5RrwA^lAH2eJ= z)S%K-eqWe;(~QqRGN79f^vKtMWenAJA6@Y zPir65Bptdiz+cGgpnd98i)v zjoC{{UsT5aozDMhEib-kK;>&1P7bBFb^y8=GAFS9?F!2Y3B z#1u-8{)49d9XI`3fBrji_tKUGptLxY-l71dYnI#Vi)JZG1x5`;>8%TZrcsemP4e&! zR?VQp!9{y;ZgmPA*Z*`hh{-@Q1~LS&P6JWtk2DWnK;aAEBQW9rr=zo_J4*i&7z)+^n$>iVn4_Nel&Jb`xi13Y}$`I|F6wl zG)qxp53rOP7U@zz zx|}47D{ToEOI86U3QYsQ9voJ=dmBf@VNnn3ykQ*}oxI zExx(_r-Z3^o6N%0oMIjoYNIIieuF_m^*)EsWP`dS{ts zy*OF_HDG0FWW6w5U&yk5gRB?ldfj7lGDj*E19K;Qtc!x9jEEpyW zfei4gj$jc2#*`WPV(>FS3H{CjdnsG)HG<8OD~qA2{A4Wz*MOtV22_BTkJ;xo`r%G1AAC!mf&MT5pt z5jr#_7!bF{QP4Au*IqQuNe%mkBU0Nmc-5}_EF`r<7D@Ofey9} z3_?mcTKwvKN_GIP0>c-C>y+$3>7&0fatXUXK_^nNM;JXoP7y2UL@E?{kZguM`9Ra? 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zo)4Vo=z>Q;2hMY32k5~4b7TkTz~|eM9iRjE&ygLV1LrvvIkEWjhVvZR0XlG=BRfC` z&U0i3=)if7>;N6Oe@;bk#B?Aa0b#ff^il-ua2@Eu1nh7fs1pHpxDF%^w*z=i1$d5b z1O?&(Isl$i0iF~0Uy->=1$d4w)CKGS9RSa%0MF5tT6lT@&(SqofE~~t0MCiLNil5z z&xt#EF*|_g=)yF>4$uMc99_f*#07K!Jg1V`O^hAUyM#P;qyjvr0z4<~XvFjaJf{LY zrvf}D?&ZYO1Ns%fb1KgBu@UjO^pIXE8vBgXi^7OAh2z7}E`3y2MpRrLP>rs6AQ diff --git a/ApolloLakeFspBinPkg/FspBin/Fsp.bsf b/ApolloLakeFspBinPkg/FspBin/Fsp.bsf deleted file mode 100644 index b4e1f0c..0000000 --- a/ApolloLakeFspBinPkg/FspBin/Fsp.bsf +++ /dev/null @@ -1,1793 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2019, Intel Corporation. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "APLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - - Find "APLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 31 bytes - $gBroxtonFspPkgTokenSpaceGuid_StackBase 4 bytes $_DEFAULT_ = 0xFEF16000 - $gBroxtonFspPkgTokenSpaceGuid_StackSize 4 bytes $_DEFAULT_ = 0x0002A000 - $gBroxtonFspPkgTokenSpaceGuid_BootLoaderTolumSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Bootmode 4 bytes $_DEFAULT_ = 0x00000000 - Skip 8 bytes - $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortType 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortDevice 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortStrideSize 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Igd 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_IgdApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_GttSize 1 bytes $_DEFAULT_ = 0x03 - $gBroxtonFspPkgTokenSpaceGuid_PrimaryVideoAdaptor 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Package 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Profile 1 bytes $_DEFAULT_ = 0x19 - $gBroxtonFspPkgTokenSpaceGuid_MemoryDown 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DDR3LPageSize 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DDR3LASR 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_InterleavedMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ChannelHashMask 2 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SliceHashMask 2 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ChannelsSlicesEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_MinRefRate2xEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DualRankSupportEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_RmtMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_MemorySizeLimit 2 bytes $_DEFAULT_ = 0x0000 - $gBroxtonFspPkgTokenSpaceGuid_LowMemoryMaxValue 2 bytes $_DEFAULT_ = 0x0000 - $gBroxtonFspPkgTokenSpaceGuid_HighMemoryMaxValue 2 bytes $_DEFAULT_ = 0x0000 - $gBroxtonFspPkgTokenSpaceGuid_DisableFastBoot 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DIMM0SPDAddress 1 bytes $_DEFAULT_ = 0xA0 - $gBroxtonFspPkgTokenSpaceGuid_DIMM1SPDAddress 1 bytes $_DEFAULT_ = 0xA4 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_RankEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_DeviceWidth 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_DramDensity 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_Option 1 bytes $_DEFAULT_ = 0x03 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_OdtConfig 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_TristateClk1 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_Mode2N 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_OdtLevels 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_RankEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_DeviceWidth 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_DramDensity 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_Option 1 bytes $_DEFAULT_ = 0x03 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_OdtConfig 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_TristateClk1 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_Mode2N 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch1_OdtLevels 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_RankEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_DeviceWidth 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_DramDensity 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_Option 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_OdtConfig 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_TristateClk1 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_Mode2N 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch2_OdtLevels 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_RankEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_DeviceWidth 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_DramDensity 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_Option 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_OdtConfig 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_TristateClk1 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_Mode2N 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Ch3_OdtLevels 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_RmtCheckRun 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_RmtMarginCheckScaleHighThreshold 2 bytes $_DEFAULT_ = 0x0000 - $gBroxtonFspPkgTokenSpaceGuid_Ch0_Bit_swizzling 32 bytes $_DEFAULT_ = 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F - $gBroxtonFspPkgTokenSpaceGuid_Ch1_Bit_swizzling 32 bytes $_DEFAULT_ = 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F - $gBroxtonFspPkgTokenSpaceGuid_Ch2_Bit_swizzling 32 bytes $_DEFAULT_ = 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F - $gBroxtonFspPkgTokenSpaceGuid_Ch3_Bit_swizzling 32 bytes $_DEFAULT_ = 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F - $gBroxtonFspPkgTokenSpaceGuid_MsgLevelMask 4 bytes $_DEFAULT_ = 0x00000000 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTablePinNum 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTableEntryNum 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_EnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SpdWriteEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_MrcDataSaving 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_OemLoadingBase 4 bytes $_DEFAULT_ = 0x7AD00000 - $gBroxtonFspPkgTokenSpaceGuid_OemFileName 16 bytes $_DEFAULT_ = "" - Skip 4 bytes - $gBroxtonFspPkgTokenSpaceGuid_eMMCTraceLen 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SkipCseRbp 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_NpkEn 1 bytes $_DEFAULT_ = 0x03 - $gBroxtonFspPkgTokenSpaceGuid_FwTraceEn 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_FwTraceDestination 1 bytes $_DEFAULT_ = 0x04 - $gBroxtonFspPkgTokenSpaceGuid_RecoverDump 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Msc0Wrap 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Msc1Wrap 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Msc0Size 4 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Msc1Size 4 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PtiMode 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PtiTraining 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PtiSpeed 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_PunitMlvl 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PmcMlvl 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SwTraceEn 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PeriodicRetrainingDisable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_EnableResetSystem 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_EnableS3Heci2 1 bytes $_DEFAULT_ = 0x01 - Skip 7 bytes - $gBroxtonFspPkgTokenSpaceGuid_StartTimerTickerOfPfetAssert 8 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_RtEn 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SkipPciePowerSequence 1 bytes $_DEFAULT_ = 0x00 - - Find "APLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gBroxtonFspPkgTokenSpaceGuid_ActiveProcessorCores 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DisableCore1 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DisableCore2 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DisableCore3 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ProcTraceMemSize 1 bytes $_DEFAULT_ = 0xFF - $gBroxtonFspPkgTokenSpaceGuid_ProcTraceEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_BootPState 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_EnableCx 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x02 - $gBroxtonFspPkgTokenSpaceGuid_CStateAutoDemotion 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_CStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_MaxCoreCState 1 bytes $_DEFAULT_ = 0x08 - $gBroxtonFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdaVerbTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_P2sbUnhide 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IpuEn 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_IpuAcpiMode 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ForceWake 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xBF000000 - $gBroxtonFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xA0000000 - $gBroxtonFspPkgTokenSpaceGuid_PavpLock 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_GraphicsFreqModify 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_GraphicsFreqReq 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_GraphicsVideoFreq 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PmLock 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DopClockGating 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UnsolicitedAttackOverride 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_WOPCMSupport 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_WOPCMSize 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PowerGating 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UnitLevelClockGating 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_FastBoot 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DynSR 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_EnableRenderStandby 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PavpPr3 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x04 - $gBroxtonFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_WriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ProtectedRangeLimit 10 bytes $_DEFAULT_ = 0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F - $gBroxtonFspPkgTokenSpaceGuid_ProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gBroxtonFspPkgTokenSpaceGuid_Gmm 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingPgcbClkTrunk 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSb 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSbClkTrunk 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSbClkPartition 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingCore 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingDma 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingRegAccess 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingHost 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingPartition 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ClkGatingTrunk 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DspEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Pme 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferOwnership 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferVoltage 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioVcType 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioLinkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DspEndpointDmic 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DspEndpointBluetooth 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DspEndpointI2sSkp 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DspEndpointI2sHp 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_AudioCtlPwrGate 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_AudioDspPwrGate 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Mmt 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Hmt 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HDAudioPwrGate 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HDAudioClkGate 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DspFeatureMask 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_DspPpModuleMask 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_BiosCfgLockDown 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Hpet 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HpetBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_HpetBusNumber 1 bytes $_DEFAULT_ = 0xFA - $gBroxtonFspPkgTokenSpaceGuid_HpetDeviceNumber 1 bytes $_DEFAULT_ = 0x1F - $gBroxtonFspPkgTokenSpaceGuid_HpetFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IoApicBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IoApicBusNumber 1 bytes $_DEFAULT_ = 0xFA - $gBroxtonFspPkgTokenSpaceGuid_IoApicDeviceNumber 1 bytes $_DEFAULT_ = 0x0F - $gBroxtonFspPkgTokenSpaceGuid_IoApicFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_IoApicId 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_IoApicRangeSelect 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IshEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_BiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_BiosLock 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SpiEiss 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_BiosLockSwSmiNumber 1 bytes $_DEFAULT_ = 0xA9 - $gBroxtonFspPkgTokenSpaceGuid_LPSS_S0ixEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gBroxtonFspPkgTokenSpaceGuid_I2cClkGateCfg 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HsuartClkGateCfg 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SpiClkGateCfg 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c0Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c1Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c2Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c3Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c4Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c5Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c6Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_I2c7Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Hsuart0Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Hsuart1Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Hsuart2Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Hsuart3Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Spi0Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Spi1Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Spi2Enable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_OsDbgEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DciEn 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Uart2KernelDebugBaseAddress 4 bytes $_DEFAULT_ = 0x0000000 - $gBroxtonFspPkgTokenSpaceGuid_PcieClockGatingDisabled 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRootPort8xhDecode 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_Pcie8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRootPortPeerMemoryWriteEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieAspmSwSmiNumber 1 bytes $_DEFAULT_ = 0xAA - Skip 1 bytes - $gBroxtonFspPkgTokenSpaceGuid_PcieRootPortEn 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpHide 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotImplemented 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpHotPlug 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpPmSci 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpExtSync 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpAcsEnabled 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqSupported 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqNumber 6 bytes $_DEFAULT_ = 0x04, 0x05, 0x00, 0x01, 0x02, 0x03 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqDetect 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_AdvancedErrorReporting 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PmeInterrupt 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UnsupportedRequestReport 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_FatalErrorReport 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_NoFatalErrorReport 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_CorrectableErrorReport 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnFatalError 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnNonFatalError 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnCorrectableError 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSpeed 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PhysicalSlotNumber 6 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PtmEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpAspm 6 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpL1Substates 6 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrEnable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PciClockRun 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Timer8254ClkSetting 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_EnableSata 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_eSATASpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SpeedLimit 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gBroxtonFspPkgTokenSpaceGuid_SataPortsEnable 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsDevSlp 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsHotPlug 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsInterlockSw 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsExternal 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsSpinUp 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SataPortsDmVal 2 bytes $_DEFAULT_ = 0x0F, 0x0F - Skip 2 bytes - $gBroxtonFspPkgTokenSpaceGuid_SataPortsDitoVal 4 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02 - $gBroxtonFspPkgTokenSpaceGuid_SubSystemVendorId 2 bytes $_DEFAULT_ = 0x8086 - $gBroxtonFspPkgTokenSpaceGuid_SubSystemId 2 bytes $_DEFAULT_ = 0x7270 - $gBroxtonFspPkgTokenSpaceGuid_CRIDSettings 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_ResetSelect 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SdcardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_eMMCEnabled 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_eMMCHostMaxSpeed 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UfsEnabled 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SdioEnabled 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_GppLock 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SirqMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_StartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ArpEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gBroxtonFspPkgTokenSpaceGuid_NumRsvdSmbusAddresses 2 bytes $_DEFAULT_ = 0x0080 - $gBroxtonFspPkgTokenSpaceGuid_RsvdSmbusAddressTable 128 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DisableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UsbPerPortCtl 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_Usb30Mode 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20Enable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PortUs20bOverCurrentPin 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_UsbOtg 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HsicSupportEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb30Enable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PortUs30bOverCurrentPin 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SsicPortEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DlanePwrGating 2 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_VtdEnable 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_LockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_ResetWaitTimer 2 bytes $_DEFAULT_ = 0x012C - $gBroxtonFspPkgTokenSpaceGuid_RtcLock 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SsicRate 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_DynamicPowerGating 2 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 6 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - Skip 2 bytes - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 12 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x00,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 6 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gBroxtonFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0 - $gBroxtonFspPkgTokenSpaceGuid_DciAutoDetect 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrMaxNonSnoopLatency 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 6 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gBroxtonFspPkgTokenSpaceGuid_TcoTimerHaltLock 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 12 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 6 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PowerButterDebounceMode 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_SdioTxCmdCntl 4 bytes $_DEFAULT_ = 0x00000505 - $gBroxtonFspPkgTokenSpaceGuid_SdioTxDataCntl1 4 bytes $_DEFAULT_ = 0x0000000E - $gBroxtonFspPkgTokenSpaceGuid_SdioTxDataCntl2 4 bytes $_DEFAULT_ = 0x22272828 - $gBroxtonFspPkgTokenSpaceGuid_SdioRxCmdDataCntl1 4 bytes $_DEFAULT_ = 0x16161616 - $gBroxtonFspPkgTokenSpaceGuid_SdioRxCmdDataCntl2 4 bytes $_DEFAULT_ = 0x00010000 - $gBroxtonFspPkgTokenSpaceGuid_SdcardTxCmdCntl 4 bytes $_DEFAULT_ = 0x00000505 - $gBroxtonFspPkgTokenSpaceGuid_SdcardTxDataCntl1 4 bytes $_DEFAULT_ = 0x00000A13 - $gBroxtonFspPkgTokenSpaceGuid_SdcardTxDataCntl2 4 bytes $_DEFAULT_ = 0x24242828 - $gBroxtonFspPkgTokenSpaceGuid_SdcardRxCmdDataCntl1 4 bytes $_DEFAULT_ = 0x073A3637 - $gBroxtonFspPkgTokenSpaceGuid_SdcardRxStrobeCntl 4 bytes $_DEFAULT_ = 0x00000000 - $gBroxtonFspPkgTokenSpaceGuid_SdcardRxCmdDataCntl2 4 bytes $_DEFAULT_ = 0x00010000 - $gBroxtonFspPkgTokenSpaceGuid_EmmcTxCmdCntl 4 bytes $_DEFAULT_ = 0x00000505 - $gBroxtonFspPkgTokenSpaceGuid_EmmcTxDataCntl1 4 bytes $_DEFAULT_ = 0x00000C11 - $gBroxtonFspPkgTokenSpaceGuid_EmmcTxDataCntl2 4 bytes $_DEFAULT_ = 0x1C2A2927 - $gBroxtonFspPkgTokenSpaceGuid_EmmcRxCmdDataCntl1 4 bytes $_DEFAULT_ = 0x000D162F - $gBroxtonFspPkgTokenSpaceGuid_EmmcRxStrobeCntl 4 bytes $_DEFAULT_ = 0x00000a0a - $gBroxtonFspPkgTokenSpaceGuid_EmmcRxCmdDataCntl2 4 bytes $_DEFAULT_ = 0x0001003b - $gBroxtonFspPkgTokenSpaceGuid_EmmcMasterSwCntl 4 bytes $_DEFAULT_ = 0x00000001 - $gBroxtonFspPkgTokenSpaceGuid_PcieRpSelectableDeemphasis 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gBroxtonFspPkgTokenSpaceGuid_HdAudioDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_IPC 16 bytes $_DEFAULT_ = 0xF8,0xEE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF - $gBroxtonFspPkgTokenSpaceGuid_SataPortsDisableDynamicPg 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_InitS3Cpu 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_SkipPunitInit 1 bytes $_DEFAULT_ = 0x00 - Skip 4 bytes - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortTxPeHalf 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortPeTxiSet 8 bytes $_DEFAULT_ = 0x07, 0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortTxiSet 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20HsSkewSel 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20IUsbTxEmphasisEn 8 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortRXISet 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PortUsb20HsNpreDrvSel 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 - $gBroxtonFspPkgTokenSpaceGuid_OsSelection 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_DptfEnabled 1 bytes $_DEFAULT_ = 0x00 - $gBroxtonFspPkgTokenSpaceGuid_PWMEnabled 1 bytes $_DEFAULT_ = 0x00 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x02 , "64 MB" - Selection 0x03 , "96 MB" - Selection 0x04 , "128 MB" - Selection 0x05 , "160 MB" - Selection 0x06 , "192 MB" - Selection 0x07 , "224 MB" - Selection 0x08 , "256 MB" - Selection 0x09 , "288 MB" - Selection 0x0A , "320 MB" - Selection 0x0B , "352 MB" - Selection 0x0C , "384 MB" - Selection 0x0D , "416 MB" - Selection 0x0E , "448 MB" - Selection 0x0F , "480 MB" - Selection 0x10 , "512 MB" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Usb30Mode - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c6Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c4Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_IgdApertureSize - Selection 0x1 , "128 MB" - Selection 0x2 , "256 MB" - Selection 0x3 , "512 MB" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkTmode - Selection 0 , " 2T" - Selection 1 , " 1T" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_MemoryDown - Selection 0x0 , "No" - Selection 0x1 , "Yes" - Selection 0x2 , "1MD+SODIMM (for DDR3L only) ACRD" - Selection 0x3 , "1x32 LPDDR4" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch3_Mode2N - Selection 0x0 , "Auto" - Selection 0x1 , "Force 2N CMD Timing Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch1_DeviceWidth - Selection 0b0000 , "x8" - Selection 0b0001 , "x16" - Selection 0b0010 , "x32" - Selection 0b0011 , "x64" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_RmtMode - Selection 0x0 , "Disabled" - Selection 0x3 , "Enabled" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Profile - Selection 0x1 , "WIO2_800_7_8_8" - Selection 0x2 , "WIO2_1066_9_10_10" - Selection 0x3 , "LPDDR3_1066_8_10_10" - Selection 0x4 , "LPDDR3_1333_10_12_12" - Selection 0x5 , "LPDDR3_1600_12_15_15" - Selection 0x6 , "LPDDR3_1866_14_17_17" - Selection 0x7 , "LPDDR3_2133_16_20_20" - Selection 0x8 , "LPDDR4_1066_10_10_10" - Selection 0x9 , "LPDDR4_1600_14_15_15" - Selection 0xA , "LPDDR4_2133_20_20_20" - Selection 0xB , "LPDDR4_2400_24_22_22" - Selection 0xC , "LPDDR4_2666_24_24_24" - Selection 0xD , "LPDDR4_2933_28_27_27" - Selection 0xE , "LPDDR4_3200_28_29_29" - Selection 0xF , "DDR3_1066_6_6_6" - Selection 0x10 , "DDR3_1066_7_7_7" - Selection 0x11 , "DDR3_1066_8_8_8" - Selection 0x12 , "DDR3_1333_7_7_7" - Selection 0x13 , "DDR3_1333_8_8_8" - Selection 0x14 , "DDR3_1333_9_9_9" - Selection 0x15 , "DDR3_1333_10_10_10" - Selection 0x16 , "DDR3_1600_8_8_8" - Selection 0x17 , "DDR3_1600_9_9_9" - Selection 0x18 , "DDR3_1600_10_10_10" - Selection 0x19 , "DDR3_1600_11_11_11" - Selection 0x1A , "DDR3_1866_10_10_10" - Selection 0x1B , "DDR3_1866_11_11_11" - Selection 0x1C , "DDR3_1866_12_12_12" - Selection 0x1D , "DDR3_1866_13_13_13" - Selection 0x1E , "DDR3_2133_11_11_11" - Selection 0x1F , "DDR3_2133_12_12_12" - Selection 0x20 , "DDR3_2133_13_13_13" - Selection 0x21 , "DDR3_2133_14_14_14" - Selection 0x22 , "DDR4_1333_10_10_10" - Selection 0x23 , "DDR4_1600_10_10_10" - Selection 0x24 , "DDR4_1600_11_11_11" - Selection 0x25 , "DDR4_1600_12_12_12" - Selection 0x26 , "DDR4_1866_12_12_12" - Selection 0x27 , "DDR4_1866_13_13_13" - Selection 0x28 , "DDR4_1866_14_14_14" - Selection 0x29 , "DDR4_2133_14_14_14" - Selection 0x2A , "DDR4_2133_15_15_15" - Selection 0x2B , "DDR4_2133_16_16_16" - Selection 0x2C , "DDR4_2400_15_15_15" - Selection 0x2D , "DDR4_2400_16_16_16" - Selection 0x2E , "DDR4_2400_17_17_17" - Selection 0x2F , "DDR4_2400_18_18_18" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Hsuart0Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c5Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Spi0Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" - Selection 3 , " 48MHz" - Selection 4 , " 96MHz" - Selection 5 , " Invalid" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortType - Selection 0 , "NONE" - Selection 1 , "I/O" - Selection 2 , "MMIO" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_EnableResetSystem - Selection 0x0 , "Disabled" - Selection 0x1 , "Eabled" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_TcoTimerHaltLock - Selection 0 , "No" - Selection 1 , "Yes (default)" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Mmt - Selection 0 , " VC0" - Selection 1 , " VC2" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_StartFramePulse - Selection 0 , "ScSfpw4Clk" - Selection 1 , "ScSfpw6Clk" - Selection 2 , "ScSfpw8Clk" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c0Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Hsuart1Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch0_Mode2N - Selection 0x0 , "Auto" - Selection 0x1 , "Force 2N CMD Timing Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Hsuart3Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SpeedLimit - Selection 0 , "Default" - Selection 1 , " 1.5 Gb/s (Gen 1)" - Selection 2 , " 3 Gb/s(Gen 2)" - Selection 3 , " 6 Gb/s (Gen 1)" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioVcType - Selection 0 , " VC0" - Selection 1 , " VC1" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Hmt - Selection 0 , " VC0" - Selection 1 , " VC2" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" - Selection 3 , " 48MHz" - Selection 4 , " 96MHz" - Selection 5 , " Invalid" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_DspEndpointDmic - Selection 0 , " Disable" - Selection 1 , " 2ch array" - Selection 2 , " 4ch array" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch3_DeviceWidth - Selection 0b0000 , "x8" - Selection 0b0001 , "x16" - Selection 0b0010 , "x32" - Selection 0b0011 , "x64" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_OsSelection - Selection 0x0 , "Windows" - Selection 0x1 , "Android" - Selection 0x3 , "Linux" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_DDR3LASR - Selection 0x0 , "Not Supported" - Selection 0x1 , "Supported" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_UsbOtg - Selection 0 , "Disable" - Selection 1 , "PCI_Mode" - Selection 2 , "ACPI_mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_GttSize - Selection 0x1 , "2 MB" - Selection 0x2 , "4 MB" - Selection 0x3 , "8 MB" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferVoltage - Selection 0 , " 3.3V" - Selection 1 , " 1.8V" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_IpuAcpiMode - Selection 0 , "Disable" - Selection 1 , "IGFX Child device" - Selection 2 , "ACPI device" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_NpkEn - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Debugger" - Selection 3 , "Auto" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortDevice - Selection 0 , "SOC UART0" - Selection 1 , "SOC UART1" - Selection 2 , "SOC UART2" - Selection 3 , "External Device" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Spi1Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch0_DramDensity - Selection 0b0000 , "4Gb" - Selection 0b0001 , "6Gb" - Selection 0b0010 , "8Gb" - Selection 0b0011 , "12Gb" - Selection 0b0100 , "16Gb" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_PwrBtnOverridePeriod - Selection 0x0 , "4s" - Selection 0x1 , "6s" - Selection 0x2 , "8s" - Selection 0x3 , "10s" - Selection 0x4 , "12s" - Selection 0x5 , "14s" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_EnableS3Heci2 - Selection 0x0 , "Disabled" - Selection 0x1 , "Enabled" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch1_DramDensity - Selection 0b0000 , "4Gb" - Selection 0b0001 , "6Gb" - Selection 0b0010 , "8Gb" - Selection 0b0011 , "12Gb" - Selection 0b0100 , "16Gb" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch3_DramDensity - Selection 0b0000 , "4Gb" - Selection 0b0001 , "6Gb" - Selection 0b0010 , "8Gb" - Selection 0b0011 , "12Gb" - Selection 0b0100 , "16Gb" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c3Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_PcieClockGatingDisabled - Selection 0 , "Enable" - Selection 1 , "Disable" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c2Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch1_Mode2N - Selection 0x0 , "Auto" - Selection 0x1 , "Force 2N CMD Timing Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch2_DramDensity - Selection 0b0000 , "4Gb" - Selection 0b0001 , "6Gb" - Selection 0b0010 , "8Gb" - Selection 0b0011 , "12Gb" - Selection 0b0100 , "16Gb" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch2_DeviceWidth - Selection 0b0000 , "x8" - Selection 0b0001 , "x16" - Selection 0b0010 , "x32" - Selection 0b0011 , "x64" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Package - Selection 0x0 , "SODIMM" - Selection 0x1 , "BGA" - Selection 0x2 , "BGA mirrored (LPDDR3 only)" - Selection 0x3 , "SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c7Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortStrideSize - Selection 0 , "1" - Selection 2 , "4" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_eMMCTraceLen - Selection 0x0 , "Long" - Selection 0x1 , "Short" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferOwnership - Selection 0 , "HD-Audio link owns all the I/O buffers" - Selection 1 , "HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers" - Selection 3 , "I2S port owns all the I/O buffers" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_PrimaryVideoAdaptor - Selection 0x0 , "AUTO" - Selection 0x2 , "IGD" - Selection 0x3 , "PCI" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Spi2Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch0_DeviceWidth - Selection 0b0000 , "x8" - Selection 0b0001 , "x16" - Selection 0b0010 , "x32" - Selection 0b0011 , "x64" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_eMMCHostMaxSpeed - Selection 0 , "HS400" - Selection 1 , " HS200" - Selection 2 , "DDR50" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Ch2_Mode2N - Selection 0x0 , "Auto" - Selection 0x1 , "Force 2N CMD Timing Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_PeriodicRetrainingDisable - Selection 0x0 , "Enabled" - Selection 0x1 , "Disabled" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_DDR3LPageSize - Selection 0x1 , "1KB" - Selection 0x2 , "2KB" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 144 MHz" - Selection 1 , " 288 MHz" - Selection 2 , " 384 MHz" - Selection 3 , " 576 MHz" - Selection 4 , " 624 MHz" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_Hsuart2Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_SkipPciePowerSequence - Selection 0x0 , "Disabled" - Selection 0x1 , "Skip" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_I2c1Enable - Selection 0 , " Disabled" - Selection 1 , " PCI Mode" - Selection 2 , " ACPI Mode" -EndList - -List &gBroxtonFspPkgTokenSpaceGuid_InterleavedMode - Selection 0x0 , "Disable" - Selection 0x2 , "Enable" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Apollo Lake Platform" -EndInfoBlock - -Page "FSP MemoryInit Settings" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortAddress, "Debug Serial Port Base address", HEX, - Help "Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. 0x00000000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortType, "Debug Serial Port Type", &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortType, - Help "16550 compatible debug serial port resource type. NONE means no serial port support. 0x02:MMIO(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortDevice, "Serial Port Debug Device", &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortDevice, - Help "Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. 0x02:SOC UART2(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortStrideSize, "Debug Serial Port Stride Size", &gBroxtonFspPkgTokenSpaceGuid_SerialDebugPortStrideSize, - Help "Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_MrcFastBoot, "Memory Fast Boot", &EN_DIS, - Help "Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_Igd, "Integrated Graphics Device", &EN_DIS, - Help "Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "DVMT Pre-Allocated", &gBroxtonFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. 0x02:64 MB(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_IgdApertureSize, "Aperture Size", &gBroxtonFspPkgTokenSpaceGuid_IgdApertureSize, - Help "Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), 0x2:256 MB, 0x3:512 MB." - Combo $gBroxtonFspPkgTokenSpaceGuid_GttSize, "GTT Size", &gBroxtonFspPkgTokenSpaceGuid_GttSize, - Help "Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 MB(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PrimaryVideoAdaptor, "Primary Display", &gBroxtonFspPkgTokenSpaceGuid_PrimaryVideoAdaptor, - Help "Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), 0x2:IGD, 0x3:PCI" - Combo $gBroxtonFspPkgTokenSpaceGuid_Package, "Package", &gBroxtonFspPkgTokenSpaceGuid_Package, - Help "NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored (DDR3L); Refer to the IAFW spec for specific details about each CA mapping." - Combo $gBroxtonFspPkgTokenSpaceGuid_Profile, "Profile", &gBroxtonFspPkgTokenSpaceGuid_Profile, - Help "Profile list. 0x19(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_MemoryDown, "MemoryDown", &gBroxtonFspPkgTokenSpaceGuid_MemoryDown, - Help "Memory Down. 0x0(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_DDR3LPageSize, "DDR3LPageSize", &gBroxtonFspPkgTokenSpaceGuid_DDR3LPageSize, - Help "NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB." - Combo $gBroxtonFspPkgTokenSpaceGuid_DDR3LASR, "DDR3LASR", &gBroxtonFspPkgTokenSpaceGuid_DDR3LASR, - Help "NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported." - Combo $gBroxtonFspPkgTokenSpaceGuid_ScramblerSupport, "ScramblerSupport", &EN_DIS, - Help "Scrambler Support - Enable or disable the memory scrambler. Data scrambling is provided as a means to increase signal integrity/reduce RFI generated by the DRAM interface. This is achieved by randomizing seed that encodes/decodes memory data so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, 01: Enable Scrambler Support" - Combo $gBroxtonFspPkgTokenSpaceGuid_InterleavedMode, "InterleavedMode", &gBroxtonFspPkgTokenSpaceGuid_InterleavedMode, - Help "This field is ignored if one of the PnP channel configurations is used. If the memory configuration is different, then the field is used directly to populate. 0x00:Disable(Default), 0x02:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_ChannelHashMask, "ChannelHashMask", HEX, - Help "ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be modified. These inputs are not used for configurations where an optimized ChannelHashMask has been provided by the PnP validation teams. 0x00(Default)." - "Valid range: 0x0 ~ 0xF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SliceHashMask, "SliceHashMask", HEX, - Help "ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be modified. These inputs are not used for configurations where an optimized ChannelHashMask has been provided by the PnP validation teams. 0x00(Default)." - "Valid range: 0x0 ~ 0xF" - Combo $gBroxtonFspPkgTokenSpaceGuid_ChannelsSlicesEnable, "ChannelsSlicesEnable", &EN_DIS, - Help "ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), 0x01:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_MinRefRate2xEnable, "MinRefRate2xEnable", &EN_DIS, - Help "Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), 0x01:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_DualRankSupportEnable, "DualRankSupportEnable", &EN_DIS, - Help "Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_RmtMode, "RmtMode", &gBroxtonFspPkgTokenSpaceGuid_RmtMode, - Help "Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_MemorySizeLimit, "MemorySizeLimit", HEX, - Help "Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)" - "Valid range: 0x0000 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_LowMemoryMaxValue, "LowMemoryMaxValue", HEX, - Help "Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)." - "Valid range: 0x0000 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_HighMemoryMaxValue, "HighMemoryMaxValue", HEX, - Help "High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default)." - "Valid range: 0x0000 ~ 0xFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableFastBoot, "DisableFastBoot", &EN_DIS, - Help "00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; Full re-train of memory on every boot." - EditNum $gBroxtonFspPkgTokenSpaceGuid_DIMM0SPDAddress, "DIMM0SPDAddress", HEX, - Help "DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_DIMM1SPDAddress, "DIMM1SPDAddress", HEX, - Help "DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_RankEnable, "Ch0_RankEnable", HEX, - Help "NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be set to 1 to enable use of this rank." - "Valid range: 0x00 ~ 0xF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch0_DeviceWidth, "Ch0_DeviceWidth", &gBroxtonFspPkgTokenSpaceGuid_Ch0_DeviceWidth, - Help "NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch0_DramDensity, "Ch0_DramDensity", &gBroxtonFspPkgTokenSpaceGuid_Ch0_DramDensity, - Help "NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device density per rank (per Chip Select). The simplest way of identifying the density per rank is to divide the total SoC memory channel density by the number of ranks. For DDR3L: Must specify the DRAM device density per DRAM device. For example, an 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_Option, "Ch0_Option", HEX, - Help "BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] Bank Address Hashing Enable. See Address Mapping section for full description: 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_OdtConfig, "Ch0_OdtConfig", HEX, - Help "[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 OHMS or so roughly. Purpose: Save power on these technologies which burn power directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The customer needs to choose this based on their actual board strapping (how they tie the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS signals). Purpose: To improve signal integrity and provide a much more optimized CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_TristateClk1, "Ch0_TristateClk1", HEX, - Help "Not used" - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch0_Mode2N, "Ch0_Mode2N", &gBroxtonFspPkgTokenSpaceGuid_Ch0_Mode2N, - Help "DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command mode that provides more setup and hold time for DRAM commands on the DRAM command bus. This is useful for platforms with unusual CMD bus routing or marginal signal integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and Control training), 1 - Force 2N Mode" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_OdtLevels, "Ch0_OdtLevels", HEX, - Help "Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to SoC, 1 - ODT held high" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_RankEnable, "Ch1_RankEnable", HEX, - Help "NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be set to 1 to enable use of this rank." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch1_DeviceWidth, "Ch1_DeviceWidth", &gBroxtonFspPkgTokenSpaceGuid_Ch1_DeviceWidth, - Help "NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch1_DramDensity, "Ch1_DramDensity", &gBroxtonFspPkgTokenSpaceGuid_Ch1_DramDensity, - Help "NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device density per rank (per Chip Select). The simplest way of identifying the density per rank is to divide the total SoC memory channel density by the number of ranks. For DDR3L: Must specify the DRAM device density per DRAM device. For example, an 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_Option, "Ch1_Option", HEX, - Help "BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] Bank Address Hashing Enable. See Address Mapping section for full description: 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_OdtConfig, "Ch1_OdtConfig", HEX, - Help "[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 OHMS or so roughly. Purpose: Save power on these technologies which burn power directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The customer needs to choose this based on their actual board strapping (how they tie the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS signals). Purpose: To improve signal integrity and provide a much more optimized CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_TristateClk1, "Ch1_TristateClk1", HEX, - Help "Not used" - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch1_Mode2N, "Ch1_Mode2N", &gBroxtonFspPkgTokenSpaceGuid_Ch1_Mode2N, - Help "DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command mode that provides more setup and hold time for DRAM commands on the DRAM command bus. This is useful for platforms with unusual CMD bus routing or marginal signal integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and Control training), 1 - Force 2N Mode" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_OdtLevels, "Ch1_OdtLevels", HEX, - Help "DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_RankEnable, "Ch2_RankEnable", HEX, - Help "NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be set to 1 to enable use of this rank." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch2_DeviceWidth, "Ch2_DeviceWidth", &gBroxtonFspPkgTokenSpaceGuid_Ch2_DeviceWidth, - Help "NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch2_DramDensity, "Ch2_DramDensity", &gBroxtonFspPkgTokenSpaceGuid_Ch2_DramDensity, - Help "NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device density per rank (per Chip Select). The simplest way of identifying the density per rank is to divide the total SoC memory channel density by the number of ranks. For DDR3L: Must specify the DRAM device density per DRAM device. For example, an 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_Option, "Ch2_Option", HEX, - Help "BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] Bank Address Hashing Enable. See Address Mapping section for full description: 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_OdtConfig, "Ch2_OdtConfig", HEX, - Help "[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 OHMS or so roughly. Purpose: Save power on these technologies which burn power directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The customer needs to choose this based on their actual board strapping (how they tie the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS signals). Purpose: To improve signal integrity and provide a much more optimized CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_TristateClk1, "Ch2_TristateClk1", HEX, - Help "Not used" - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch2_Mode2N, "Ch2_Mode2N", &gBroxtonFspPkgTokenSpaceGuid_Ch2_Mode2N, - Help "DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command mode that provides more setup and hold time for DRAM commands on the DRAM command bus. This is useful for platforms with unusual CMD bus routing or marginal signal integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and Control training), 1 - Force 2N Mode" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_OdtLevels, "Ch2_OdtLevels", HEX, - Help "DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_RankEnable, "Ch3_RankEnable", HEX, - Help "NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be set to 1 to enable use of this rank." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch3_DeviceWidth, "Ch3_DeviceWidth", &gBroxtonFspPkgTokenSpaceGuid_Ch3_DeviceWidth, - Help "NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch3_DramDensity, "Ch3_DramDensity", &gBroxtonFspPkgTokenSpaceGuid_Ch3_DramDensity, - Help "NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device density per rank (per Chip Select). The simplest way of identifying the density per rank is to divide the total SoC memory channel density by the number of ranks. For DDR3L: Must specify the DRAM device density per DRAM device. For example, an 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_Option, "Ch3_Option", HEX, - Help "BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] Bank Address Hashing Enable. See Address Mapping section for full description: 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_OdtConfig, "Ch3_OdtConfig", HEX, - Help "[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 OHMS or so roughly. Purpose: Save power on these technologies which burn power directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The customer needs to choose this based on their actual board strapping (how they tie the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS signals). Purpose: To improve signal integrity and provide a much more optimized CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_TristateClk1, "Ch3_TristateClk1", HEX, - Help "Not used" - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Ch3_Mode2N, "Ch3_Mode2N", &gBroxtonFspPkgTokenSpaceGuid_Ch3_Mode2N, - Help "DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command mode that provides more setup and hold time for DRAM commands on the DRAM command bus. This is useful for platforms with unusual CMD bus routing or marginal signal integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and Control training), 1 - Force 2N Mode" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_OdtLevels, "Ch3_OdtLevels", HEX, - Help "DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW (default), 1 - ODT_AB_HIGH_HIGH" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_RmtCheckRun, "RmtCheckRun", HEX, - Help "Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK" - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_RmtMarginCheckScaleHighThreshold, "RmtMarginCheckScaleHighThreshold", HEX, - Help "Percentage used to determine the margin tolerances over the failing margin." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch0_Bit_swizzling, "Ch0_Bit_swizzling", HEX, - Help "Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes need to follow the DQ byte lane they correspond too. So for example if you have DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion can arrise from the fact that the indexes to the array do not necessarily map 1:1 to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates a 2 physical channels need to be stuffed and operated together. Are the CHx_A and CHx_B physical channels operated in tandem or completely separate? If separate, why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you have 2 channels in order to power gate one PHY, those two channel populated must be on one PHY instance. So yes all channels are independent of each other, but there are some restrictions on how they need to be populated. Q: How is it that an LPDDR4 device is identified as having a x16 width when all 32-bits are used at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel the CS of the two devices in the same die are connected together to make a single rank of one x32 channel (SDP). The second die in the DDP package makes the second rank." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch1_Bit_swizzling, "Ch1_Bit_swizzling", HEX, - Help "Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch2_Bit_swizzling, "Ch2_Bit_swizzling", HEX, - Help "Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Ch3_Bit_swizzling, "Ch3_Bit_swizzling", HEX, - Help "Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_MsgLevelMask, "MsgLevelMask", HEX, - Help "32 bits used to mask out debug messages. Masking out bit 0 mask all other messages." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTablePinNum, "PreMem GPIO Pin Number for each table", HEX, - Help "Number of Pins in each PreMem GPIO Table. 0(Default)." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTablePtr, "PreMem GPIO Table Pointer", HEX, - Help "Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default)." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreMemGpioTableEntryNum, "PreMem GPIO Table Entry Number. Currently maximum entry number is 4", HEX, - Help "Number of Entries in PreMem GPIO Table. 0(Default)." - "Valid range: 0x0 ~ 0x04" - Combo $gBroxtonFspPkgTokenSpaceGuid_EnhancePort8xhDecoding, "Enhance the port 8xh decoding", &EN_DIS, - Help "Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SpdWriteEnable, "SPD Data Write", &EN_DIS, - Help "Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_MrcDataSaving, "MRC Training Data Saving", &EN_DIS, - Help "Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_OemLoadingBase, "OEM File Loading Address", HEX, - Help "Determine the memory base address to load a specified file from CSE file system after memory is available." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditText $gBroxtonFspPkgTokenSpaceGuid_OemFileName, "OEM File Name to Load", - Help "Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded." - Combo $gBroxtonFspPkgTokenSpaceGuid_eMMCTraceLen, "eMMC Trace Length", &gBroxtonFspPkgTokenSpaceGuid_eMMCTraceLen, - Help "Select eMMC trace length to load OEM file from when loading OEM file name is specified. 0x0:Long(Default), 0x1:Short." - Combo $gBroxtonFspPkgTokenSpaceGuid_SkipCseRbp, "Skip CSE RBP to support zero sized IBB", &EN_DIS, - Help "Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of CSE. 0x00:Disable(Default), 0x01:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_NpkEn, "Npk Enable", &gBroxtonFspPkgTokenSpaceGuid_NpkEn, - Help "Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_FwTraceEn, "FW Trace Enable", &EN_DIS, - Help "Enable/Disable FW Trace. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_FwTraceDestination, "FW Trace Destination", HEX, - Help "FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, 4-NPK_TRACE_TO_PTI(Default)." - "Valid range: 0x1 ~ 0x04" - Combo $gBroxtonFspPkgTokenSpaceGuid_RecoverDump, "NPK Recovery Dump", &EN_DIS, - Help "Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_Msc0Wrap, "Memory Region 0 Buffer WrapAround", HEX, - Help "Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default)." - "Valid range: 0x0 ~ 0x01" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Msc1Wrap, "Memory Region 1 Buffer WrapAround", HEX, - Help "Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default)." - "Valid range: 0x0 ~ 0x01" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Msc0Size, "Memory Region 0 Buffer Size", HEX, - Help "Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB." - "Valid range: 0x0 ~ 0x07" - EditNum $gBroxtonFspPkgTokenSpaceGuid_Msc1Size, "Memory Region 1 Buffer Size", HEX, - Help "Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB." - "Valid range: 0x0 ~ 0x07" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PtiMode, "PTI Mode", HEX, - Help "PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16." - "Valid range: 0x0 ~ 0x04" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PtiTraining, "PTI Training", HEX, - Help "PTI Training. 0-off(Default), 1-6=1-6." - "Valid range: 0x0 ~ 0x06" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PtiSpeed, "PTI Speed", HEX, - Help "PTI Speed. 0-full, 1-half, 2-quarter(Default)." - "Valid range: 0x0 ~ 0x02" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PunitMlvl, "Punit Message Level", HEX, - Help "Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4." - "Valid range: 0x0 ~ 0x04" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PmcMlvl, "PMC Message Level", HEX, - Help "PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4." - "Valid range: 0x0 ~ 0x04" - Combo $gBroxtonFspPkgTokenSpaceGuid_SwTraceEn, "SW Trace Enable", &EN_DIS, - Help "Enable/Disable SW Trace. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PeriodicRetrainingDisable, "Periodic Retraining Disable", &gBroxtonFspPkgTokenSpaceGuid_PeriodicRetrainingDisable, - Help "Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic Retraining for debug purposes. Periodic Retraining should be enabled in production. Periodic retraining allows the platform to operate reliably over a larger voltage and temperature range. This field has no effect for DDR3L and LPDDR3 memory type configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic Retraining (debug configuration only)" - Combo $gBroxtonFspPkgTokenSpaceGuid_EnableResetSystem, "Enable Reset System", &gBroxtonFspPkgTokenSpaceGuid_EnableResetSystem, - Help " Enable FSP to trigger reset instead of returning reset request. 0x00: Return the Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside FSP instead of returning from the API." - Combo $gBroxtonFspPkgTokenSpaceGuid_EnableS3Heci2, "Enable HECI2 in S3 resume path", &gBroxtonFspPkgTokenSpaceGuid_EnableS3Heci2, - Help " Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ; 0x01: Enable HECI2 in S3 resume path.(Default)" - EditNum $gBroxtonFspPkgTokenSpaceGuid_StartTimerTickerOfPfetAssert, "PCIE SLOT Power Enable Assert Time - PFET.", HEX, - Help "ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer who designed the board PCIE slot Power automatically enabled, can pass value of zero here." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_RtEn, "Real Time Enabling", &EN_DIS, - Help "Real-Time Feature Configuration Bits settings. 0x0:Disabled (default), 0x1:Enabled" - Combo $gBroxtonFspPkgTokenSpaceGuid_SkipPciePowerSequence, "Skip Pcie Power Sequence", &gBroxtonFspPkgTokenSpaceGuid_SkipPciePowerSequence, - Help "UPD To Skip PciePowerSequence in FSP if set this UPD is set to 1. 0x0:Disabled (default), 0x1:Skip" -EndPage - -Page "FSP SiliconInit Settings" - EditNum $gBroxtonFspPkgTokenSpaceGuid_ActiveProcessorCores, "ActiveProcessorCores", HEX, - Help "Number of active cores. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableCore1, "Disable Core1", &EN_DIS, - Help "Disable/Enable Core1. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableCore2, "Disable Core2", &EN_DIS, - Help "Disable/Enable Core2. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableCore3, "Disable Core3", &EN_DIS, - Help "Disable/Enable Core3. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_VmxEnable, "VMX Enable", &EN_DIS, - Help "Enable or Disable VMX. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_ProcTraceMemSize, "Memory region allocation for Processor Trace", HEX, - Help "Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default)" - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_ProcTraceEnable, "Enable Processor Trace", &EN_DIS, - Help "Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_Eist, "Eist", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_BootPState, "Boot PState", HEX, - Help "Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_EnableCx, "CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_C1e, "Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_BiProcHot, "Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_PkgCStateLimit, "Max Pkg Cstate", HEX, - Help "Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_CStateAutoDemotion, "C-State auto-demotion", HEX, - Help "C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion to C1 and C3." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_CStateUnDemotion, "C-State un-demotion", HEX, - Help "C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_MaxCoreCState, "Max Core C-State", HEX, - Help "Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_PkgCStateDemotion, "Package C-State Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Package C-State Un-demotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_HdaVerbTableEntryNum, "SC HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table. 0(Default)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_HdaVerbTablePtr, "SC HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table. 0x00000000(Default)." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_P2sbUnhide, "Enable/Disable P2SB device hidden.", &EN_DIS, - Help "Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_IpuEn, "IPU Enable/Disable", &EN_DIS, - Help "Enable/Disable IPU Device. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_IpuAcpiMode, "IMGU ACPI mode selection", &gBroxtonFspPkgTokenSpaceGuid_IpuAcpiMode, - Help "0:Auto, 1:IGFX Child device(Default), 2:ACPI device." - Combo $gBroxtonFspPkgTokenSpaceGuid_ForceWake, "Enable ForceWake", &EN_DIS, - Help "Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_GttMmAdr, "GttMmAdr", HEX, - Help "GttMmAdr structure for initialization. 0xBF000000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_GmAdr, "GmAdr", HEX, - Help "GmAdr structure for initialization. 0xA0000000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_PavpLock, "Enable PavpLock", &EN_DIS, - Help "Enable/disable PavpLock. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_GraphicsFreqModify, "Enable GraphicsFreqModify", &EN_DIS, - Help "Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_GraphicsFreqReq, "Enable GraphicsFreqReq", &EN_DIS, - Help "Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_GraphicsVideoFreq, "Enable GraphicsVideoFreq", &EN_DIS, - Help "Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PmLock, "Enable PmLock", &EN_DIS, - Help "Enable/disable PmLock. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_DopClockGating, "Enable DopClockGating", &EN_DIS, - Help "Enable/disable DopClockGating. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_UnsolicitedAttackOverride, "Enable UnsolicitedAttackOverride", &EN_DIS, - Help "Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_WOPCMSupport, "Enable WOPCMSupport", &EN_DIS, - Help "Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_WOPCMSize, "Enable WOPCMSize", &EN_DIS, - Help "Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PowerGating, "Enable PowerGating", &EN_DIS, - Help "Enable/disable PowerGating. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_UnitLevelClockGating, "Enable UnitLevelClockGating", &EN_DIS, - Help "Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_FastBoot, "Enable FastBoot", &EN_DIS, - Help "Enable/disable FastBoot. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_DynSR, "Enable DynSR", &EN_DIS, - Help "Enable/disable DynSR. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_SaIpuEnable, "Enable SaIpuEnable", &EN_DIS, - Help "Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PmSupport, "GT PM Support", &EN_DIS, - Help "Enable/Disable GT power management support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_EnableRenderStandby, "RC6(Render Standby)", &EN_DIS, - Help "Enable/Disable render standby support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PavpEnable, "PAVP Enable", &EN_DIS, - Help "Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PavpPr3, "PAVP PR3", &EN_DIS, - Help "Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gBroxtonFspPkgTokenSpaceGuid_CdClock, - Help "0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_WriteProtectionEnable, "Write Protection Support", HEX, - Help "Enable/disable Write Protection. 0:Disable, 1:Enable(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_ReadProtectionEnable, "Read Protection Support", HEX, - Help "Enable/disable Read Protection. 0:Disable, 1:Enable(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_ProtectedRangeLimit, "Protected Range Limitation", HEX, - Help "The address of the upper limit of protection, 0x0FFFh(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_ProtectedRangeBase, "Protected Range Base", HEX, - Help "The base address of the upper limit of protection. 0x0000(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_Gmm, "Enable SC Gaussian Mixture Models", &EN_DIS, - Help "Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingPgcbClkTrunk, "GMM Clock Gating - PGCB Clock Trunk", &EN_DIS, - Help "Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSb, "GMM Clock Gating - Sideband", &EN_DIS, - Help "Enable/disable Sideband. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSbClkTrunk, "GMM Clock Gating - Sideband", &EN_DIS, - Help "Enable/disable Sideband. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingSbClkPartition, "GMM Clock Gating - Sideband Clock Partition", &EN_DIS, - Help "Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingCore, "GMM Clock Gating - Core", &EN_DIS, - Help "Enable/disable Core. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingDma, "GMM Clock Gating - DMA", &EN_DIS, - Help "Enable/disable DMA. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingRegAccess, "GMM Clock Gating - Register Access", &EN_DIS, - Help "Enable/disable Register Access. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingHost, "GMM Clock Gating - Host", &EN_DIS, - Help "Enable/disable Host. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingPartition, "GMM Clock Gating - Partition", &EN_DIS, - Help "Enable/disable Partition. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ClkGatingTrunk, "Clock Gating - Trunk", &EN_DIS, - Help "Enable/disable Trunk. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdaEnable, "HD Audio Support", &EN_DIS, - Help "Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_DspEnable, "HD Audio DSP Support", &EN_DIS, - Help "Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_Pme, "Azalia wake-on-ring", &EN_DIS, - Help "Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferOwnership, "HD-Audio I/O Buffer Ownership", &gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferOwnership, - Help "Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)" - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferVoltage, "HD-Audio I/O Buffer Voltage", &gBroxtonFspPkgTokenSpaceGuid_HdAudioIoBufferVoltage, - Help "HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioVcType, "HD-Audio Virtual Channel Type", &gBroxtonFspPkgTokenSpaceGuid_HdAudioVcType, - Help "HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioLinkFrequency, "HD-Audio Link Frequency", &gBroxtonFspPkgTokenSpaceGuid_HdAudioLinkFrequency, - Help "HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkFrequency, "HD-Audio iDisp-Link Frequency", &gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkFrequency, - Help "HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkTmode, "HD-Audio iDisp-Link T-Mode", &gBroxtonFspPkgTokenSpaceGuid_HdAudioIDispLinkTmode, - Help "HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T." - Combo $gBroxtonFspPkgTokenSpaceGuid_DspEndpointDmic, "HD-Audio Disp DMIC", &gBroxtonFspPkgTokenSpaceGuid_DspEndpointDmic, - Help "HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array." - Combo $gBroxtonFspPkgTokenSpaceGuid_DspEndpointBluetooth, "HD-Audio Bluetooth", &EN_DIS, - Help "Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_DspEndpointI2sSkp, "HD-Audio I2S SHK", &EN_DIS, - Help "Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_DspEndpointI2sHp, "HD-Audio I2S HP", &EN_DIS, - Help "Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_AudioCtlPwrGate, "HD-Audio Controller Power Gating", &EN_DIS, - Help "Enable/Disable HD-Audio Controller Power Gating. This option is deprecated." - Combo $gBroxtonFspPkgTokenSpaceGuid_AudioDspPwrGate, "HD-Audio ADSP Power Gating", &EN_DIS, - Help "Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated." - Combo $gBroxtonFspPkgTokenSpaceGuid_Mmt, "HD-Audio CSME Memory Transfers", &gBroxtonFspPkgTokenSpaceGuid_Mmt, - Help "Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2." - Combo $gBroxtonFspPkgTokenSpaceGuid_Hmt, "HD-Audio Host Memory Transfers", &gBroxtonFspPkgTokenSpaceGuid_Hmt, - Help "Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2." - Combo $gBroxtonFspPkgTokenSpaceGuid_HDAudioPwrGate, "HD-Audio Power Gating", &EN_DIS, - Help "Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_HDAudioClkGate, "HD-Audio Clock Gatingn", &EN_DIS, - Help "Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_DspFeatureMask, "Bitmask of DSP Feature", HEX, - Help "Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_DspPpModuleMask, "Bitmask of supported DSP Post-Processing Modules", HEX, - Help "Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_BiosCfgLockDown, "HD-Audio BIOS Configuration Lock Down", &EN_DIS, - Help "Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. This option is deprecated" - Combo $gBroxtonFspPkgTokenSpaceGuid_Hpet, "Enable High Precision Timer", &EN_DIS, - Help "Enable/Disable Hpet. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_HpetBdfValid, "Hpet Valid BDF Value", &EN_DIS, - Help "Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_HpetBusNumber, "Bus Number of Hpet", HEX, - Help "Completer ID of Bus Number of Hpet. Default = 0xFA(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_HpetDeviceNumber, "Device Number of Hpet", HEX, - Help "Completer ID of Device Number of Hpet. 0x1F(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_HpetFunctionNumber, "Function Number of Hpet", HEX, - Help "Completer ID of Function Number of Hpet. 0x00(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_IoApicBdfValid, "IoApic Valid BDF Value", &EN_DIS, - Help "Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_IoApicBusNumber, "Bus Number of IoApic", HEX, - Help "Completer ID of Bus Number of IoApic. 0xFA(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_IoApicDeviceNumber, "Device Number of IoApic", HEX, - Help "Completer ID of Device Number of IoApic. 0x0F(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_IoApicFunctionNumber, "Function Number of IoApic", HEX, - Help "Completer ID of Function Number of IoApic. 0x00(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_IoApicEntry24_119, "IOAPIC Entry 24-119", &EN_DIS, - Help "Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_IoApicId, "IO APIC ID", HEX, - Help "This member determines IOAPIC ID. 0x01(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_IoApicRangeSelect, "IoApic Range", HEX, - Help "Define address bits 19:12 for the IOxAPIC range. 0x00(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_IshEnable, "ISH Controller", &EN_DIS, - Help "Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_BiosInterface, "BIOS Interface Lock Down", &EN_DIS, - Help "Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_BiosLock, "Bios LockDown Enable", &EN_DIS, - Help "Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_SpiEiss, "SPI EISS Status", &EN_DIS, - Help "Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_BiosLockSwSmiNumber, "BiosLock SWSMI Number", HEX, - Help "This member describes the SwSmi value for Bios Lock. 0xA9(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_LPSS_S0ixEnable, "LPSS IOSF PMCTL S0ix Enable", &EN_DIS, - Help "Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_I2cClkGateCfg, "LPSS I2C Clock Gating Configuration", HEX, - Help "Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_HsuartClkGateCfg, "PSS HSUART Clock Gating Configuration", HEX, - Help "Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SpiClkGateCfg, "LPSS SPI Clock Gating Configuration", HEX, - Help "Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default)." - "Valid range: 0x0000 ~ 0xFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c0Enable, "I2C Device 0", &gBroxtonFspPkgTokenSpaceGuid_I2c0Enable, - Help "Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c1Enable, "I2C Device 1", &gBroxtonFspPkgTokenSpaceGuid_I2c1Enable, - Help "Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c2Enable, "I2C Device 2", &gBroxtonFspPkgTokenSpaceGuid_I2c2Enable, - Help "Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c3Enable, "I2C Device 3", &gBroxtonFspPkgTokenSpaceGuid_I2c3Enable, - Help "Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c4Enable, "I2C Device 4", &gBroxtonFspPkgTokenSpaceGuid_I2c4Enable, - Help "Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c5Enable, "I2C Device 5", &gBroxtonFspPkgTokenSpaceGuid_I2c5Enable, - Help "Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c6Enable, "I2C Device 6", &gBroxtonFspPkgTokenSpaceGuid_I2c6Enable, - Help "Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_I2c7Enable, "I2C Device 7", &gBroxtonFspPkgTokenSpaceGuid_I2c7Enable, - Help "Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Hsuart0Enable, "UART Device 0", &gBroxtonFspPkgTokenSpaceGuid_Hsuart0Enable, - Help "Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Hsuart1Enable, "UART Device 1", &gBroxtonFspPkgTokenSpaceGuid_Hsuart1Enable, - Help "Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Hsuart2Enable, "UART Device 2", &gBroxtonFspPkgTokenSpaceGuid_Hsuart2Enable, - Help "Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Hsuart3Enable, "UART Device 3", &gBroxtonFspPkgTokenSpaceGuid_Hsuart3Enable, - Help "Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Spi0Enable, "SPI UART Device 0", &gBroxtonFspPkgTokenSpaceGuid_Spi0Enable, - Help "Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Spi1Enable, "SPI UART Device 1", &gBroxtonFspPkgTokenSpaceGuid_Spi1Enable, - Help "Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_Spi2Enable, "SPI UART Device 2", &gBroxtonFspPkgTokenSpaceGuid_Spi2Enable, - Help "Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_OsDbgEnable, "OS Debug Feature", &EN_DIS, - Help "Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_DciEn, "DCI Feature", &EN_DIS, - Help "Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_Uart2KernelDebugBaseAddress, "UART Debug Base Address", HEX, - Help "UART Debug Base Address. 0x00000000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_PcieClockGatingDisabled, "Enable PCIE Clock Gating", &gBroxtonFspPkgTokenSpaceGuid_PcieClockGatingDisabled, - Help "Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PcieRootPort8xhDecode, "Enable PCIE Root Port 8xh Decode", &EN_DIS, - Help "Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_Pcie8xhDecodePortIndex, "PCIE 8xh Decode Port Index", HEX, - Help "PCIE 8xh Decode Port Index. 0x00(Default)." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_PcieRootPortPeerMemoryWriteEnable, "Enable PCIE Root Port Peer Memory Write", &EN_DIS, - Help "Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieAspmSwSmiNumber, "PCIE SWSMI Number", HEX, - Help "This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRootPortEn, "PCI Express Root Port", HEX, - Help "Control the PCI Express Root Port . 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpHide, "Hide PCIE Root Port Configuration Space", HEX, - Help "Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCIE Root Port Slot Implement", HEX, - Help "Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpHotPlug, "Hot Plug", HEX, - Help "PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpPmSci, "PCIE PM SCI", HEX, - Help "Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpExtSync, "PCIE Root Port Extended Sync", HEX, - Help "Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Transmitter Half Swing", HEX, - Help "Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "ACS", HEX, - Help "Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqSupported, "Clock Request Support", HEX, - Help "Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqNumber, "Configure CLKREQ Number", HEX, - Help "Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, 0x01, 0x02, 0x03." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "CLKREQ# Detection", HEX, - Help "Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_AdvancedErrorReporting, "Advanced Error Reporting", HEX, - Help "Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PmeInterrupt, "PME Interrupt", HEX, - Help "Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_UnsupportedRequestReport, " URR", HEX, - Help "PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_FatalErrorReport, " FER", HEX, - Help "PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_NoFatalErrorReport, " NFER", HEX, - Help "PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_CorrectableErrorReport, " CER", HEX, - Help "PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnFatalError, " SEFE", HEX, - Help "Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnNonFatalError, " SENFE", HEX, - Help "Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SystemErrorOnCorrectableError, " SECE", HEX, - Help "Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSpeed, "PCIe Speed", HEX, - Help "Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PhysicalSlotNumber, "Physical Slot Number", HEX, - Help "Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "CTO", HEX, - Help "Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PtmEnable, "PTM Support", HEX, - Help "Enable/Disable PTM Support. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpAspm, "ASPM", HEX, - Help "PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, 4:Auto(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpL1Substates, "L1 Substates", HEX, - Help "PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCH PCIe LTR", HEX, - Help "PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE LTR Lock", HEX, - Help "PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_PmeB0S5Dis, "PME_B0_S5 Disable bit", &EN_DIS, - Help "PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_PciClockRun, "PCI Clock Run", &EN_DIS, - Help "This member describes whether or not the PCI ClockRun feature of SC should be enabled. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_Timer8254ClkSetting, "Enable/Disable Timer 8254 Clock Setting", &EN_DIS, - Help "Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_EnableSata, "Chipset SATA", &EN_DIS, - Help "Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SataMode, "SATA Mode Selection", &gBroxtonFspPkgTokenSpaceGuid_SataMode, - Help "Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID." - Combo $gBroxtonFspPkgTokenSpaceGuid_SataSalpSupport, "Aggressive LPM Support", &EN_DIS, - Help "Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SataPwrOptEnable, "SATA Power Optimization", &EN_DIS, - Help "Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_eSATASpeedLimit, "eSATA Speed Limit", &EN_DIS, - Help "Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_SpeedLimit, "SATA Speed Limit", &gBroxtonFspPkgTokenSpaceGuid_SpeedLimit, - Help "SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsEnable, "SATA Port", HEX, - Help "Enable or Disable SATA Port. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsDevSlp, "SATA Port DevSlp", HEX, - Help "Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsHotPlug, "SATA Port HotPlug", HEX, - Help "Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Mechanical Presence Switch", HEX, - Help "Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires hardware support. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsExternal, "External SATA Ports", HEX, - Help "Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsSpinUp, "Spin Up Device", HEX, - Help "Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "SATA Solid State", HEX, - Help "Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard Disk Drive(Default), 1:Solid State Drive." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, " DITO Configuration", HEX, - Help "Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsDmVal, "DM Value", HEX, - Help "DM Value. 0:Minimum, 0x0F:Maximum(Default)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsDitoVal, "DITO Value", HEX, - Help "DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SubSystemVendorId, "Subsystem Vendor ID", HEX, - Help "Subsystem Vendor ID. 0x8086(Default)." - "Valid range: 0x0000 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SubSystemId, "Subsystem ID", HEX, - Help "Subsystem ID. 0x7270(Default)." - "Valid range: 0x0000 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_CRIDSettings, "CRIDSettings", HEX, - Help "PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3." - "Valid range: 0x00 ~ 0xFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_ResetSelect, "ResetSelect", HEX, - Help "ResetSelect. 0x6:warm reset(Default), 0xE:cold reset." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_SdcardEnabled, "SD Card Support (D27:F0)", &EN_DIS, - Help "Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_eMMCEnabled, "SeMMC Support (D28:F0)", &EN_DIS, - Help "Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_eMMCHostMaxSpeed, "eMMC Max Speed", &gBroxtonFspPkgTokenSpaceGuid_eMMCHostMaxSpeed, - Help "Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50." - Combo $gBroxtonFspPkgTokenSpaceGuid_UfsEnabled, "UFS Support (D29:F0)", &EN_DIS, - Help "Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SdioEnabled, "SDIO Support (D30:F0)", &EN_DIS, - Help "Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_GppLock, "GPP Lock Feature", &EN_DIS, - Help "Enable/Disable GPP lock. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_SirqEnable, "Serial IRQ", &EN_DIS, - Help "Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SirqMode, "Serial IRQ Mode", &EN_DIS, - Help "Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_StartFramePulse, "Start Frame Pulse Width", &gBroxtonFspPkgTokenSpaceGuid_StartFramePulse, - Help "Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk." - Combo $gBroxtonFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_ArpEnable, "SMBus ARP Support", &EN_DIS, - Help "Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_NumRsvdSmbusAddresses, "SMBus Table Elements", HEX, - Help "The number of elements in the Reserved SMBus Address Table. 0x0080(Default)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_RsvdSmbusAddressTable, "Reserved SMBus Address Table", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableComplianceMode, "XHCI Disable Compliance Mode", &EN_DIS, - Help "Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True." - Combo $gBroxtonFspPkgTokenSpaceGuid_UsbPerPortCtl, "USB Per-Port Control", &EN_DIS, - Help "Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_Usb30Mode, "xHCI Mode", &gBroxtonFspPkgTokenSpaceGuid_Usb30Mode, - Help "Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUs20bOverCurrentPin, "USB20 Over Current Pin", HEX, - Help "Over Current Pin number of USB 2.0 Port. 0x00(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_UsbOtg, "XDCI Support", &gBroxtonFspPkgTokenSpaceGuid_UsbOtg, - Help "Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode." - Combo $gBroxtonFspPkgTokenSpaceGuid_HsicSupportEnable, "Enable XHCI HSIC Support", &EN_DIS, - Help "Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUs30bOverCurrentPin, "USB20 Over Current Pin", HEX, - Help "Over Current Pin number of USB 3.0 Port. 0x01(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SsicPortEnable, "Enable XHCI SSIC Support", HEX, - Help "Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. 0x00(Default)." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DlanePwrGating, "SSIC Dlane PowerGating", &EN_DIS, - Help "Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_VtdEnable, "VT-d", &EN_DIS, - Help "Enable/Disable VT-d. 0:Disable(Default), 1:Enable." - Combo $gBroxtonFspPkgTokenSpaceGuid_LockDownGlobalSmi, "SMI Lock bit", &EN_DIS, - Help "Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, 1:Enable(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_ResetWaitTimer, "HDAudio Delay Timer", HEX, - Help "The delay timer after Azalia reset. 0x012C(Default)." - "Valid range: 0x0000 ~ 0xFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_RtcLock, "RTC Lock Bits", &EN_DIS, - Help "Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_SataTestMode, "SATA Test Mode Selection", &EN_DIS, - Help "Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_SsicRate, "XHCI SSIC RATE", HEX, - Help "Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series." - "Valid range: 0x00 ~ 0xFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DynamicPowerGating, "SMBus Dynamic Power Gating", &EN_DIS, - Help "Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable." - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, " Snoop Latency Override", HEX, - Help "Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, " Snoop Latency Value", HEX, - Help "LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, " Snoop Latency Multiplier", HEX, - Help "LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize(Default), 1: Skip" - Combo $gBroxtonFspPkgTokenSpaceGuid_DciAutoDetect, "DCI Auto Detect", &EN_DIS, - Help "Deprecated: Enable/disable DCI AUTO mode. Enabled(Default)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpLtrMaxNonSnoopLatency, "Max Non-Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, " Non Snoop Latency Override", HEX, - Help "Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_TcoTimerHaltLock, "Halt and Lock TCO Timer", &gBroxtonFspPkgTokenSpaceGuid_TcoTimerHaltLock, - Help "Halt and Lock the TCO Timer (Watchdog)." - Combo $gBroxtonFspPkgTokenSpaceGuid_PwrBtnOverridePeriod, "Power Button Override Period", &gBroxtonFspPkgTokenSpaceGuid_PwrBtnOverridePeriod, - Help "specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, " Non Snoop Latency Value", HEX, - Help "LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default)." - "Valid range: 0x0000 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, " Non Snoop Latency Multiplier", HEX, - Help "LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE Root Port Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. 0x00(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE Root Port Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. 0x00(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_DisableNativePowerButton, "Power Button Native Mode Disable", &EN_DIS, - Help "Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default))" - Combo $gBroxtonFspPkgTokenSpaceGuid_PowerButterDebounceMode, "Power Button Debounce Mode", &EN_DIS, - Help "Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdioTxCmdCntl, "SDIO_TX_CMD_DLL_CNTL", HEX, - Help "SDIO_TX_CMD_DLL_CNTL. 0x505(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdioTxDataCntl1, "SDIO_TX_DATA_DLL_CNTL1", HEX, - Help "SDIO_TX_DATA_DLL_CNTL1. 0xE(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdioTxDataCntl2, "SDIO_TX_DATA_DLL_CNTL2", HEX, - Help "SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdioRxCmdDataCntl1, "SDIO_RX_CMD_DATA_DLL_CNTL1", HEX, - Help "SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdioRxCmdDataCntl2, "SDIO_RX_CMD_DATA_DLL_CNTL2", HEX, - Help "SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardTxCmdCntl, "SDCARD_TX_CMD_DLL_CNTL", HEX, - Help "SDCARD_TX_CMD_DLL_CNTL. 0x505(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardTxDataCntl1, "SDCARD_TX_DATA_DLL_CNTL1", HEX, - Help "SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardTxDataCntl2, "SDCARD_TX_DATA_DLL_CNTL2", HEX, - Help "SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardRxCmdDataCntl1, "SDCARD_RX_CMD_DATA_DLL_CNTL1", HEX, - Help "SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardRxStrobeCntl, "SDCARD_RX_STROBE_DLL_CNTL", HEX, - Help "SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SdcardRxCmdDataCntl2, "SDCARD_RX_CMD_DATA_DLL_CNTL2", HEX, - Help "SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcTxCmdCntl, "EMMC_TX_CMD_DLL_CNTL", HEX, - Help "EMMC_TX_CMD_DLL_CNTL. 0x505(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcTxDataCntl1, "EMMC_TX_DATA_DLL_CNTL1", HEX, - Help "EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcTxDataCntl2, "EMMC_TX_DATA_DLL_CNTL2", HEX, - Help "EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcRxCmdDataCntl1, "EMMC_RX_CMD_DATA_DLL_CNTL1", HEX, - Help "EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcRxStrobeCntl, "EMMC_RX_STROBE_DLL_CNTL", HEX, - Help "EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcRxCmdDataCntl2, "EMMC_RX_CMD_DATA_DLL_CNTL2", HEX, - Help "EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_EmmcMasterSwCntl, "EMMC_MASTER_DLL_CNTL", HEX, - Help "EMMC_MASTER_DLL_CNTL. 0x001(Default)." - "Valid range: 0x00000000 ~ 0xFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PcieRpSelectableDeemphasis, "PCIe Selectable De-emphasis", HEX, - Help "When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Monitor Mwait Enable", &EN_DIS, - Help "Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux based OS, this should be Disabled. 0:Disable, 1:Enable(Default)." - Combo $gBroxtonFspPkgTokenSpaceGuid_HdAudioDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - EditNum $gBroxtonFspPkgTokenSpaceGuid_IPC, "IRQ Interrupt Polarity Control", HEX, - Help "Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low" - "Valid range: 0x00000000 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_SataPortsDisableDynamicPg, "Disable ModPHY dynamic power gate", HEX, - Help "Disable ModPHY dynamic power gate for the specific SATA port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_InitS3Cpu, "Init CPU during S3 resume", &EN_DIS, - Help "0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume." - Combo $gBroxtonFspPkgTokenSpaceGuid_SkipPunitInit, "Skip P-unit Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize P-unit before SilicionInit API. 0: Initialize(Default), 1: Skip" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortTxPeHalf, "PerPort Half Bit Pre-emphasis", HEX, - Help "PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortPeTxiSet, "PerPort HS Pre-emphasis Bias", HEX, - Help "PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortTxiSet, "PerPort HS Transmitter Bias", HEX, - Help "PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20HsSkewSel, "Select the skew direction for HS transition", HEX, - Help "Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20IUsbTxEmphasisEn, "Per Port HS Transmitter Emphasis", HEX, - Help "Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20PerPortRXISet, "PerPort HS Receiver Bias", HEX, - Help "PerPort HS Receiver Bias. Value of register USB2_PER_PORT_PPX [19:17]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gBroxtonFspPkgTokenSpaceGuid_PortUsb20HsNpreDrvSel, "Delay/skew's strength control for HS driver", HEX, - Help "Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0]" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gBroxtonFspPkgTokenSpaceGuid_OsSelection, "OS Selection", &gBroxtonFspPkgTokenSpaceGuid_OsSelection, - Help "Windows or Android or Linux OS selection to be used by HDA, USB Common, PWM and PEI Graphics modules. Windows (default), Android, Linux" - Combo $gBroxtonFspPkgTokenSpaceGuid_DptfEnabled, "DPTF", &EN_DIS, - Help "Intel® Dynamic Platform and Thermal Framework. 0x0:Disabled (default), 0x1:Enabled" - Combo $gBroxtonFspPkgTokenSpaceGuid_PWMEnabled, "PWM Enabled", &EN_DIS, - Help "PWM Device Enabling. Windows needs this to be disabled, while Android needs this to be enabled. 0x0:Disabled (default), 0x1:Enabled" -EndPage - diff --git a/ApolloLakeFspBinPkg/FspBin/Fsp.fd b/ApolloLakeFspBinPkg/FspBin/Fsp.fd deleted file mode 100644 index 0c9c25a812b0ce378aca9fe30ac99ed1a5137752..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 548864 zcmc$_bzD?k*DyTvNDU>Sl!}7VAs`{$(%qtnFo;rvAnk}S90rvz5Jf;jKv0kpq=piu zyOdBFN)XKD`|Q1Xt-ba-=O_a4Kb!yem>9)qPQxc>aZV8g z;cmnm(gOfTO$+V)J#vIL;)Ci%1cLNnn&dyY`~THeauyLn2*k!7zui&J#Y)5ce5s=% zPtLHh02COsN}2z`o#Rqki;Xt0AR5`>O{nZ^aRzv6;W-#=@&Ci+&xi!H{R4s|z*3!7SpTFyX-oM+Q>HkUNV3Gu}#e+a>p#c2B@2mg9 z{5O?@@n2F1M9v=`zi0jp__ z!776GA3LB>2!t1@7wO$FPw#_y*bE1Quzyhh{~M70vG9N7g`M=D1_TAaLa@yLiUwF- z(u0OTD1e{eSB1ZG{{!+j9LWJ33=9AK#r>DwBox5T^k70jfd4ovXfS7Zj+q*sf5BbMya;*TImAl9G~&it4Ydf1`!u zw{OY*&i_UGyZ-n7|6`wH4olN|B-ixqyqrN=(<8h$7u&P@Ib?|Yq=*f2kY9XB5lj{~ z7f48H%1C6uhUEo+u4KFie8vEGhJSGs@x9^?auOmRND0H${OSJ%g5U+{BHmZ7-MIW4 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zpr=O8F9`B0&jO|Z>}>FavFO?qEmRar#Ru!%su!X}Lp-9eUDoC!3z=Z;54qf;^MP37p1x%9;PB?;-tO`Q@?%tBm9o+qCwpC&Jo&y_pm^W^j8 zzn3qNKQ8CwGPzu?kSpa;@@RRCTqW-&kCn&C)$(|Gf}EFY;}65%8-7>j(#+2?O(WhQ-793DhkVAQPETEsx;pi_)Jv)IwBBj= zre&r*2OX=*w2#uxr)3%@8VU_h7&btA=!PM|c(>7P91ZP|70{;JZ{A_qZTZUbwMA}= zwneIfO$B(V^bb>A-%H_t5m;5;$l#rk4?OoM6kM?5SSMuT#^#$uGSd6txbH&$8=n$Y AJOBUy diff --git a/BraswellFspBinPkg/FspBin/BraswellFsp.bsf b/BraswellFspBinPkg/FspBin/BraswellFsp.bsf deleted file mode 100644 index 0706e98..0000000 --- a/BraswellFspBinPkg/FspBin/BraswellFsp.bsf +++ /dev/null @@ -1,258 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2017, Intel Corporation. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "$BSWUPD$" - Skip 40 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_DEFAULT_ = 0x0004 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_DEFAULT_ = 0x0800 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1 1 bytes $_DEFAULT_ = 0xA0 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2 1 bytes $_DEFAULT_ = 0xA2 - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdDdr3AutoSelfRefreshEnable 1 bytes $_DEFAULT_ = 0 - Skip 204 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 bytes $_DEFAULT_ = 0 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 bytes $_DEFAULT_ = 1 - Skip 15 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode 1 bytes $_DEFAULT_ = 1 - Skip 27 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed 1 bytes $_DEFAULT_ = 3 - Skip 13 bytes - $gPlatformFspPkgTokenSpaceGuid_PMIC_I2CBus 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig 1 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdTurboMode 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings 1 bytes $_DEFAULT_ = 3 - $gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk 1 bytes $_DEFAULT_ = 1 - - Find "$BSWFSP$" - $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x01010800 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode - Selection 0x0 , "Disabled" - Selection 0x1 , "PCI Mode" - Selection 0x2 , "ACPI Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" - Selection 0x03 , "96 MB" - Selection 0x04 , "128 MB" - Selection 0x05 , "160 MB" - Selection 0x06 , "192 MB" - Selection 0x07 , "224 MB" - Selection 0x08 , "256 MB" - Selection 0x09 , "288 MB" - Selection 0x0A , "320 MB" - Selection 0x0B , "352 MB" - Selection 0x0C , "384 MB" - Selection 0x0D , "416 MB" - Selection 0x0E , "448 MB" - Selection 0x0F , "480 MB" - Selection 0x10 , "512 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn - Selection 0x00 , "Disable" - Selection 0x01 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig - Selection 0x1 , " ISP PCI Device as B0D2F0" - Selection 0x2 , " ISP PCI Device as B0D3F0" - Selection 0x3 , " ISP PCI Device as B0D3F0 with Virtual ISP B0D2F0" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe - Selection 0x2 , "ACPI Mode" - Selection 0x1 , "PCI Mode" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize - Selection 0x01 , "1 MB" - Selection 0x02 , "2 MB" - Selection 0x04 , "4 MB" - Selection 0x08 , "8 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize - Selection 0x400 , "1.0 GB" - Selection 0x600 , "1.5 GB" - Selection 0x800 , "2.0 GB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings - Selection 0 , " Disable" - Selection 1 , " Power" - Selection 2 , " Performance" - Selection 3 , " Power & Performance" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdGttSize - Selection 0x1 , "1 MB" - Selection 0x2 , "2 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode - Selection 0x0 , "Disabled" - Selection 0x1 , "PCI Mode" - Selection 0x2 , "ACPI Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed - Selection 1 , "GEN1" - Selection 2 , "GEN2" - Selection 3 , "GEN3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize - Selection 0x1 , "128 MB" - Selection 0x2 , "256 MB" - Selection 0x3 , "512 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable - Selection 0x00 , "DDR3" - Selection 0x01 , "LPDDR3" -EndList - -BeginInfoBlock - PPVer "1.0" - Description "Braswell platform" -EndInfoBlock - -Page "Platform" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdTurboMode, "Processor Turbo Mode", &EN_DIS, - Help "Enable/disable Processor Turbo Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings, "Pnp Setting Type", &gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings, - Help "Select Pnp type " - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk, "SdDetectChk", &EN_DIS, - Help "Check for Sd card detect " -EndPage - -Page "South Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode, "SD Card Mode", &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode, - Help "SD Card Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, - Help "Enable/disable HSUART0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, - Help "Enable/disable HSUART1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS, - Help "Enable/disable Azalia controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, - Help "Enable/disable XHCI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, - Help "Choose LPE Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, - Help "Enable/disable DMA0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, - Help "Enable/disable DMA1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, - Help "Enable/disable I2C0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, - Help "Enable/disable I2C1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, - Help "Enable/disable I2C2." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, - Help "Enable/disable I2C3." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, - Help "Enable/disable I2C4." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, - Help "Enable/disable I2C5." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, - Help "Enable/disable I2C6." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode, "eMMC Mode", &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode, - Help "EMMC Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed, "SATA Interface Speed", &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed, - Help "Select SATA controller Interface Speed." - Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, - Help "Enable/disable ISP." - Combo $gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig, "Select ISP Device Number", &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig, - Help "Select ISP PCI Device Configuration" -EndPage - -Page "North Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, - Help "Size of SMRAM memory reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "MMIO Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, - Help "Size of memory address space reserved for MMIO (Memory Mapped I/O)." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1, "DIMM 0 SPD SMBus Address", HEX, - Help "SPD Address of DIMM." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2, "DIMM 1 SPD SMBus Address", HEX, - Help "SPD Address of DIMM." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &gPlatformFspPkgTokenSpaceGuid_PcdGttSize, - Help "Select the GTT Size." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode, "Enable Legacy E/F segments decoding to ROM", &EN_DIS, - Help "If disabled, E0000h-FFFFFh decoding will be routed to DRAM." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable, "Enable DVFS", &EN_DIS, - Help "Enable/disable DVFS." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable, "MemoryType", &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable, - Help "To Configure Memory Type" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn, "CaMirrorEn", &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn, - Help "To Enable/Disable CaMirrorEn" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdDdr3AutoSelfRefreshEnable, "DDR3 Auto Self Refresh", &EN_DIS, - Help "Enable/Disable DDR3 Auto Self Refresh" -EndPage - diff --git a/BraswellFspBinPkg/FspBin/SecureBootEnabled/BSWFSP.fd b/BraswellFspBinPkg/FspBin/SecureBootEnabled/BSWFSP.fd deleted file mode 100644 index 219ea6d7dd3cb4394468ab887e9e77aa85539595..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 314368 zcmeFae|%Kcoi~0bGb96Z`)jsUA>UI&+3Nu6!P+Nb{R;{}a!TxY)L_>8UV90#mpL6dy zbMKjx?!KNM`^SEr7dQ9b_j#Ys`*S|$+;h)8_XnD0|84sHBad9yTYAg)uS~4(8MyS2 zHlD`_Yn$4dGZQYYS-bbdI!()Cup^r{BmF-6@u;>y)5az)yyLvm(VyM&KmNzU^Dg`T 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z-e}%t?lxaDkItBsk(E)DwL0siEKkgFlE~Abq_|!v#Y}hauay_uL?nJy(%2hVu?8{{zh0!%_eM diff --git a/BraswellFspBinPkg/FspBin/SecureBootEnabled/BraswellFsp.bsf b/BraswellFspBinPkg/FspBin/SecureBootEnabled/BraswellFsp.bsf deleted file mode 100644 index c5dbb2f..0000000 --- a/BraswellFspBinPkg/FspBin/SecureBootEnabled/BraswellFsp.bsf +++ /dev/null @@ -1,268 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2017, Intel Corporation. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "$BSWUPD$" - Skip 40 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_DEFAULT_ = 0x0004 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_DEFAULT_ = 0x0800 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1 1 bytes $_DEFAULT_ = 0xA0 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2 1 bytes $_DEFAULT_ = 0xA2 - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdDdr3AutoSelfRefreshEnable 1 bytes $_DEFAULT_ = 0 - Skip 204 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 bytes $_DEFAULT_ = 0 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 bytes $_DEFAULT_ = 1 - Skip 15 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode 1 bytes $_DEFAULT_ = 1 - Skip 27 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed 1 bytes $_DEFAULT_ = 3 - Skip 13 bytes - $gPlatformFspPkgTokenSpaceGuid_PMIC_I2CBus 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig 1 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdTurboMode 1 bytes $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings 1 bytes $_DEFAULT_ = 3 - $gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk 1 bytes $_DEFAULT_ = 1 - - Find "BSWSBFSP" - $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x01010800 - Skip 24 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 bytes $_DEFAULT_ = 2 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode - Selection 0x0 , "Disabled" - Selection 0x1 , "PCI Mode" - Selection 0x2 , "ACPI Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" - Selection 0x03 , "96 MB" - Selection 0x04 , "128 MB" - Selection 0x05 , "160 MB" - Selection 0x06 , "192 MB" - Selection 0x07 , "224 MB" - Selection 0x08 , "256 MB" - Selection 0x09 , "288 MB" - Selection 0x0A , "320 MB" - Selection 0x0B , "352 MB" - Selection 0x0C , "384 MB" - Selection 0x0D , "416 MB" - Selection 0x0E , "448 MB" - Selection 0x0F , "480 MB" - Selection 0x10 , "512 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn - Selection 0x00 , "Disable" - Selection 0x01 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig - Selection 0x1 , " ISP PCI Device as B0D2F0" - Selection 0x2 , " ISP PCI Device as B0D3F0" - Selection 0x3 , " ISP PCI Device as B0D3F0 with Virtual ISP B0D2F0" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe - Selection 0x2 , "ACPI Mode" - Selection 0x1 , "PCI Mode" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize - Selection 0x01 , "1 MB" - Selection 0x02 , "2 MB" - Selection 0x04 , "4 MB" - Selection 0x08 , "8 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize - Selection 0x400 , "1.0 GB" - Selection 0x600 , "1.5 GB" - Selection 0x800 , "2.0 GB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings - Selection 0 , " Disable" - Selection 1 , " Power" - Selection 2 , " Performance" - Selection 3 , " Power & Performance" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdGttSize - Selection 0x1 , "1 MB" - Selection 0x2 , "2 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode - Selection 0x0 , "Disabled" - Selection 0x1 , "PCI Mode" - Selection 0x2 , "ACPI Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed - Selection 1 , "GEN1" - Selection 2 , "GEN2" - Selection 3 , "GEN3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize - Selection 0x1 , "128 MB" - Selection 0x2 , "256 MB" - Selection 0x3 , "512 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable - Selection 0x00 , "DDR3" - Selection 0x01 , "LPDDR3" -EndList - -BeginInfoBlock - PPVer "1.0" - Description "Braswell platform" -EndInfoBlock - -Page "Platform" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, - Help "Enable/disable secure boot. Auto by default." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdTurboMode, "Processor Turbo Mode", &EN_DIS, - Help "Enable/disable Processor Turbo Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings, "Pnp Setting Type", &gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings, - Help "Select Pnp type " - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk, "SdDetectChk", &EN_DIS, - Help "Check for Sd card detect " -EndPage - -Page "South Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode, "SD Card Mode", &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode, - Help "SD Card Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, - Help "Enable/disable HSUART0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, - Help "Enable/disable HSUART1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS, - Help "Enable/disable Azalia controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, - Help "Enable/disable XHCI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, - Help "Choose LPE Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, - Help "Enable/disable DMA0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, - Help "Enable/disable DMA1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, - Help "Enable/disable I2C0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, - Help "Enable/disable I2C1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, - Help "Enable/disable I2C2." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, - Help "Enable/disable I2C3." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, - Help "Enable/disable I2C4." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, - Help "Enable/disable I2C5." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, - Help "Enable/disable I2C6." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode, "eMMC Mode", &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode, - Help "EMMC Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed, "SATA Interface Speed", &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed, - Help "Select SATA controller Interface Speed." - Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, - Help "Enable/disable ISP." - Combo $gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig, "Select ISP Device Number", &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig, - Help "Select ISP PCI Device Configuration" -EndPage - -Page "North Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, - Help "Size of SMRAM memory reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "MMIO Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, - Help "Size of memory address space reserved for MMIO (Memory Mapped I/O)." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1, "DIMM 0 SPD SMBus Address", HEX, - Help "SPD Address of DIMM." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2, "DIMM 1 SPD SMBus Address", HEX, - Help "SPD Address of DIMM." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &gPlatformFspPkgTokenSpaceGuid_PcdGttSize, - Help "Select the GTT Size." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode, "Enable Legacy E/F segments decoding to ROM", &EN_DIS, - Help "If disabled, E0000h-FFFFFh decoding will be routed to DRAM." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable, "Enable DVFS", &EN_DIS, - Help "Enable/disable DVFS." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable, "MemoryType", &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable, - Help "To Configure Memory Type" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn, "CaMirrorEn", &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn, - Help "To Enable/Disable CaMirrorEn" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdDdr3AutoSelfRefreshEnable, "DDR3 Auto Self Refresh", &EN_DIS, - Help "Enable/Disable DDR3 Auto Self Refresh" -EndPage - diff --git a/BraswellFspBinPkg/Include/FspUpdVpd.h b/BraswellFspBinPkg/Include/FspUpdVpd.h deleted file mode 100644 index 9ee0230..0000000 --- a/BraswellFspBinPkg/Include/FspUpdVpd.h +++ /dev/null @@ -1,539 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 - -typedef struct { - UINT32 VendorDeviceId; - UINT16 SubSystemId; - UINT8 RevisionId; /// 0xFF applies to all steppings - UINT8 FrontPanelSupport; - UINT16 NumberOfRearJacks; - UINT16 NumberOfFrontJacks; -} BL_PCH_AZALIA_VERB_TABLE_HEADER; - -typedef struct { - BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; - UINT32 *VerbTableData; -} BL_PCH_AZALIA_VERB_TABLE; - -typedef struct { - UINT8 Pme : 1; /// 0: Disable; 1: Enable - UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported - UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached - UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable - UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable - UINT8 Rsvdbits : 3; - UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform - BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) - UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds -} BL_PCH_AZALIA_CONFIG; - -typedef struct { - UINT32 Confg; - UINT32 ConfgChanges; - UINT32 Misc; - UINT32 MmioAddr; - CHAR16 *Name; -} BL_GPIO_FAMILY_INIT; - -typedef struct { - UINT32 Confg0; - UINT32 Confg0Changes; - UINT32 Confg1; - UINT32 Confg1Changes; - UINT32 Community; - UINT32 MmioAddr; - CHAR16 *Name; - UINT32 Misc; -} BL_GPIO_PAD_INIT; - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -typedef struct { -/** Offset 0x0020 -**/ - UINT64 Signature; -/** Offset 0x0028 -**/ - UINT8 Revision; -/** Offset 0x0029 -**/ - UINT8 UnusedUpdSpace2[7]; -/** Offset 0x0030 - Tseg Size - Size of SMRAM memory reserved. -**/ - UINT16 PcdMrcInitTsegSize; -/** Offset 0x0032 - MMIO Size - Size of memory address space reserved for MMIO (Memory Mapped I/O). -**/ - UINT16 PcdMrcInitMmioSize; -/** Offset 0x0034 - DIMM 0 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr1; -/** Offset 0x0035 - DIMM 1 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr2; -/** Offset 0x0036 -**/ - UINT8 PcdMemChannel0Config; -/** Offset 0x0037 -**/ - UINT8 PcdMemChannel1Config; -/** Offset 0x0038 -**/ - UINT32 PcdMemorySpdPtr; -/** Offset 0x003C - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics -**/ - UINT8 PcdIgdDvmt50PreAlloc; -/** Offset 0x003D - Aperture Size - Select the Aperture Size. -**/ - UINT8 PcdApertureSize; -/** Offset 0x003E - GTT Size - Select the GTT Size. -**/ - UINT8 PcdGttSize; -/** Offset 0x003F - Enable Legacy E/F segments decoding to ROM - If disabled, E0000h-FFFFFh decoding will be routed to DRAM. -**/ - UINT8 PcdLegacySegDecode; -/** Offset 0x0040 - Enable DVFS - Enable/disable DVFS. -**/ - UINT8 PcdDvfsEnable; -/** Offset 0x0041 - MemoryType - To Configure Memory Type -**/ - UINT8 PcdMemoryTypeEnable; -/** Offset 0x0042 - CaMirrorEn - To Enable/Disable CaMirrorEn -**/ - UINT8 PcdCaMirrorEn; -/** Offset 0x0043 - DDR3 Auto Self Refresh - Enable/Disable DDR3 Auto Self Refresh -**/ - UINT8 PcdDdr3AutoSelfRefreshEnable; -/** Offset 0x0044 -**/ - UINT8 ReservedMemoryInitUpd[188]; -} MEMORY_INIT_UPD; - -typedef struct { -/** Offset 0x0100 -**/ - UINT64 Signature; -/** Offset 0x0108 -**/ - UINT8 Revision; -/** Offset 0x0109 -**/ - UINT8 UnusedUpdSpace3[7]; -/** Offset 0x0110 - SD Card Mode - SD Card Mode -**/ - UINT8 PcdSdcardMode; -/** Offset 0x0111 - Enable HSUART0 - Enable/disable HSUART0. -**/ - UINT8 PcdEnableHsuart0; -/** Offset 0x0112 - Enable HSUART1 - Enable/disable HSUART1. -**/ - UINT8 PcdEnableHsuart1; -/** Offset 0x0113 - Enable Azalia - Enable/disable Azalia controller. -**/ - UINT8 PcdEnableAzalia; -/** Offset 0x0114 -**/ - BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr; -/** Offset 0x0118 - Enable SATA - Enable/disable SATA controller. -**/ - UINT8 PcdEnableSata; -/** Offset 0x0119 - Enable XHCI - Enable/disable XHCI controller. -**/ - UINT8 PcdEnableXhci; -/** Offset 0x011A - Enable LPE - Choose LPE Mode. -**/ - UINT8 PcdEnableLpe; -/** Offset 0x011B - Enable DMA0 - Enable/disable DMA0. -**/ - UINT8 PcdEnableDma0; -/** Offset 0x011C - Enable DMA1 - Enable/disable DMA1. -**/ - UINT8 PcdEnableDma1; -/** Offset 0x011D - Enable I2C0 - Enable/disable I2C0. -**/ - UINT8 PcdEnableI2C0; -/** Offset 0x011E - Enable I2C1 - Enable/disable I2C1. -**/ - UINT8 PcdEnableI2C1; -/** Offset 0x011F - Enable I2C2 - Enable/disable I2C2. -**/ - UINT8 PcdEnableI2C2; -/** Offset 0x0120 - Enable I2C3 - Enable/disable I2C3. -**/ - UINT8 PcdEnableI2C3; -/** Offset 0x0121 - Enable I2C4 - Enable/disable I2C4. -**/ - UINT8 PcdEnableI2C4; -/** Offset 0x0122 - Enable I2C5 - Enable/disable I2C5. -**/ - UINT8 PcdEnableI2C5; -/** Offset 0x0123 - Enable I2C6 - Enable/disable I2C6. -**/ - UINT8 PcdEnableI2C6; -/** Offset 0x0124 -**/ - UINT32 GraphicsConfigPtr; -/** Offset 0x0128 -**/ - BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr; -/** Offset 0x012C -**/ - BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0130 -**/ - UINT8 PunitPwrConfigDisable; -/** Offset 0x0131 -**/ - UINT8 ChvSvidConfig; -/** Offset 0x0132 -**/ - UINT8 DptfDisable; -/** Offset 0x0133 - eMMC Mode - EMMC Mode -**/ - UINT8 PcdEmmcMode; -/** Offset 0x0134 -**/ - UINT8 PcdUsb3ClkSsc; -/** Offset 0x0135 -**/ - UINT8 PcdDispClkSsc; -/** Offset 0x0136 -**/ - UINT8 PcdSataClkSsc; -/** Offset 0x0137 -**/ - UINT8 Usb2Port0PerPortPeTxiSet; -/** Offset 0x0138 -**/ - UINT8 Usb2Port0PerPortTxiSet; -/** Offset 0x0139 -**/ - UINT8 Usb2Port0IUsbTxEmphasisEn; -/** Offset 0x013A -**/ - UINT8 Usb2Port0PerPortTxPeHalf; -/** Offset 0x013B -**/ - UINT8 Usb2Port1PerPortPeTxiSet; -/** Offset 0x013C -**/ - UINT8 Usb2Port1PerPortTxiSet; -/** Offset 0x013D -**/ - UINT8 Usb2Port1IUsbTxEmphasisEn; -/** Offset 0x013E -**/ - UINT8 Usb2Port1PerPortTxPeHalf; -/** Offset 0x013F -**/ - UINT8 Usb2Port2PerPortPeTxiSet; -/** Offset 0x0140 -**/ - UINT8 Usb2Port2PerPortTxiSet; -/** Offset 0x0141 -**/ - UINT8 Usb2Port2IUsbTxEmphasisEn; -/** Offset 0x0142 -**/ - UINT8 Usb2Port2PerPortTxPeHalf; -/** Offset 0x0143 -**/ - UINT8 Usb2Port3PerPortPeTxiSet; -/** Offset 0x0144 -**/ - UINT8 Usb2Port3PerPortTxiSet; -/** Offset 0x0145 -**/ - UINT8 Usb2Port3IUsbTxEmphasisEn; -/** Offset 0x0146 -**/ - UINT8 Usb2Port3PerPortTxPeHalf; -/** Offset 0x0147 -**/ - UINT8 Usb2Port4PerPortPeTxiSet; -/** Offset 0x0148 -**/ - UINT8 Usb2Port4PerPortTxiSet; -/** Offset 0x0149 -**/ - UINT8 Usb2Port4IUsbTxEmphasisEn; -/** Offset 0x014A -**/ - UINT8 Usb2Port4PerPortTxPeHalf; -/** Offset 0x014B -**/ - UINT8 Usb3Lane0Ow2tapgen2deemph3p5; -/** Offset 0x014C -**/ - UINT8 Usb3Lane1Ow2tapgen2deemph3p5; -/** Offset 0x014D -**/ - UINT8 Usb3Lane2Ow2tapgen2deemph3p5; -/** Offset 0x014E -**/ - UINT8 Usb3Lane3Ow2tapgen2deemph3p5; -/** Offset 0x014F - SATA Interface Speed - Select SATA controller Interface Speed. -**/ - UINT8 PcdSataInterfaceSpeed; -/** Offset 0x0150 -**/ - UINT8 PcdPchUsbSsicPort; -/** Offset 0x0151 -**/ - UINT8 PcdPchUsbHsicPort; -/** Offset 0x0152 -**/ - UINT8 PcdPcieRootPortSpeed; -/** Offset 0x0153 -**/ - UINT8 PcdPchSsicEnable; -/** Offset 0x0154 -**/ - UINT32 PcdLogoPtr; -/** Offset 0x0158 -**/ - UINT32 PcdLogoSize; -/** Offset 0x015C -**/ - UINT8 PcdRtcLock; -/** Offset 0x015D - PMIC I2c Bus Number - I2c Bus Number to communicate with PMIC -**/ - UINT8 PMIC_I2CBus; -/** Offset 0x015E - Enable ISP - Enable/disable ISP. -**/ - UINT8 ISPEnable; -/** Offset 0x015F - Select ISP Device Number - Select ISP PCI Device Configuration -**/ - UINT8 ISPPciDevConfig; -/** Offset 0x0160 - Processor Turbo Mode - Enable/disable Processor Turbo Mode. -**/ - UINT8 PcdTurboMode; -/** Offset 0x0161 - Pnp Setting Type - Select Pnp type -**/ - UINT8 PcdPnpSettings; -/** Offset 0x0162 - SdDetectChk - Check for Sd card detect -**/ - UINT8 PcdSdDetectChk; -/** Offset 0x0163 -**/ - UINT8 I2C0Frequency; -/** Offset 0x0164 -**/ - UINT8 I2C1Frequency; -/** Offset 0x0165 -**/ - UINT8 I2C2Frequency; -/** Offset 0x0166 -**/ - UINT8 I2C3Frequency; -/** Offset 0x0167 -**/ - UINT8 I2C4Frequency; -/** Offset 0x0168 -**/ - UINT8 I2C5Frequency; -/** Offset 0x0169 -**/ - UINT8 I2C6Frequency; -/** Offset 0x016A -**/ - UINT16 APTaskTimeoutCnt; -/** Offset 0x016C -**/ - UINT8 ReservedSiliconInitUpd[409]; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -typedef struct _UPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 Signature; -/** Offset 0x0008 -**/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 UnusedUpdSpace0[7]; -/** Offset 0x0010 -**/ - UINT32 MemoryInitUpdOffset; -/** Offset 0x0014 -**/ - UINT32 SiliconInitUpdOffset; -/** Offset 0x0018 -**/ - UINT64 UnusedUpdSpace1; -/** Offset 0x0020 -**/ - MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0100 -**/ - SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0305 -**/ - UINT16 PcdRegionTerminator; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ -#define FSP_IMAGE_REV 0x01010800 - -typedef struct _VPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - UINT32 PcdImageRevision; -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; -} VPD_DATA_REGION; - -#pragma pack() - -#endif diff --git a/BraswellFspBinPkg/Include/SecureBootEnabled/FspUpdVpd.h b/BraswellFspBinPkg/Include/SecureBootEnabled/FspUpdVpd.h deleted file mode 100644 index 860ba16..0000000 --- a/BraswellFspBinPkg/Include/SecureBootEnabled/FspUpdVpd.h +++ /dev/null @@ -1,553 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 - -typedef struct { - UINT32 VendorDeviceId; - UINT16 SubSystemId; - UINT8 RevisionId; /// 0xFF applies to all steppings - UINT8 FrontPanelSupport; - UINT16 NumberOfRearJacks; - UINT16 NumberOfFrontJacks; -} BL_PCH_AZALIA_VERB_TABLE_HEADER; - -typedef struct { - BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; - UINT32 *VerbTableData; -} BL_PCH_AZALIA_VERB_TABLE; - -typedef struct { - UINT8 Pme : 1; /// 0: Disable; 1: Enable - UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported - UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached - UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable - UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable - UINT8 Rsvdbits : 3; - UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform - BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) - UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds -} BL_PCH_AZALIA_CONFIG; - -typedef struct { - UINT32 Confg; - UINT32 ConfgChanges; - UINT32 Misc; - UINT32 MmioAddr; - CHAR16 *Name; -} BL_GPIO_FAMILY_INIT; - -typedef struct { - UINT32 Confg0; - UINT32 Confg0Changes; - UINT32 Confg1; - UINT32 Confg1Changes; - UINT32 Community; - UINT32 MmioAddr; - CHAR16 *Name; - UINT32 Misc; -} BL_GPIO_PAD_INIT; - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -typedef struct { -/** Offset 0x0020 -**/ - UINT64 Signature; -/** Offset 0x0028 -**/ - UINT8 Revision; -/** Offset 0x0029 -**/ - UINT8 UnusedUpdSpace2[7]; -/** Offset 0x0030 - Tseg Size - Size of SMRAM memory reserved. -**/ - UINT16 PcdMrcInitTsegSize; -/** Offset 0x0032 - MMIO Size - Size of memory address space reserved for MMIO (Memory Mapped I/O). -**/ - UINT16 PcdMrcInitMmioSize; -/** Offset 0x0034 - DIMM 0 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr1; -/** Offset 0x0035 - DIMM 1 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr2; -/** Offset 0x0036 -**/ - UINT8 PcdMemChannel0Config; -/** Offset 0x0037 -**/ - UINT8 PcdMemChannel1Config; -/** Offset 0x0038 -**/ - UINT32 PcdMemorySpdPtr; -/** Offset 0x003C - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics -**/ - UINT8 PcdIgdDvmt50PreAlloc; -/** Offset 0x003D - Aperture Size - Select the Aperture Size. -**/ - UINT8 PcdApertureSize; -/** Offset 0x003E - GTT Size - Select the GTT Size. -**/ - UINT8 PcdGttSize; -/** Offset 0x003F - Enable Legacy E/F segments decoding to ROM - If disabled, E0000h-FFFFFh decoding will be routed to DRAM. -**/ - UINT8 PcdLegacySegDecode; -/** Offset 0x0040 - Enable DVFS - Enable/disable DVFS. -**/ - UINT8 PcdDvfsEnable; -/** Offset 0x0041 - MemoryType - To Configure Memory Type -**/ - UINT8 PcdMemoryTypeEnable; -/** Offset 0x0042 - CaMirrorEn - To Enable/Disable CaMirrorEn -**/ - UINT8 PcdCaMirrorEn; -/** Offset 0x0043 - DDR3 Auto Self Refresh - Enable/Disable DDR3 Auto Self Refresh -**/ - UINT8 PcdDdr3AutoSelfRefreshEnable; -/** Offset 0x0044 -**/ - UINT8 ReservedMemoryInitUpd[188]; -} MEMORY_INIT_UPD; - -typedef struct { -/** Offset 0x0100 -**/ - UINT64 Signature; -/** Offset 0x0108 -**/ - UINT8 Revision; -/** Offset 0x0109 -**/ - UINT8 UnusedUpdSpace3[7]; -/** Offset 0x0110 - SD Card Mode - SD Card Mode -**/ - UINT8 PcdSdcardMode; -/** Offset 0x0111 - Enable HSUART0 - Enable/disable HSUART0. -**/ - UINT8 PcdEnableHsuart0; -/** Offset 0x0112 - Enable HSUART1 - Enable/disable HSUART1. -**/ - UINT8 PcdEnableHsuart1; -/** Offset 0x0113 - Enable Azalia - Enable/disable Azalia controller. -**/ - UINT8 PcdEnableAzalia; -/** Offset 0x0114 -**/ - BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr; -/** Offset 0x0118 - Enable SATA - Enable/disable SATA controller. -**/ - UINT8 PcdEnableSata; -/** Offset 0x0119 - Enable XHCI - Enable/disable XHCI controller. -**/ - UINT8 PcdEnableXhci; -/** Offset 0x011A - Enable LPE - Choose LPE Mode. -**/ - UINT8 PcdEnableLpe; -/** Offset 0x011B - Enable DMA0 - Enable/disable DMA0. -**/ - UINT8 PcdEnableDma0; -/** Offset 0x011C - Enable DMA1 - Enable/disable DMA1. -**/ - UINT8 PcdEnableDma1; -/** Offset 0x011D - Enable I2C0 - Enable/disable I2C0. -**/ - UINT8 PcdEnableI2C0; -/** Offset 0x011E - Enable I2C1 - Enable/disable I2C1. -**/ - UINT8 PcdEnableI2C1; -/** Offset 0x011F - Enable I2C2 - Enable/disable I2C2. -**/ - UINT8 PcdEnableI2C2; -/** Offset 0x0120 - Enable I2C3 - Enable/disable I2C3. -**/ - UINT8 PcdEnableI2C3; -/** Offset 0x0121 - Enable I2C4 - Enable/disable I2C4. -**/ - UINT8 PcdEnableI2C4; -/** Offset 0x0122 - Enable I2C5 - Enable/disable I2C5. -**/ - UINT8 PcdEnableI2C5; -/** Offset 0x0123 - Enable I2C6 - Enable/disable I2C6. -**/ - UINT8 PcdEnableI2C6; -/** Offset 0x0124 -**/ - UINT32 GraphicsConfigPtr; -/** Offset 0x0128 -**/ - BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr; -/** Offset 0x012C -**/ - BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0130 -**/ - UINT8 PunitPwrConfigDisable; -/** Offset 0x0131 -**/ - UINT8 ChvSvidConfig; -/** Offset 0x0132 -**/ - UINT8 DptfDisable; -/** Offset 0x0133 - eMMC Mode - EMMC Mode -**/ - UINT8 PcdEmmcMode; -/** Offset 0x0134 -**/ - UINT8 PcdUsb3ClkSsc; -/** Offset 0x0135 -**/ - UINT8 PcdDispClkSsc; -/** Offset 0x0136 -**/ - UINT8 PcdSataClkSsc; -/** Offset 0x0137 -**/ - UINT8 Usb2Port0PerPortPeTxiSet; -/** Offset 0x0138 -**/ - UINT8 Usb2Port0PerPortTxiSet; -/** Offset 0x0139 -**/ - UINT8 Usb2Port0IUsbTxEmphasisEn; -/** Offset 0x013A -**/ - UINT8 Usb2Port0PerPortTxPeHalf; -/** Offset 0x013B -**/ - UINT8 Usb2Port1PerPortPeTxiSet; -/** Offset 0x013C -**/ - UINT8 Usb2Port1PerPortTxiSet; -/** Offset 0x013D -**/ - UINT8 Usb2Port1IUsbTxEmphasisEn; -/** Offset 0x013E -**/ - UINT8 Usb2Port1PerPortTxPeHalf; -/** Offset 0x013F -**/ - UINT8 Usb2Port2PerPortPeTxiSet; -/** Offset 0x0140 -**/ - UINT8 Usb2Port2PerPortTxiSet; -/** Offset 0x0141 -**/ - UINT8 Usb2Port2IUsbTxEmphasisEn; -/** Offset 0x0142 -**/ - UINT8 Usb2Port2PerPortTxPeHalf; -/** Offset 0x0143 -**/ - UINT8 Usb2Port3PerPortPeTxiSet; -/** Offset 0x0144 -**/ - UINT8 Usb2Port3PerPortTxiSet; -/** Offset 0x0145 -**/ - UINT8 Usb2Port3IUsbTxEmphasisEn; -/** Offset 0x0146 -**/ - UINT8 Usb2Port3PerPortTxPeHalf; -/** Offset 0x0147 -**/ - UINT8 Usb2Port4PerPortPeTxiSet; -/** Offset 0x0148 -**/ - UINT8 Usb2Port4PerPortTxiSet; -/** Offset 0x0149 -**/ - UINT8 Usb2Port4IUsbTxEmphasisEn; -/** Offset 0x014A -**/ - UINT8 Usb2Port4PerPortTxPeHalf; -/** Offset 0x014B -**/ - UINT8 Usb3Lane0Ow2tapgen2deemph3p5; -/** Offset 0x014C -**/ - UINT8 Usb3Lane1Ow2tapgen2deemph3p5; -/** Offset 0x014D -**/ - UINT8 Usb3Lane2Ow2tapgen2deemph3p5; -/** Offset 0x014E -**/ - UINT8 Usb3Lane3Ow2tapgen2deemph3p5; -/** Offset 0x014F - SATA Interface Speed - Select SATA controller Interface Speed. -**/ - UINT8 PcdSataInterfaceSpeed; -/** Offset 0x0150 -**/ - UINT8 PcdPchUsbSsicPort; -/** Offset 0x0151 -**/ - UINT8 PcdPchUsbHsicPort; -/** Offset 0x0152 -**/ - UINT8 PcdPcieRootPortSpeed; -/** Offset 0x0153 -**/ - UINT8 PcdPchSsicEnable; -/** Offset 0x0154 -**/ - UINT32 PcdLogoPtr; -/** Offset 0x0158 -**/ - UINT32 PcdLogoSize; -/** Offset 0x015C -**/ - UINT8 PcdRtcLock; -/** Offset 0x015D - PMIC I2c Bus Number - I2c Bus Number to communicate with PMIC -**/ - UINT8 PMIC_I2CBus; -/** Offset 0x015E - Enable ISP - Enable/disable ISP. -**/ - UINT8 ISPEnable; -/** Offset 0x015F - Select ISP Device Number - Select ISP PCI Device Configuration -**/ - UINT8 ISPPciDevConfig; -/** Offset 0x0160 - Processor Turbo Mode - Enable/disable Processor Turbo Mode. -**/ - UINT8 PcdTurboMode; -/** Offset 0x0161 - Pnp Setting Type - Select Pnp type -**/ - UINT8 PcdPnpSettings; -/** Offset 0x0162 - SdDetectChk - Check for Sd card detect -**/ - UINT8 PcdSdDetectChk; -/** Offset 0x0163 -**/ - UINT8 I2C0Frequency; -/** Offset 0x0164 -**/ - UINT8 I2C1Frequency; -/** Offset 0x0165 -**/ - UINT8 I2C2Frequency; -/** Offset 0x0166 -**/ - UINT8 I2C3Frequency; -/** Offset 0x0167 -**/ - UINT8 I2C4Frequency; -/** Offset 0x0168 -**/ - UINT8 I2C5Frequency; -/** Offset 0x0169 -**/ - UINT8 I2C6Frequency; -/** Offset 0x016A -**/ - UINT16 APTaskTimeoutCnt; -/** Offset 0x016C -**/ - UINT8 ReservedSiliconInitUpd[409]; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -typedef struct _UPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 Signature; -/** Offset 0x0008 -**/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 UnusedUpdSpace0[7]; -/** Offset 0x0010 -**/ - UINT32 MemoryInitUpdOffset; -/** Offset 0x0014 -**/ - UINT32 SiliconInitUpdOffset; -/** Offset 0x0018 -**/ - UINT64 UnusedUpdSpace1; -/** Offset 0x0020 -**/ - MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0100 -**/ - SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0305 -**/ - UINT16 PcdRegionTerminator; -/** Offset 0x0307 -**/ - UINT8 UnusedUpdSpace4[2116]; -/** Offset 0x0B4B -**/ - UINT8 PcdPaddingSpace; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x5053464253575342 /* 'BSWSBFSP' */ -#define FSP_IMAGE_REV 0x01010800 - -typedef struct _VPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - UINT32 PcdImageRevision; -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[20]; -/** Offset 0x0024 - Enable Secure Boot - Enable/disable secure boot. Auto by default. -**/ - UINT8 PcdEnableSecureBoot; -} VPD_DATA_REGION; - -#pragma pack() - -#endif diff --git a/BraswellFspBinPkg/SampleCode/FspUpdVpd.h b/BraswellFspBinPkg/SampleCode/FspUpdVpd.h deleted file mode 100644 index 9ee0230..0000000 --- a/BraswellFspBinPkg/SampleCode/FspUpdVpd.h +++ /dev/null @@ -1,539 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 - -typedef struct { - UINT32 VendorDeviceId; - UINT16 SubSystemId; - UINT8 RevisionId; /// 0xFF applies to all steppings - UINT8 FrontPanelSupport; - UINT16 NumberOfRearJacks; - UINT16 NumberOfFrontJacks; -} BL_PCH_AZALIA_VERB_TABLE_HEADER; - -typedef struct { - BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; - UINT32 *VerbTableData; -} BL_PCH_AZALIA_VERB_TABLE; - -typedef struct { - UINT8 Pme : 1; /// 0: Disable; 1: Enable - UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported - UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached - UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable - UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable - UINT8 Rsvdbits : 3; - UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform - BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) - UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds -} BL_PCH_AZALIA_CONFIG; - -typedef struct { - UINT32 Confg; - UINT32 ConfgChanges; - UINT32 Misc; - UINT32 MmioAddr; - CHAR16 *Name; -} BL_GPIO_FAMILY_INIT; - -typedef struct { - UINT32 Confg0; - UINT32 Confg0Changes; - UINT32 Confg1; - UINT32 Confg1Changes; - UINT32 Community; - UINT32 MmioAddr; - CHAR16 *Name; - UINT32 Misc; -} BL_GPIO_PAD_INIT; - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -typedef struct { -/** Offset 0x0020 -**/ - UINT64 Signature; -/** Offset 0x0028 -**/ - UINT8 Revision; -/** Offset 0x0029 -**/ - UINT8 UnusedUpdSpace2[7]; -/** Offset 0x0030 - Tseg Size - Size of SMRAM memory reserved. -**/ - UINT16 PcdMrcInitTsegSize; -/** Offset 0x0032 - MMIO Size - Size of memory address space reserved for MMIO (Memory Mapped I/O). -**/ - UINT16 PcdMrcInitMmioSize; -/** Offset 0x0034 - DIMM 0 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr1; -/** Offset 0x0035 - DIMM 1 SPD SMBus Address - SPD Address of DIMM. -**/ - UINT8 PcdMrcInitSpdAddr2; -/** Offset 0x0036 -**/ - UINT8 PcdMemChannel0Config; -/** Offset 0x0037 -**/ - UINT8 PcdMemChannel1Config; -/** Offset 0x0038 -**/ - UINT32 PcdMemorySpdPtr; -/** Offset 0x003C - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics -**/ - UINT8 PcdIgdDvmt50PreAlloc; -/** Offset 0x003D - Aperture Size - Select the Aperture Size. -**/ - UINT8 PcdApertureSize; -/** Offset 0x003E - GTT Size - Select the GTT Size. -**/ - UINT8 PcdGttSize; -/** Offset 0x003F - Enable Legacy E/F segments decoding to ROM - If disabled, E0000h-FFFFFh decoding will be routed to DRAM. -**/ - UINT8 PcdLegacySegDecode; -/** Offset 0x0040 - Enable DVFS - Enable/disable DVFS. -**/ - UINT8 PcdDvfsEnable; -/** Offset 0x0041 - MemoryType - To Configure Memory Type -**/ - UINT8 PcdMemoryTypeEnable; -/** Offset 0x0042 - CaMirrorEn - To Enable/Disable CaMirrorEn -**/ - UINT8 PcdCaMirrorEn; -/** Offset 0x0043 - DDR3 Auto Self Refresh - Enable/Disable DDR3 Auto Self Refresh -**/ - UINT8 PcdDdr3AutoSelfRefreshEnable; -/** Offset 0x0044 -**/ - UINT8 ReservedMemoryInitUpd[188]; -} MEMORY_INIT_UPD; - -typedef struct { -/** Offset 0x0100 -**/ - UINT64 Signature; -/** Offset 0x0108 -**/ - UINT8 Revision; -/** Offset 0x0109 -**/ - UINT8 UnusedUpdSpace3[7]; -/** Offset 0x0110 - SD Card Mode - SD Card Mode -**/ - UINT8 PcdSdcardMode; -/** Offset 0x0111 - Enable HSUART0 - Enable/disable HSUART0. -**/ - UINT8 PcdEnableHsuart0; -/** Offset 0x0112 - Enable HSUART1 - Enable/disable HSUART1. -**/ - UINT8 PcdEnableHsuart1; -/** Offset 0x0113 - Enable Azalia - Enable/disable Azalia controller. -**/ - UINT8 PcdEnableAzalia; -/** Offset 0x0114 -**/ - BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr; -/** Offset 0x0118 - Enable SATA - Enable/disable SATA controller. -**/ - UINT8 PcdEnableSata; -/** Offset 0x0119 - Enable XHCI - Enable/disable XHCI controller. -**/ - UINT8 PcdEnableXhci; -/** Offset 0x011A - Enable LPE - Choose LPE Mode. -**/ - UINT8 PcdEnableLpe; -/** Offset 0x011B - Enable DMA0 - Enable/disable DMA0. -**/ - UINT8 PcdEnableDma0; -/** Offset 0x011C - Enable DMA1 - Enable/disable DMA1. -**/ - UINT8 PcdEnableDma1; -/** Offset 0x011D - Enable I2C0 - Enable/disable I2C0. -**/ - UINT8 PcdEnableI2C0; -/** Offset 0x011E - Enable I2C1 - Enable/disable I2C1. -**/ - UINT8 PcdEnableI2C1; -/** Offset 0x011F - Enable I2C2 - Enable/disable I2C2. -**/ - UINT8 PcdEnableI2C2; -/** Offset 0x0120 - Enable I2C3 - Enable/disable I2C3. -**/ - UINT8 PcdEnableI2C3; -/** Offset 0x0121 - Enable I2C4 - Enable/disable I2C4. -**/ - UINT8 PcdEnableI2C4; -/** Offset 0x0122 - Enable I2C5 - Enable/disable I2C5. -**/ - UINT8 PcdEnableI2C5; -/** Offset 0x0123 - Enable I2C6 - Enable/disable I2C6. -**/ - UINT8 PcdEnableI2C6; -/** Offset 0x0124 -**/ - UINT32 GraphicsConfigPtr; -/** Offset 0x0128 -**/ - BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr; -/** Offset 0x012C -**/ - BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0130 -**/ - UINT8 PunitPwrConfigDisable; -/** Offset 0x0131 -**/ - UINT8 ChvSvidConfig; -/** Offset 0x0132 -**/ - UINT8 DptfDisable; -/** Offset 0x0133 - eMMC Mode - EMMC Mode -**/ - UINT8 PcdEmmcMode; -/** Offset 0x0134 -**/ - UINT8 PcdUsb3ClkSsc; -/** Offset 0x0135 -**/ - UINT8 PcdDispClkSsc; -/** Offset 0x0136 -**/ - UINT8 PcdSataClkSsc; -/** Offset 0x0137 -**/ - UINT8 Usb2Port0PerPortPeTxiSet; -/** Offset 0x0138 -**/ - UINT8 Usb2Port0PerPortTxiSet; -/** Offset 0x0139 -**/ - UINT8 Usb2Port0IUsbTxEmphasisEn; -/** Offset 0x013A -**/ - UINT8 Usb2Port0PerPortTxPeHalf; -/** Offset 0x013B -**/ - UINT8 Usb2Port1PerPortPeTxiSet; -/** Offset 0x013C -**/ - UINT8 Usb2Port1PerPortTxiSet; -/** Offset 0x013D -**/ - UINT8 Usb2Port1IUsbTxEmphasisEn; -/** Offset 0x013E -**/ - UINT8 Usb2Port1PerPortTxPeHalf; -/** Offset 0x013F -**/ - UINT8 Usb2Port2PerPortPeTxiSet; -/** Offset 0x0140 -**/ - UINT8 Usb2Port2PerPortTxiSet; -/** Offset 0x0141 -**/ - UINT8 Usb2Port2IUsbTxEmphasisEn; -/** Offset 0x0142 -**/ - UINT8 Usb2Port2PerPortTxPeHalf; -/** Offset 0x0143 -**/ - UINT8 Usb2Port3PerPortPeTxiSet; -/** Offset 0x0144 -**/ - UINT8 Usb2Port3PerPortTxiSet; -/** Offset 0x0145 -**/ - UINT8 Usb2Port3IUsbTxEmphasisEn; -/** Offset 0x0146 -**/ - UINT8 Usb2Port3PerPortTxPeHalf; -/** Offset 0x0147 -**/ - UINT8 Usb2Port4PerPortPeTxiSet; -/** Offset 0x0148 -**/ - UINT8 Usb2Port4PerPortTxiSet; -/** Offset 0x0149 -**/ - UINT8 Usb2Port4IUsbTxEmphasisEn; -/** Offset 0x014A -**/ - UINT8 Usb2Port4PerPortTxPeHalf; -/** Offset 0x014B -**/ - UINT8 Usb3Lane0Ow2tapgen2deemph3p5; -/** Offset 0x014C -**/ - UINT8 Usb3Lane1Ow2tapgen2deemph3p5; -/** Offset 0x014D -**/ - UINT8 Usb3Lane2Ow2tapgen2deemph3p5; -/** Offset 0x014E -**/ - UINT8 Usb3Lane3Ow2tapgen2deemph3p5; -/** Offset 0x014F - SATA Interface Speed - Select SATA controller Interface Speed. -**/ - UINT8 PcdSataInterfaceSpeed; -/** Offset 0x0150 -**/ - UINT8 PcdPchUsbSsicPort; -/** Offset 0x0151 -**/ - UINT8 PcdPchUsbHsicPort; -/** Offset 0x0152 -**/ - UINT8 PcdPcieRootPortSpeed; -/** Offset 0x0153 -**/ - UINT8 PcdPchSsicEnable; -/** Offset 0x0154 -**/ - UINT32 PcdLogoPtr; -/** Offset 0x0158 -**/ - UINT32 PcdLogoSize; -/** Offset 0x015C -**/ - UINT8 PcdRtcLock; -/** Offset 0x015D - PMIC I2c Bus Number - I2c Bus Number to communicate with PMIC -**/ - UINT8 PMIC_I2CBus; -/** Offset 0x015E - Enable ISP - Enable/disable ISP. -**/ - UINT8 ISPEnable; -/** Offset 0x015F - Select ISP Device Number - Select ISP PCI Device Configuration -**/ - UINT8 ISPPciDevConfig; -/** Offset 0x0160 - Processor Turbo Mode - Enable/disable Processor Turbo Mode. -**/ - UINT8 PcdTurboMode; -/** Offset 0x0161 - Pnp Setting Type - Select Pnp type -**/ - UINT8 PcdPnpSettings; -/** Offset 0x0162 - SdDetectChk - Check for Sd card detect -**/ - UINT8 PcdSdDetectChk; -/** Offset 0x0163 -**/ - UINT8 I2C0Frequency; -/** Offset 0x0164 -**/ - UINT8 I2C1Frequency; -/** Offset 0x0165 -**/ - UINT8 I2C2Frequency; -/** Offset 0x0166 -**/ - UINT8 I2C3Frequency; -/** Offset 0x0167 -**/ - UINT8 I2C4Frequency; -/** Offset 0x0168 -**/ - UINT8 I2C5Frequency; -/** Offset 0x0169 -**/ - UINT8 I2C6Frequency; -/** Offset 0x016A -**/ - UINT16 APTaskTimeoutCnt; -/** Offset 0x016C -**/ - UINT8 ReservedSiliconInitUpd[409]; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -typedef struct _UPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 Signature; -/** Offset 0x0008 -**/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 UnusedUpdSpace0[7]; -/** Offset 0x0010 -**/ - UINT32 MemoryInitUpdOffset; -/** Offset 0x0014 -**/ - UINT32 SiliconInitUpdOffset; -/** Offset 0x0018 -**/ - UINT64 UnusedUpdSpace1; -/** Offset 0x0020 -**/ - MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0100 -**/ - SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0305 -**/ - UINT16 PcdRegionTerminator; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ -#define FSP_IMAGE_REV 0x01010800 - -typedef struct _VPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - UINT32 PcdImageRevision; -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; -} VPD_DATA_REGION; - -#pragma pack() - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp.h b/BraswellFspBinPkg/SampleCode/fsp.h deleted file mode 100644 index 16d443c..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - -Copyright (C) 2015, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/** \file fsp.h - * - * - */ - - -#ifndef __FSP_H__ - -#include "fsp_types.h" -#include "fsp_fv.h" -#include "fsp_ffs.h" -#include "fsp_api.h" -#include "fsp_hob.h" -#include "fsp_platform.h" -#include "fsp_infoheader.h" -#include "fsp_bootmode.h" -#include "FspUpdVpd.h" -#include "fsp_support.h" - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_api.h b/BraswellFspBinPkg/SampleCode/fsp_api.h deleted file mode 100644 index fffc0ad..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_api.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_API_H__ -#define __FSP_API_H__ - -/// -/// FSP Init continuation function prototype. -/// Control will be returned to this callback function after FspInit API call. -/// -typedef VOID (FSPAPI *CONTINUATION_PROC) (EFI_STATUS Status, VOID *HobListPtr); - -#pragma pack(1) - -typedef struct { - /// - /// Non-volatile storage buffer pointer. - /// - VOID *NvsBufferPtr; - /// - /// Runtime buffer pointer - /// - VOID *RtBufferPtr; - /// - /// Continuation function address - /// - CONTINUATION_PROC ContinuationFunc; -} FSP_INIT_PARAMS; - -typedef struct { - /// - /// Stack top pointer used by the bootloader. - /// The new stack frame will be set up at this location after FspInit API call. - /// - UINT32 *StackTop; - /// - /// Current system boot mode. - /// - UINT32 BootMode; - /// - /// User platform configuraiton data region pointer. - /// - VOID *UpdDataRgnPtr; - /// - /// Reserved - /// - UINT32 Reserved[7]; -} FSP_INIT_RT_COMMON_BUFFER; - - -typedef enum { - /// - /// Notification code for post PCI enuermation - /// - EnumInitPhaseAfterPciEnumeration = 0x20, - /// - /// Notification code before transfering control to the payload - /// - EnumInitPhaseReadyToBoot = 0x40 -} FSP_INIT_PHASE; - -typedef struct { - /// - /// Notification phase used for NotifyPhase API - /// - FSP_INIT_PHASE Phase; -} NOTIFY_PHASE_PARAMS; - -#pragma pack() - -/// -/// FspInit API function prototype -/// -typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr); - -/// -/// NotifyPhase API function prototype -/// -typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr); - -#endif - diff --git a/BraswellFspBinPkg/SampleCode/fsp_bootmode.h b/BraswellFspBinPkg/SampleCode/fsp_bootmode.h deleted file mode 100644 index f3b917d..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_bootmode.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_BOOT_MODE_H__ -#define __FSP_BOOT_MODE_H__ - -/// -/// EFI boot mode -/// -typedef UINT32 EFI_BOOT_MODE; - -// -// 0x21 - 0xf..f are reserved. -// -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_ON_S3_RESUME 0x11 - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_ffs.h b/BraswellFspBinPkg/SampleCode/fsp_ffs.h deleted file mode 100644 index 4771553..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_ffs.h +++ /dev/null @@ -1,507 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef __FSP_FFS_H__ -#define __FSP_FFS_H__ - -#pragma pack(1) -/// -/// Used to verify the integrity of the file. -/// -typedef union { - struct { - /// - /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file - /// header. The State and IntegrityCheck.Checksum.File fields are assumed - /// to be zero and the checksum is calculated such that the entire header sums to zero. - /// - UINT8 Header; - /// - /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes - /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit - /// checksum of the file data. - /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, - /// the IntegrityCheck.Checksum.File field must be initialized with a value of - /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the - /// EFI_FILE_DATA_VALID bit is set in the State field. - /// - UINT8 File; - } Checksum; - /// - /// This is the full 16 bits of the IntegrityCheck field. - /// - UINT16 Checksum16; -} EFI_FFS_INTEGRITY_CHECK; - -/// -/// FFS_FIXED_CHECKSUM is the checksum value used when the -/// FFS_ATTRIB_CHECKSUM attribute bit is clear. -/// -#define FFS_FIXED_CHECKSUM 0xAA - -typedef UINT8 EFI_FV_FILETYPE; -typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; -typedef UINT8 EFI_FFS_FILE_STATE; - -/// -/// File Types Definitions -/// -#define EFI_FV_FILETYPE_ALL 0x00 -#define EFI_FV_FILETYPE_RAW 0x01 -#define EFI_FV_FILETYPE_FREEFORM 0x02 -#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 -#define EFI_FV_FILETYPE_PEI_CORE 0x04 -#define EFI_FV_FILETYPE_DXE_CORE 0x05 -#define EFI_FV_FILETYPE_PEIM 0x06 -#define EFI_FV_FILETYPE_DRIVER 0x07 -#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 -#define EFI_FV_FILETYPE_APPLICATION 0x09 -#define EFI_FV_FILETYPE_SMM 0x0A -#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B -#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C -#define EFI_FV_FILETYPE_SMM_CORE 0x0D -#define EFI_FV_FILETYPE_OEM_MIN 0xc0 -#define EFI_FV_FILETYPE_OEM_MAX 0xdf -#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 -#define EFI_FV_FILETYPE_DEBUG_MAX 0xef -#define EFI_FV_FILETYPE_FFS_MIN 0xf0 -#define EFI_FV_FILETYPE_FFS_MAX 0xff -#define EFI_FV_FILETYPE_FFS_PAD 0xf0 -/// -/// FFS File Attributes. -/// -#define FFS_ATTRIB_LARGE_FILE 0x01 -#define FFS_ATTRIB_FIXED 0x04 -#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 -#define FFS_ATTRIB_CHECKSUM 0x40 - -/// -/// FFS File State Bits. -/// -#define EFI_FILE_HEADER_CONSTRUCTION 0x01 -#define EFI_FILE_HEADER_VALID 0x02 -#define EFI_FILE_DATA_VALID 0x04 -#define EFI_FILE_MARKED_FOR_UPDATE 0x08 -#define EFI_FILE_DELETED 0x10 -#define EFI_FILE_HEADER_INVALID 0x20 - - -/// -/// Each file begins with the header that describe the -/// contents and state of the files. -/// -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. - /// - EFI_GUID Name; - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - /// - /// The length of the file in bytes, including the FFS header. - /// - UINT8 Size[3]; - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; -} EFI_FFS_FILE_HEADER; - -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. There may be only - /// one instance of a file with the file name GUID of Name in any given firmware - /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. - /// - EFI_GUID Name; - - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - - /// - /// The length of the file in bytes, including the FFS header. - /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a - /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). - /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is - /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. - /// - UINT8 Size[3]; - - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; - - /// - /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. - /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. - /// - UINT32 ExtendedSize; -} EFI_FFS_FILE_HEADER2; - -#define IS_FFS_FILE2(FfsFileHeaderPtr) \ - (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) - -#define FFS_FILE_SIZE(FfsFileHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff)) - -#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ - (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize) - -typedef UINT8 EFI_SECTION_TYPE; - -/// -/// Pseudo type. It is used as a wild card when retrieving sections. -/// The section type EFI_SECTION_ALL matches all section types. -/// -#define EFI_SECTION_ALL 0x00 - -/// -/// Encapsulation section Type values. -/// -#define EFI_SECTION_COMPRESSION 0x01 - -#define EFI_SECTION_GUID_DEFINED 0x02 - -#define EFI_SECTION_DISPOSABLE 0x03 - -/// -/// Leaf section Type values. -/// -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/// -/// Common section header. -/// -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - EFI_SECTION_TYPE Type; - /// - /// Declares the section type. - /// -} EFI_COMMON_SECTION_HEADER; - -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - - EFI_SECTION_TYPE Type; - - /// - /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If - /// Size is not equal to 0xFFFFFF, then this field does not exist. - /// - UINT32 ExtendedSize; -} EFI_COMMON_SECTION_HEADER2; - -/// -/// Leaf section type that contains an -/// IA-32 16-bit executable image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; - -/// -/// CompressionType of EFI_COMPRESSION_SECTION. -/// -#define EFI_NOT_COMPRESSED 0x00 -#define EFI_STANDARD_COMPRESSION 0x01 -/// -/// An encapsulation section type in which the -/// section data is compressed. -/// -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION; - -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION2; - -/// -/// An encapsulation section type in which the section data is disposable. -/// A disposable section is an encapsulation section in which the section data may be disposed of during -/// the process of creating or updating a firmware image without significant impact on the usefulness of -/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This -/// allows optional or descriptive data to be included with the firmware file which can be removed in -/// order to conserve space. The contents of this section are implementation specific, but might contain -/// debug data or detailed integration instructions. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; - -/// -/// The leaf section which could be used to determine the dispatch order of DXEs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; - -/// -/// The leaf section which contains a PI FV. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; - -/// -/// The leaf section which contains a single GUID. -/// -typedef struct { - /// - /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; - -/// -/// Attributes of EFI_GUID_DEFINED_SECTION. -/// -#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 -#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 -/// -/// The leaf section which is encapsulation defined by specific GUID. -/// -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION2; - -/// -/// The leaf section which contains PE32+ image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; - -/// -/// The leaf section used to determine the dispatch order of PEIMs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; - -/// -/// A leaf section type that contains a position-independent-code (PIC) image. -/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. -/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be -/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all -/// relocation information has been stripped from the image and the image can be moved and will -/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must -/// be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; - -/// -/// The leaf section which constains the position-independent-code image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; - -/// -/// The leaf section which contains an array of zero or more bytes. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; - -/// -/// The SMM dependency expression section is a leaf section that contains a dependency expression that -/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the -/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform -/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. -/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol -/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; - -/// -/// The leaf section which contains a unicode string that -/// is human readable file name. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - - /// - /// Array of unicode string. - /// - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION2; - -/// -/// The leaf section which contains a numeric build number and -/// an optional unicode string that represents the file revision. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - UINT16 BuildNumber; - - /// - /// Array of unicode string. - /// - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// A UINT16 that represents a particular build. Subsequent builds have monotonically - /// increasing build numbers relative to earlier builds. - /// - UINT16 BuildNumber; - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION2; - -#define IS_SECTION2(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff) - -#define SECTION_SIZE(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff)) - -#define SECTION2_SIZE(SectionHeaderPtr) \ - (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) - -#pragma pack() - -#endif - diff --git a/BraswellFspBinPkg/SampleCode/fsp_fv.h b/BraswellFspBinPkg/SampleCode/fsp_fv.h deleted file mode 100644 index dad6c90..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_fv.h +++ /dev/null @@ -1,247 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_FV___ -#define __FSP_FV___ - -/// -/// EFI_FV_FILE_ATTRIBUTES -/// -typedef UINT32 EFI_FV_FILE_ATTRIBUTES; - -// -// Value of EFI_FV_FILE_ATTRIBUTES. -// -#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F -#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100 -#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200 - -/// -/// type of EFI FVB attribute -/// -typedef UINT32 EFI_FVB_ATTRIBUTES_2; - -// -// Attributes bit definitions -// -#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB2_READ_STATUS 0x00000004 -#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB2_WRITE_STATUS 0x00000020 -#define EFI_FVB2_LOCK_CAP 0x00000040 -#define EFI_FVB2_LOCK_STATUS 0x00000080 -#define EFI_FVB2_STICKY_WRITE 0x00000200 -#define EFI_FVB2_MEMORY_MAPPED 0x00000400 -#define EFI_FVB2_ERASE_POLARITY 0x00000800 -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - - -typedef struct { - /// - /// The number of sequential blocks which are of the same size. - /// - UINT32 NumBlocks; - /// - /// The size of the blocks. - /// - UINT32 Length; -} EFI_FV_BLOCK_MAP_ENTRY; - -/// -/// Describes the features and layout of the firmware volume. -/// -typedef struct { - /// - /// The first 16 bytes are reserved to allow for the reset vector of - /// processors whose reset vector is at address 0. - /// - UINT8 ZeroVector[16]; - /// - /// Declares the file system with which the firmware volume is formatted. - /// - EFI_GUID FileSystemGuid; - /// - /// Length in bytes of the complete firmware volume, including the header. - /// - UINT64 FvLength; - /// - /// Set to EFI_FVH_SIGNATURE - /// - UINT32 Signature; - /// - /// Declares capabilities and power-on defaults for the firmware volume. - /// - EFI_FVB_ATTRIBUTES_2 Attributes; - /// - /// Length in bytes of the complete firmware volume header. - /// - UINT16 HeaderLength; - /// - /// A 16-bit checksum of the firmware volume header. A valid header sums to zero. - /// - UINT16 Checksum; - /// - /// Offset, relative to the start of the header, of the extended header - /// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header. - /// - UINT16 ExtHeaderOffset; - /// - /// This field must always be set to zero. - /// - UINT8 Reserved[1]; - /// - /// Set to 2. Future versions of this specification may define new header fields and will - /// increment the Revision field accordingly. - /// - UINT8 Revision; - /// - /// An array of run-length encoded FvBlockMapEntry structures. The array is - /// terminated with an entry of {0,0}. - /// - EFI_FV_BLOCK_MAP_ENTRY BlockMap[1]; -} EFI_FIRMWARE_VOLUME_HEADER; - -#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H') - -/// -/// Firmware Volume Header Revision definition -/// -#define EFI_FVH_REVISION 0x02 - -/// -/// Extension header pointed by ExtHeaderOffset of volume header. -/// -typedef struct { - /// - /// Firmware volume name. - /// - EFI_GUID FvName; - /// - /// Size of the rest of the extension header, including this structure. - /// - UINT32 ExtHeaderSize; -} EFI_FIRMWARE_VOLUME_EXT_HEADER; - -/// -/// Entry struture for describing FV extension header -/// -typedef struct { - /// - /// Size of this header extension. - /// - UINT16 ExtEntrySize; - /// - /// Type of the header. - /// - UINT16 ExtEntryType; -} EFI_FIRMWARE_VOLUME_EXT_ENTRY; - -#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 -/// -/// This extension header provides a mapping between a GUID and an OEM file type. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit - /// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types. - /// - UINT32 TypeMask; - /// - /// An array of GUIDs, each GUID representing an OEM file type. - /// - /// EFI_GUID Types[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE; - -#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002 - -/// -/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific -/// GUID FormatType type which includes a length and a successive series of data bytes. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// Vendor-specific GUID. - /// - EFI_GUID FormatType; - /// - /// An arry of bytes of length Length. - /// - /// UINT8 Data[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE; - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_hob.h b/BraswellFspBinPkg/SampleCode/fsp_hob.h deleted file mode 100644 index 9a7b9e0..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_hob.h +++ /dev/null @@ -1,427 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_HOB_H__ -#define __FSP_HOB_H__ - -// -// HobType of EFI_HOB_GENERIC_HEADER. -// -#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 -#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 -#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 -#define EFI_HOB_TYPE_UNUSED 0xFFFE -#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF - -/// -/// Describes the format and size of the data inside the HOB. -/// All HOBs must contain this generic HOB header. -/// -typedef struct { - /// - /// Identifies the HOB data structure type. - /// - UINT16 HobType; - /// - /// The length in bytes of the HOB. - /// - UINT16 HobLength; - /// - /// This field must always be set to zero. - /// - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -/// -/// Enumeration of memory types introduced in UEFI. -/// -typedef enum { - /// - /// Not used. - /// - EfiReservedMemoryType, - /// - /// The code portions of a loaded application. - /// (Note that UEFI OS loaders are UEFI applications.) - /// - EfiLoaderCode, - /// - /// The data portions of a loaded application and the default data allocation - /// type used by an application to allocate pool memory. - /// - EfiLoaderData, - /// - /// The code portions of a loaded Boot Services Driver. - /// - EfiBootServicesCode, - /// - /// The data portions of a loaded Boot Serves Driver, and the default data - /// allocation type used by a Boot Services Driver to allocate pool memory. - /// - EfiBootServicesData, - /// - /// The code portions of a loaded Runtime Services Driver. - /// - EfiRuntimeServicesCode, - /// - /// The data portions of a loaded Runtime Services Driver and the default - /// data allocation type used by a Runtime Services Driver to allocate pool memory. - /// - EfiRuntimeServicesData, - /// - /// Free (unallocated) memory. - /// - EfiConventionalMemory, - /// - /// Memory in which errors have been detected. - /// - EfiUnusableMemory, - /// - /// Memory that holds the ACPI tables. - /// - EfiACPIReclaimMemory, - /// - /// Address space reserved for use by the firmware. - /// - EfiACPIMemoryNVS, - /// - /// Used by system firmware to request that a memory-mapped IO region - /// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services. - /// - EfiMemoryMappedIO, - /// - /// System memory-mapped IO region that is used to translate memory - /// cycles to IO cycles by the processor. - /// - EfiMemoryMappedIOPortSpace, - /// - /// Address space reserved by the firmware for code that is part of the processor. - /// - EfiPalCode, - EfiMaxMemoryType -} EFI_MEMORY_TYPE; - -/// -/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the -/// various attributes of the logical memory allocation. The type field will be used for -/// subsequent inclusion in the UEFI memory map. -/// -typedef struct { - /// - /// A GUID that defines the memory allocation region's type and purpose, as well as - /// other fields within the memory allocation HOB. This GUID is used to define the - /// additional data within the HOB that may be present for the memory allocation HOB. - /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 - /// specification. - /// - EFI_GUID Name; - - /// - /// The base address of memory allocated by this HOB. Type - /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 - /// specification. - /// - EFI_PHYSICAL_ADDRESS MemoryBaseAddress; - - /// - /// The length in bytes of memory allocated by this HOB. - /// - UINT64 MemoryLength; - - /// - /// Defines the type of memory allocated by this HOB. The memory type definition - /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined - /// in AllocatePages() in the UEFI 2.0 specification. - /// - EFI_MEMORY_TYPE MemoryType; - - /// - /// Padding for Itanium processor family - /// - UINT8 Reserved[4]; -} EFI_HOB_MEMORY_ALLOCATION_HEADER; - -/// -/// Describes all memory ranges used during the HOB producer -/// phase that exist outside the HOB list. This HOB type -/// describes how memory is used, not the physical attributes of memory. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the - /// various attributes of the logical memory allocation. - /// - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; - // - // Additional data pertaining to the "Name" Guid memory - // may go here. - // -} EFI_HOB_MEMORY_ALLOCATION; - -/// -/// The resource type. -/// -typedef UINT32 EFI_RESOURCE_TYPE; - -// -// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR. -// -#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 -#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 -#define EFI_RESOURCE_IO 0x00000002 -#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 -#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004 -#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 -#define EFI_RESOURCE_IO_RESERVED 0x00000006 -#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 - -/// -/// A type of recount attribute type. -/// -typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; - -// -// These types can be ORed together as needed. -// -// The first three enumerations describe settings -// -#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 -#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 -#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 -// -// The rest of the settings describe capabilities -// -#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 -#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 -#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 -#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 -#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 - -/// -/// Describes the resource properties of all fixed, -/// nonrelocatable resource ranges found on the processor -/// host bus during the HOB producer phase. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID representing the owner of the resource. This GUID is used by HOB - /// consumer phase components to correlate device ownership of a resource. - /// - EFI_GUID Owner; - /// - /// The resource type enumeration as defined by EFI_RESOURCE_TYPE. - /// - EFI_RESOURCE_TYPE ResourceType; - /// - /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE. - /// - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - /// - /// The physical start address of the resource region. - /// - EFI_PHYSICAL_ADDRESS PhysicalStart; - /// - /// The number of bytes of the resource region. - /// - UINT64 ResourceLength; -} EFI_HOB_RESOURCE_DESCRIPTOR; - -/// -/// Allows writers of executable content in the HOB producer phase to -/// maintain and manage HOBs with specific GUID. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID that defines the contents of this HOB. - /// - EFI_GUID Name; - // - // Guid specific data goes here - // -} EFI_HOB_GUID_TYPE; - -/// -/// Union of all the possible HOB Types. -/// -typedef union { - EFI_HOB_GENERIC_HEADER *Header; - EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; - EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; - EFI_HOB_GUID_TYPE *Guid; - UINT8 *Raw; -} EFI_PEI_HOB_POINTERS; - - -/** - Returns the type of a HOB. - - This macro returns the HobType field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobType. - -**/ -#define GET_HOB_TYPE(HobStart) \ - ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType) - -/** - Returns the length, in bytes, of a HOB. - - This macro returns the HobLength field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobLength. - -**/ -#define GET_HOB_LENGTH(HobStart) \ - ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength) - -/** - Returns a pointer to the next HOB in the HOB list. - - This macro returns a pointer to HOB that follows the - HOB specified by HobStart in the HOB List. - - @param HobStart A pointer to a HOB. - - @return A pointer to the next HOB in the HOB list. - -**/ -#define GET_NEXT_HOB(HobStart) \ - (VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart)) - -/** - Determines if a HOB is the last HOB in the HOB list. - - This macro determine if the HOB specified by HobStart is the - last HOB in the HOB list. If HobStart is last HOB in the HOB list, - then TRUE is returned. Otherwise, FALSE is returned. - - @param HobStart A pointer to a HOB. - - @retval TRUE The HOB specified by HobStart is the last HOB in the HOB list. - @retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list. - -**/ -#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST) - -/** - Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns a pointer to the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return A pointer to the data buffer in a HOB. - -**/ -#define GET_GUID_HOB_DATA(HobStart) \ - (VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE)) - -/** - Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return The size of the data buffer. -**/ -#define GET_GUID_HOB_DATA_SIZE(HobStart) \ - (UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE)) - - -/** - - FSP specific GUID HOB definitions - - **/ -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - { \ - 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ - } - -#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ - { \ - 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ - } - -#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ - { \ - 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ - } - -#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ - { \ - 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ - } - -#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ - { \ - 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ - } - -#define FSP_HOB_GRAPHICS_INFO_GUID \ -{ 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } } - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_infoheader.h b/BraswellFspBinPkg/SampleCode/fsp_infoheader.h deleted file mode 100644 index 1af1abb..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_infoheader.h +++ /dev/null @@ -1,118 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_INFO_HEADER_H_ -#define _FSP_INFO_HEADER_H_ - -/// -/// Fixed FSP header offset in the FSP image -/// -#define FSP_INFO_HEADER_OFF 0x94 - -#pragma pack(1) - -typedef struct { - /// - /// Signature ('FSPH') for the FSP Information Header - /// - UINT32 Signature; - /// - /// Length of the FSP Information Header - /// - UINT32 HeaderLength; - /// - /// Reserved - /// - UINT8 Reserved1[3]; - /// - /// Revision of the FSP Information Header - /// - UINT8 HeaderRevision; - /// - /// Revision of the FSP binary - /// - UINT32 ImageRevision; - - - /// - /// Signature string that will help match the FSP Binary to a supported - /// hardware configuration. - /// - CHAR8 ImageId[8]; - /// - /// Size of the entire FSP binary - /// - UINT32 ImageSize; - /// - /// FSP binary preferred base address - /// - UINT32 ImageBase; - - - /// - /// Attribute for the FSP binary - /// - UINT32 ImageAttribute; - /// - /// Offset of the FSP configuration region - /// - UINT32 CfgRegionOffset; - /// - /// Size of the FSP configuration region - /// - UINT32 CfgRegionSize; - /// - /// Number of API entries this FSP supports - /// - UINT32 ApiEntryNum; - - - /// - /// TempRamInit API entry offset - /// - UINT32 TempRamInitEntry; - /// - /// FspInit API entry offset - /// - UINT32 FspInitEntry; - /// - /// NotifyPhase API entry offset - /// - UINT32 NotifyPhaseEntry; - /// - /// Reserved - /// - UINT32 Reserved2; - -} FSP_INFO_HEADER; - -#pragma pack() - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_platform.h b/BraswellFspBinPkg/SampleCode/fsp_platform.h deleted file mode 100644 index a725123..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_platform.h +++ /dev/null @@ -1,75 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_PLATFORM_H__ -#define __FSP_PLATFORM_H__ - -#pragma pack(1) - -typedef struct { - uint32_t RedMask; - uint32_t GreenMask; - uint32_t BlueMask; - uint32_t ReservedMask; -} EFI_PIXEL_BITMASK; - -typedef enum { - PixelRedGreenBlueReserved8BitPerColor, - PixelBlueGreenRedReserved8BitPerColor, - PixelBitMask, - PixelBltOnly, - PixelFormatMax -} EFI_GRAPHICS_PIXEL_FORMAT; - -typedef struct { - uint32_t Version; - uint32_t HorizontalResolution; - uint32_t VerticalResolution; - EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; - EFI_PIXEL_BITMASK PixelInformation; - uint32_t PixelsPerScanLine; -} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION; - -typedef struct { - uint64_t FrameBufferBase; - uint64_t FrameBufferSize; - EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode; -} PLATFORM_GRAPHICS_OUTPUT; - -typedef struct { - /// - /// FSP common runtime data structure - /// - FSP_INIT_RT_COMMON_BUFFER Common; -} FSP_INIT_RT_BUFFER; - -#pragma pack() - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_support.h b/BraswellFspBinPkg/SampleCode/fsp_support.h deleted file mode 100644 index 8a32d99..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_support.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/** \file fsp_support.h - * - * - */ - - -#ifndef __FSP_SUPPORT_H__ -#define __FSP_SUPPORT_H__ - -UINT32 -GetPhysicalLowMemTop ( - CONST VOID *HobStart -); - -UINT32 -GetUsableLowMemTop ( - CONST VOID *HobListPtr - ); - -UINT64 -GetUsableHighMemTop ( - CONST VOID *HobListPtr - ); - -VOID * -GetGuidHobDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length, - EFI_GUID *Guid - ); - -UINT64 -GetFspReservedMemoryFromGuid ( - CONST VOID *HobListPtr, - UINT64 *FspMemoryLength, - EFI_GUID *FspReservedMemoryGuid - ); - -UINT32 -GetTsegReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -); - -UINT32 -GetFspReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -); - -VOID* -GetFspNvsDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length - ); - -VOID * -GetBootloaderTempMemoryBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length - ); - -VOID * -EFIAPI -GetNextHob ( - UINT16 Type, - CONST VOID *HobStart - ); - -VOID * -EFIAPI -GetFirstHob ( - UINT16 Type - ); - -VOID * -EFIAPI -GetNextGuidHob ( - CONST EFI_GUID *Guid, - CONST VOID *HobStart - ); - -VOID * -EFIAPI -GetFirstGuidHob ( - CONST EFI_GUID *Guid - ); - -VOID -UpdateFspUpdConfigs ( - UPD_DATA_REGION *UpdDataRgn - ); - -VOID * -GetFspGraphicsModeData( - CONST VOID *HobListPtr, - UINT32 *DataSize -); - -#endif diff --git a/BraswellFspBinPkg/SampleCode/fsp_types.h b/BraswellFspBinPkg/SampleCode/fsp_types.h deleted file mode 100644 index 8ff310c..0000000 --- a/BraswellFspBinPkg/SampleCode/fsp_types.h +++ /dev/null @@ -1,222 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/// -/// 8-byte unsigned value. -/// -typedef unsigned long long UINT64; - -/// -/// 8-byte signed value. -/// -typedef long long INT64; - -/// -/// 4-byte unsigned value. -/// -typedef unsigned int UINT32; - -/// -/// 4-byte signed value. -/// -typedef int INT32; - -/// -/// 2-byte unsigned value. -/// -typedef unsigned short UINT16; - -/// -/// 2-byte Character. -/// -typedef unsigned short CHAR16; -/// -/// 2-byte signed value. -/// -typedef short INT16; - -/// -/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other -/// values are undefined. -/// -typedef unsigned char BOOLEAN; - -/// -/// 1-byte unsigned value. -/// -typedef unsigned char UINT8; - -/// -/// 1-byte Character -/// -typedef char CHAR8; - -/// -/// 1-byte signed value -/// -typedef char INT8; - -/// -/// Undeclared type. -/// -typedef void VOID; - -/// -/// 64-bit physical memory address. -/// -typedef UINT64 EFI_PHYSICAL_ADDRESS; - -/// -/// UEFI and FSP defined status. -/// -typedef UINT32 EFI_STATUS; -#define FSP_STATUS EFI_STATUS - -/// -/// Datum is read-only. -/// -#define CONST const - -/// -/// Datum is scoped to the current file or function. -/// -#define STATIC static - -/// -/// Boolean true value. UEFI Specification defines this value to be 1, -/// but this form is more portable. -/// -#define TRUE ((BOOLEAN)(1==1)) - -/// -/// Boolean false value. UEFI Specification defines this value to be 0, -/// but this form is more portable. -/// -#define FALSE ((BOOLEAN)(0==1)) - -/// -/// Null pointer -/// -#ifndef NULL -#define NULL ((VOID *) 0) -#endif - -/// -/// Modifier to ensure that all API functions use the correct C calling -/// convention. -/// -#define EFIAPI __attribute__((cdecl)) -#define FSPAPI EFIAPI - -/// -/// 128 bit buffer containing a unique identifier value. -/// -typedef struct { - UINT32 Data1; - UINT16 Data2; - UINT16 Data3; - UINT8 Data4[8]; -} EFI_GUID; - -/** - Returns a 16-bit signature built from 2 ASCII characters. - - This macro returns a 16-bit value built from the two ASCII characters specified - by A and B. - - @param A The first ASCII character. - @param B The second ASCII character. - - @return A 16-bit value built from the two ASCII characters specified by A and B. - -**/ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - Returns a 32-bit signature built from 4 ASCII characters. - - This macro returns a 32-bit value built from the four ASCII characters specified - by A, B, C, and D. - - @param A The first ASCII character. - @param B The second ASCII character. - @param C The third ASCII character. - @param D The fourth ASCII character. - - @return A 32-bit value built from the two ASCII characters specified by A, B, - C and D. - -**/ -#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16)) - -/** - Returns a 64-bit signature built from 8 ASCII characters. - - This macro returns a 64-bit value built from the eight ASCII characters specified - by A, B, C, D, E, F, G,and H. - - @param A The first ASCII character. - @param B The second ASCII character. - @param C The third ASCII character. - @param D The fourth ASCII character. - @param E The fifth ASCII character. - @param F The sixth ASCII character. - @param G The seventh ASCII character. - @param H The eighth ASCII character. - - @return A 64-bit value built from the two ASCII characters specified by A, B, - C, D, E, F, G and H. - -**/ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) - -/// -/// Assertion for debug -/// -#define ASSERT(Expression) do { if (!(Expression)) for (;;); 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TITLE BMP.bsf - BMP Scrip File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2011). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ - -StructDef - -Find "BIOS_DATA_BLOCK " - - ; The following block will determine the reference - ; pointer for all table pointer variables. - -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - ; = 0, DESKTOP - ; = 1, MOBILE - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 17 - SandyBridge-Desktop - ; = 18 - Sandybridge-Mobile - ; = 19 - Ivybridge-Desktop - ; = 20 - Ivybridge-Mobile - ; = 21 - Haswell-Desktop - ; = 22 - Haswell-Mobile - - ; = 24 - VaalleyView - -$Integrated_LVDS 1 bit ; Integrated LVDS Support: - ; 1 = Yes - ; 0 = None - -$Integrated_TV 1 bit ; Integrated TV Support: - ; 1 = Yes - ; 0 = None - -$Integrated_EFP 1 bit ; Integrated EFP Support: - ; 1 = Yes - ; 0 = None - -$eDP 1 bit ; eDP: - ; 1 = Yes - ; 0 = None - -SKIP 4 bits -SKIP 4 bytes ; Skip build number string - - ; Signon and copyright strings - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - - ; General Byte Definitions - -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Popup Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - - ; - ; bmp_Bits_1 - ; - -$Enable_Panel_Fitting 2 bits ; Enable / Disable panel fitting -$Flexaim_Support 1 bit ; Enable / Disable Flex-aim support -$Msg_Enable 1 bit ; Disable signon and copyright -$Cls_After_Signon 3 bits ; Clear screen after display message and pause -$bmp_DVO_A_Color_Flip 1 bit ; Flat color flip -ALIGN - - ; - ; bmp_Bits_2 - ; -$Download_Ext_VBT 1 bit ; Download external VBT flag -$Enable_SSC 1 bit ; Enable/Disable SSC -$SSC_Freq 1 bit ; SSC Frequency -$Enable_LFPOn_Override 1 bit ; Enable/Disable LFP ON Override -$Disable_SSC_DDT 1 bit ; Disable SSC in Dual Display Twin -$Override_VGA_720p 1 bit ; Enable/Disable Override 720p for VGA modes -$Display_Clock_Mode 1 bit ; Enables DCI mode or legacy BTM mode -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS - -ALIGN - ; - ; bmp_Bits_3 - ; -SKIP 2 bits -$180_Deg_Rotation_Enable 1 bit ; 180 Degree Rotation Enable bit -SKIP 5 bits -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Use legacy monitor detect algorithm -SKIP 7 bits -ALIGN - - ; - ; Int_Displays_Support - ; -$Int_CRT_Support 1 bit ; Integrated CRT support -$Int_TV_Support 1 bit ; Integrated TV support -$Int_EFP_Support 1 bit ; Integrated EFP support -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -$DP_SSC_Freq 1 bit ; DP SSC Frequency bit -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits - -ALIGN - - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte -$ChildDevice1Primary 1 byte -$ChildDevice1Secondary 1 byte -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$CRT_DDC_GMBUS_Pin 1 byte ; CRT DDC GMBUS pin pair - -$DPMS_ACPI_Bit 1 bit ; Apply ACPI DPMS CRT Power States -$Skip_Boot_CRT_Detect 1 bit ; Disable/Enable skip boot CRT detect -$DPMS_AIM_Bit 1 bit ; Apply DPMS to AIM devices -SKIP 5 bits -ALIGN - - -$Boot_Display 2 bytes ; Boot display type -$size_ChildStruc 1 byte - - -$Int_LFP1_DID 2 bytes ; Skip Device Handle -$Int_LFP1_Type 2 bytes ; Device type -SKIP 7 bytes ; Skip -SKIP 1 byte ; Skip -$Int_LFP1_Priority 1 byte ; primary/secondary panel select -ALIGN -SKIP 3 bytes ; Skip -$Int_LFP1_Port 1 byte ; eDP port select -SKIP 2 bytes ; Skip remaining Data structure -$Int_LFP1_DDC_Pin 1 byte ; LFP DDC GMBUS pin pair -SKIP 5 bytes -$Int_LFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 7 bytes -SKIP 4 bytes - - - - -$Int_EFP1_DID 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP1_OnBoard_PreEmph_Level 3 bits ; EFP1 On Board Dp Redriver PreEmphasis Level -$EFP1_OnBoard_VSwing_Level 3 bits ; EFP1 On Board Dp Redriver VSwing Level -$EFP1_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP1 -SKIP 1 bit ; Reserved -$EFP1_OnDock_PreEmph_Level 3 bits ; EFP1 On Dock Dp Redriver PreEmphasis Level -$EFP1_OnDock_VSwing_Level 3 bits ; EFP1 On Dock Dp Redriver VSwing Level -$EFP1_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP1 -SKIP 1 bit ; Reserved -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes -$Int_EFP1_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP1_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP1_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP1_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP1_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP1_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP1_GPIO_Number 2 bytes ;GPIO number - - -$Int_EFP2_DID 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP2_OnBoard_PreEmph_Level 3 bits ; EFP2 On Board Dp Redriver PreEmphasis Level -$EFP2_OnBoard_VSwing_Level 3 bits ; EFP2 On Board Dp Redriver VSwing Level -$EFP2_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$EFP2_OnDock_PreEmph_Level 3 bits ; EFP2 On Dock Dp Redriver PreEmphasis Level -$EFP2_OnDock_VSwing_Level 3 bits ; EFP2 On Dock Dp Redriver VSwing Level -$EFP2_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes -$Int_EFP2_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP2_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP2_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP2_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP2_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP2_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP2_GPIO_Number 2 bytes ;GPIO number - - -$Int_EFP3_DID 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP3_OnBoard_PreEmph_Level 3 bits ; EFP3 On Board Dp Redriver PreEmphasis Level -$EFP3_OnBoard_VSwing_Level 3 bits ; EFP3 On Board Dp Redriver VSwing Level -$EFP3_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$EFP3_OnDock_PreEmph_Level 3 bits ; EFP3 On Dock Dp Redriver PreEmphasis Level -$EFP3_OnDock_VSwing_Level 3 bits ; EFP3 On Dock Dp Redriver VSwing Level -$EFP3_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP3 -SKIP 1 bit ; Reserved -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP3_Port 1 byte ; EFP3 port -SKIP 2 bytes ; Skip -$Int_EFP3_DDC_Pin 1 byte ; EFP3 DDC Pin -SKIP 3 bytes -$Int_EFP3_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP3_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP3_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP3_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP3_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP3_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP3_GPIO_Number 2 bytes ;GPIO number - - - - - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Display must be attached or not - -;============================================================================== -; Block 4 - Mode Support Bit Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 28 bytes ; Mode List - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$H31_POST_End_Hook 1 byte ; POST end hook int vector -$H33_After_Mode_Set 1 byte ; After mode set hook -$H35_Bootup_Display 1 byte ; Bootup display hook -$H38_Before_Mode_Set 1 byte ; Before mode set hook -$H45_VESA_DDC_Hook 1 byte ; VESA DDC hook interrupt vector -$H46_VESA_PM_Hook 1 byte ; VESA PM hook interrupt vector -$H47_Notify_Display_Sw 1 byte ; Notify display switch hook -$H48_After_VESA_PM 1 byte ; After VESA PM hook -$H14_Update_Display 1 byte ; Update Expansion/Display State Hook -$H14_Get_Misc_Status 1 byte ; Get Miscellaneous Status Hook -$H36_Boot_TV_Format 1 byte ; Boot TV to NTSC/PAL -$H34_Set_LFP_Fitting 1 byte ; Set panel fitting flags -$H40_Set_Panel_Type 1 byte ; Set panel fitting flags -$H49_Get_BL_Inv_Pol 1 byte ; Get inverter type and polarity for backlight -$H51_LFP_Panel_Type 1 byte ; Get active LFP configuration from CMOS setup -$H74_SR_Enable 1 byte ; Hook to enable/ disable Self Refresh as part of WA. - - ; BMP - Pointer tables - -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at BMP Remove configurations table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - - -$Mode_Rem_Table_Ptr 2 bytes ; Start at BMP Boot table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -SKIP 80 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initializaton -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initializaton -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 61 bytes ; Skip data - -;============================================================================== - -;============================================================================== -; Block 9 - PSR Feature Table -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 96 bytes ; PSR Table data - -;============================================================================== - - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 203 bytes ; Skip data - - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Driver_Boot_Device 1 bit -$Block_Disp_Switch 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Allow FS DOS display switching -$Hot_Plug_DVO 1 bit -$Dual_View_Zoom 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; X resolution -$Driver_Boot_Mode_Y 2 bytes ; Y resolution -$Driver_Boot_Mode_BPP 1 byte ; Pixel depth -$Driver_Boot_Mode_RR 1 byte ; Refresh rate -; bmp_Ext_Driver_Bits - -$Enable_LFP_Primary 1 bit -$GTF_Mode_Pruning 1 bit -SKIP 1 bit ; DISABLE_DFGT -SKIP 1 bit ; DISABLE_DFGT -$NT4_Dual_Dsp_Clone_Spt 1 bit ; Dual display clone support for NT4 -$Default_Power_Scheme 1 bit -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; SDVO device power down -$Hot_Plug_CRT 1 bit ; CRT hot plug -$LVDS_Config 2 bits ; LVDS configuration -$Hot_Plug_TV 1 bit ; Hot plug TV enable/disable -$INT_HDMI_Config 2 bits ; Integrated HDMI Configuration -ALIGN - - ; bmp_Driver_Flags_1 - -$CUIHotK_Static_Display 1 bit -SKIP 7 bits -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes -ALIGN - -; bmp_Ext2_Driver_Bits - -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number -ALIGN - - ; bmp_Driver_Feature_Flags - -SKIP 5 bits -$PM_DRRS_Enable 1 bit ; Intel ® Display Refresh Rate Switching (DRRS) Enable/Disable Flag. -SKIP 3 bits -$Panel_Self_Refresh 1 bit ; Panel Self refresh feature (PSR) -SKIP 2 bits -$DMRRS 1 bit ; Dynamic Media Refresh Rate Enable/Disable -SKIP 3 bits - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Driver_Persist_Hotkey 1 bit -$Driver_Persist_Lid_Switch 1 bit -$Driver_Persist_PM 1 bit -$PersistHotkeyRestoreCloneMDS 1 bit -$PersistHotkeyRestoreRefreshrate 1 bit -$PersistHotkeyRestorePipe 1 bit -$PersistHotkeyRestoreMode 1 bit -$PersistEDIDRestoreMode 1 bit -$PersistHotPlugRestoreMode 1 bit -$Driver_Persist_Docking 1 bit -SKIP 6 bits -ALIGN -$PersistMaxConfig 1 byte - -;============================================================================== -; Block 16 - VBIOS/Driver Toggle list, capabilities tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 132 bytes ; Skip Toggle lists -ALIGN - - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$SV_Dis_Arbiter 1 bit ; Disable VGA fast arbiter -$SV_Setmode_No_DVO 1 bit ; Do Setmode without reprogramming DVO -$SV_Special_GMBus 1 bit ; Special GMBus support -$SV_Wait_Timeout_Hang 1 bit -SKIP 4 bits -ALIGN -SKIP 7 bytes ; Skip reserved space - - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Rotation_Support_Enable 1 bit ; Driver Rotation Feature Support bit -SKIP 7 bits -$Rot_Flags 1 byte -SKIP 10 bytes - - -;============================================================================== -; Block 19 - Removed Display Configurations -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip ID -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV Options -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip ID and size -$Under_Over_Scan_Via_YPrPb 2 bits ; Underscan/overscan for HDTV via YPrPb -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Underscan/overscan for HDTV via DVI -$Add_Overscan_Mode 1 bit ; Add modes to avoid overscan issue -$D_Connector 1 bit ; D-Connector Support -ALIGN - -;============================================================================== -; Block #27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - - ; Panel#1 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - - ; Panel#2 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - - ; Panel#3 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - - ; Panel#4 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - - ; Panel#5 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - - ; Panel#6 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - - ; Panel#7 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - - ; Panel#8 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - - ; Panel#9 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - - ; Panel#10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - - ; Panel#11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - - ; Panel#12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - - ; Panel#13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - - ; Panel#14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - - ; Panel#15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - - ; Panel#16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -$eDP_Link_DataRate_01 4 bits ; Panel #1 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #1 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #1 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #1 Link Voltage Swing - -$eDP_Link_DataRate_02 4 bits ; Panel #2 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #2 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #2 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #2 Link Voltage Swing - -$eDP_Link_DataRate_03 4 bits ; Panel #3 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #3 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #3 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #3 Link Voltage Swing - -$eDP_Link_DataRate_04 4 bits ; Panel #4 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #4 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #4 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #4 Link Voltage Swing - -$eDP_Link_DataRate_05 4 bits ; Panel #5 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #5 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #5 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #5 Link Voltage Swing - -$eDP_Link_DataRate_06 4 bits ; Panel #6 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #6 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #6 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #6 Link Voltage Swing - -$eDP_Link_DataRate_07 4 bits ; Panel #7 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #7 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #7 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #7 Link Voltage Swing - -$eDP_Link_DataRate_08 4 bits ; Panel #8 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #8 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #8 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #8 Link Voltage Swing - -$eDP_Link_DataRate_09 4 bits ; Panel #9 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #9 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #9 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #9 Link Voltage Swing - -$eDP_Link_DataRate_10 4 bits ; Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -$eDP_Link_DataRate_11 4 bits ; Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -$eDP_Link_DataRate_12 4 bits ; Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -$eDP_Link_DataRate_13 4 bits ; Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -$eDP_Link_DataRate_14 4 bits ; Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -$eDP_Link_DataRate_15 4 bits ; Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -$eDP_Link_DataRate_16 4 bits ; Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -$eDP_sDRRS_MSA_Delay_01 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_02 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_03 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_04 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_05 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_06 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_07 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_08 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_09 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_10 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_11 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_12 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_13 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_14 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_15 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_16 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 - -SKIP 2 bytes ; S3D Feature -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_1 4 bits; eDp selects VSwing Preemph table for panel #1 -$eDP_VSwingPreEmph_2 4 bits; eDp selects VSwing Preemph table for panel #2 -$eDP_VSwingPreEmph_3 4 bits; eDp selects VSwing Preemph table for panel #3 -$eDP_VSwingPreEmph_4 4 bits; eDp selects VSwing Preemph table for panel #4 -$eDP_VSwingPreEmph_5 4 bits; eDp selects VSwing Preemph table for panel #5 -$eDP_VSwingPreEmph_6 4 bits; eDp selects VSwing Preemph table for panel #6 -$eDP_VSwingPreEmph_7 4 bits; eDp selects VSwing Preemph table for panel #7 -$eDP_VSwingPreEmph_8 4 bits; eDp selects VSwing Preemph table for panel #8 -$eDP_VSwingPreEmph_9 4 bits; eDp selects VSwing Preemph table for panel #9 -$eDP_VSwingPreEmph_10 4 bits; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits; eDp selects VSwing Preemph table for panel #16 - -$Fast_Link_Training_Supported_01 1 bit ; eDP Selects Fast Link Training if supported for Panel #1 -$Fast_Link_Training_Supported_02 1 bit ; eDP Selects Fast Link Training if supported for Panel #2 -$Fast_Link_Training_Supported_03 1 bit ; eDP Selects Fast Link Training if supported for Panel #3 -$Fast_Link_Training_Supported_04 1 bit ; eDP Selects Fast Link Training if supported for Panel #4 -$Fast_Link_Training_Supported_05 1 bit ; eDP Selects Fast Link Training if supported for Panel #5 -$Fast_Link_Training_Supported_06 1 bit ; eDP Selects Fast Link Training if supported for Panel #6 -$Fast_Link_Training_Supported_07 1 bit ; eDP Selects Fast Link Training if supported for Panel #7 -$Fast_Link_Training_Supported_08 1 bit ; eDP Selects Fast Link Training if supported for Panel #8 -$Fast_Link_Training_Supported_09 1 bit ; eDP Selects Fast Link Training if supported for Panel #9 -$Fast_Link_Training_Supported_10 1 bit ; eDP Selects Fast Link Training if supported for Panel #10 -$Fast_Link_Training_Supported_11 1 bit ; eDP Selects Fast Link Training if supported for Panel #11 -$Fast_Link_Training_Supported_12 1 bit ; eDP Selects Fast Link Training if supported for Panel #12 -$Fast_Link_Training_Supported_13 1 bit ; eDP Selects Fast Link Training if supported for Panel #13 -$Fast_Link_Training_Supported_14 1 bit ; eDP Selects Fast Link Training if supported for Panel #14 -$Fast_Link_Training_Supported_15 1 bit ; eDP Selects Fast Link Training if supported for Panel #15 -$Fast_Link_Training_Supported_16 1 bit ; eDP Selects Fast Link Training if supported for Panel #16 - -SKIP 2 bytes ;Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#7 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#7 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#8 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#8 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#9 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#9 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#16 - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for HSW/BDW/CHV -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List1 32 bytes ; Toggle list 1 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List2 16 bytes ; Toggle list 2 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List3 16 bytes ; Toggle list 3 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List4 16 bytes ; Toggle list 4 -ALIGN - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsoleted -SKIP 6 bits -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit -SKIP 1 byte - - ; INT_LVDS_Panel_Channel_Bits - -$Int_LVDS_Panel_1_Channel_Type 2 bits ; Bits [2:3] = Panel #1 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_2_Channel_Type 2 bits ; Bits [2:3] = Panel #2 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_3_Channel_Type 2 bits ; Bits [2:3] = Panel #3 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_4_Channel_Type 2 bits ; Bits [2:3] = Panel #4 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_5_Channel_Type 2 bits ; Bits [2:3] = Panel #5 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_6_Channel_Type 2 bits ; Bits [2:3] = Panel #6 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_7_Channel_Type 2 bits ; Bits [2:3] = Panel #7 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_8_Channel_Type 2 bits ; Bits [2:3] = Panel #8 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_9_Channel_Type 2 bits ; Bits [2:3] = Panel #9 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_10_Channel_Type 2 bits ; Bits [2:3] = Panel #10 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_11_Channel_Type 2 bits ; Bits [2:3] = Panel #11 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_12_Channel_Type 2 bits ; Bits [2:3] = Panel #12 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_13_Channel_Type 2 bits ; Bits [2:3] = Panel #13 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_14_Channel_Type 2 bits ; Bits [2:3] = Panel #14 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_15_Channel_Type 2 bits ; Bits [2:3] = Panel #15 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_16_Channel_Type 2 bits ; Bits [2:3] = Panel #16 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved - - ; LVDS Spread Spectrum Clock - ; Enabel/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No, 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - - ; LVDS Spread Spectrum Clock Frequency - ; SSC Frequency -$SSC_Freq01 1 bit ; Panel #01, 0=48MHz, 1=66MHz -$SSC_Freq02 1 bit ; Panel #02, 0=48MHz, 1=66MHz -$SSC_Freq03 1 bit ; Panel #03, 0=48MHz, 1=66MHz -$SSC_Freq04 1 bit ; Panel #04, 0=48MHz, 1=66MHz -$SSC_Freq05 1 bit ; Panel #05, 0=48MHz, 1=66MHz -$SSC_Freq06 1 bit ; Panel #06, 0=48MHz, 1=66MHz -$SSC_Freq07 1 bit ; Panel #07, 0=48MHz, 1=66MHz -$SSC_Freq08 1 bit ; Panel #08, 0=48MHz, 1=66MHz -$SSC_Freq09 1 bit ; Panel #09, 0=48MHz, 1=66MHz -$SSC_Freq10 1 bit ; Panel #10, 0=48MHz, 1=66MHz -$SSC_Freq11 1 bit ; Panel #11, 0=48MHz, 1=66MHz -$SSC_Freq12 1 bit ; Panel #12, 0=48MHz, 1=66MHz -$SSC_Freq13 1 bit ; Panel #13, 0=48MHz, 1=66MHz -$SSC_Freq14 1 bit ; Panel #14, 0=48MHz, 1=66MHz -$SSC_Freq15 1 bit ; Panel #15, 0=48MHz, 1=66MHz -$SSC_Freq16 1 bit ; Panel #16, 0=48MHz, 1=66MHz - - ; Disable SSC in Dual Display Twin -$Disable_SSC_DDT01 1 bit ; panel #01, 0=Disable, 1=Enable -$Disable_SSC_DDT02 1 bit ; panel #02, 0=Disable, 1=Enable -$Disable_SSC_DDT03 1 bit ; panel #03, 0=Disable, 1=Enable -$Disable_SSC_DDT04 1 bit ; panel #04, 0=Disable, 1=Enable -$Disable_SSC_DDT05 1 bit ; panel #05, 0=Disable, 1=Enable -$Disable_SSC_DDT06 1 bit ; panel #06, 0=Disable, 1=Enable -$Disable_SSC_DDT07 1 bit ; panel #07, 0=Disable, 1=Enable -$Disable_SSC_DDT08 1 bit ; panel #08, 0=Disable, 1=Enable -$Disable_SSC_DDT09 1 bit ; panel #09, 0=Disable, 1=Enable -$Disable_SSC_DDT10 1 bit ; panel #10, 0=Disable, 1=Enable -$Disable_SSC_DDT11 1 bit ; panel #11, 0=Disable, 1=Enable -$Disable_SSC_DDT12 1 bit ; panel #12, 0=Disable, 1=Enable -$Disable_SSC_DDT13 1 bit ; panel #13, 0=Disable, 1=Enable -$Disable_SSC_DDT14 1 bit ; panel #14, 0=Disable, 1=Enable -$Disable_SSC_DDT15 1 bit ; panel #15, 0=Disable, 1=Enable -$Disable_SSC_DDT16 1 bit ; panel #16, 0=Disable, 1=Enable - -$INT_Panel_Color_Depth01 1 bit ; Panel #01, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth02 1 bit ; Panel #02, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth03 1 bit ; Panel #03, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth04 1 bit ; Panel #04, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth05 1 bit ; Panel #05, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth06 1 bit ; Panel #06, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth07 1 bit ; Panel #07, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth08 1 bit ; Panel #08, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth09 1 bit ; Panel #09, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth10 1 bit ; Panel #10, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth11 1 bit ; Panel #11, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth12 1 bit ; Panel #12, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth13 1 bit ; Panel #13, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth14 1 bit ; Panel #14, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth15 1 bit ; Panel #15, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth16 1 bit ; Panel #16, 0 = 18bpps, 1 = 24bpps - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -SKIP 2 bytes ;LfpPanelNameTable Offset -SKIP 1 byte ;LfpPanelName Length - - - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - - ; Flat Panel #1 - -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither01 1 bit ; Panel #01, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ; address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_01 13 bits ; Power on Backlight Enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_01 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ; address-0x6120C or 0x0C720C (for ILM) -Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_01 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_01 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM) -Panel power cycle delay and reference divider -$PowerCycleDelay_01 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -ALIGN -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end - -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #2 - -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither02 1 bit ; Panel #02, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_02 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_02 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_02 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_02 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_02 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #3 - -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither03 1 bit ; Panel #03, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_03 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_03 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_03 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_03 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;aaddress-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_03 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #4 - -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither04 1 bit ; Panel #04, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_04 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_04 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_04 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_04 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_04 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #5 - -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither05 1 bit ; Panel #05, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_05 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_05 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_05 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_05 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_05 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #6 - -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither06 1 bit ; Panel #06, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_06 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_06 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_06 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_06 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_06 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #7 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither07 1 bit ; Panel #07, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_07 13 bits ; Power on Backlight enable delay delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_07 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_07 13 bits ; Backlight off delay power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_07 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_07 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #8 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither08 1 bit ; Panel #08, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_08 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_08 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_08 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_08 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_08 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #9 - -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither09 1 bit ; Panel #09, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_09 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_09 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_09 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_09 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_09 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #10 - -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither10 1 bit ; Panel #10, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_10 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_10 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_10 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_10 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_10 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #11 - -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither11 1 bit ; Panel #11, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_11 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_11 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_11 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_11 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_11 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #12 - -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither12 1 bit ; Panel #12, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_12 13 bits ; Powen on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_12 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_12 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_12 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_12 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #13 - -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither13 1 bit ; Panel #13, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_13 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_13 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_13 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_13 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_13 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #14 - -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither14 1 bit ; Panel #14, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_14 13 bits ; Power on baklight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_14 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_14 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_14 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_14 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #15 - -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither15 1 bit ; Panel #15, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_15 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_15 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_15 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_15 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_15 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #16 - -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither16 1 bit ; Panel #16, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_16 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_16 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_16 13 bits ; backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_16 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_16 5 bits ; Power cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -$Enable_Scaling_01 1 bit ; Scaling Enable bit for Panel#1 -$Enable_Scaling_02 1 bit ; Scaling Enable bit for Panel#2 -$Enable_Scaling_03 1 bit ; Scaling Enable bit for Panel#3 -$Enable_Scaling_04 1 bit ; Scaling Enable bit for Panel#4 -$Enable_Scaling_05 1 bit ; Scaling Enable bit for Panel#5 -$Enable_Scaling_06 1 bit ; Scaling Enable bit for Panel#6 -$Enable_Scaling_07 1 bit ; Scaling Enable bit for Panel#7 -$Enable_Scaling_08 1 bit ; Scaling Enable bit for Panel#8 -$Enable_Scaling_09 1 bit ; Scaling Enable bit for Panel#9 -$Enable_Scaling_10 1 bit ; Scaling Enable bit for Panel#10 -$Enable_Scaling_11 1 bit ; Scaling Enable bit for Panel#11 -$Enable_Scaling_12 1 bit ; Scaling Enable bit for Panel#12 -$Enable_Scaling_13 1 bit ; Scaling Enable bit for Panel#13 -$Enable_Scaling_14 1 bit ; Scaling Enable bit for Panel#14 -$Enable_Scaling_15 1 bit ; Scaling Enable bit for Panel#15 -$Enable_Scaling_16 1 bit ; Scaling Enable bit for Panel#16 - -$Seamless_DRRS_Min_RR_01 1 byte ; Seamless DRRS Min Refresh Rate for Panel#1 -$Seamless_DRRS_Min_RR_02 1 byte ; Seamless DRRS Min Refresh Rate for Panel#2 -$Seamless_DRRS_Min_RR_03 1 byte ; Seamless DRRS Min Refresh Rate for Panel#3 -$Seamless_DRRS_Min_RR_04 1 byte ; Seamless DRRS Min Refresh Rate for Panel#4 -$Seamless_DRRS_Min_RR_05 1 byte ; Seamless DRRS Min Refresh Rate for Panel#5 -$Seamless_DRRS_Min_RR_06 1 byte ; Seamless DRRS Min Refresh Rate for Panel#6 -$Seamless_DRRS_Min_RR_07 1 byte ; Seamless DRRS Min Refresh Rate for Panel#7 -$Seamless_DRRS_Min_RR_08 1 byte ; Seamless DRRS Min Refresh Rate for Panel#8 -$Seamless_DRRS_Min_RR_09 1 byte ; Seamless DRRS Min Refresh Rate for Panel#9 -$Seamless_DRRS_Min_RR_10 1 byte ; Seamless DRRS Min Refresh Rate for Panel#10 -$Seamless_DRRS_Min_RR_11 1 byte ; Seamless DRRS Min Refresh Rate for Panel#11 -$Seamless_DRRS_Min_RR_12 1 byte ; Seamless DRRS Min Refresh Rate for Panel#12 -$Seamless_DRRS_Min_RR_13 1 byte ; Seamless DRRS Min Refresh Rate for Panel#13 -$Seamless_DRRS_Min_RR_14 1 byte ; Seamless DRRS Min Refresh Rate for Panel#14 -$Seamless_DRRS_Min_RR_15 1 byte ; Seamless DRRS Min Refresh Rate for Panel#15 -$Seamless_DRRS_Min_RR_16 1 byte ; Seamless DRRS Min Refresh Rate for Panel#16 - - -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - - ; Flat Panel #1 -$BLC_Inv_Type_1 2 bits ; BLC inverter type -$BLC_Inv_Polarity_1 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_1 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_1 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_1 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_1 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_1 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_1 1 byte ; I2C inverter command code - - - ; Flat Panel #2 -$BLC_Inv_Type_2 2 bits ; BLC inverter type -$BLC_Inv_Polarity_2 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_2 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_2 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_2 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_2 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_2 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_2 1 byte ; I2C inverter command code - - ; Flat Panel #3 -$BLC_Inv_Type_3 2 bits ; BLC inverter type -$BLC_Inv_Polarity_3 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_3 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_3 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_3 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_3 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_3 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_3 1 byte ; I2C inverter command code - - - ; Flat Panel #4 -$BLC_Inv_Type_4 2 bits ; BLC inverter type -$BLC_Inv_Polarity_4 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_4 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_4 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_4 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_4 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_4 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_4 1 byte ; I2C inverter command code - - ; Flat Panel #5 -$BLC_Inv_Type_5 2 bits ; BLC inverter type -$BLC_Inv_Polarity_5 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_5 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_5 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_5 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_5 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_5 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_5 1 byte ; I2C inverter command code - - - ; Flat Panel #6 -$BLC_Inv_Type_6 2 bits ; BLC inverter type -$BLC_Inv_Polarity_6 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_6 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_6 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_6 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_6 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_6 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_6 1 byte ; I2C inverter command code - - ; Flat Panel #7 -$BLC_Inv_Type_7 2 bits ; BLC inverter type -$BLC_Inv_Polarity_7 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_7 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_7 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_7 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_7 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_7 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_7 1 byte ; I2C inverter command code - - - ; Flat Panel #8 -$BLC_Inv_Type_8 2 bits ; BLC inverter type -$BLC_Inv_Polarity_8 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_8 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_8 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_8 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_8 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_8 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_8 1 byte ; I2C inverter command code - - - ; Flat Panel #9 -$BLC_Inv_Type_9 2 bits ; BLC inverter type -$BLC_Inv_Polarity_9 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_9 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_9 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_9 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_9 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_9 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_9 1 byte ; I2C inverter command code - - ; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - - - ; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - - - ; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - - ; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - - - ; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - - - ; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - - - ; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #1 - $POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #2 - $POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #3 - $POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #4 - $POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #5 - $POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #6 - $POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #7 - $POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #8 - $POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #9 - $POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 - $POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 - $POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 - $POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 - $POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 - $POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 - $POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - - $Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 - $Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - - $Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 - $Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - - $Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 - $Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - - $Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 - $Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - - $Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 - $Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - - $Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 - $Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - - $Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 - $Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - - $Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 - $Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - - $Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 - $Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - - $Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 - $Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - - $Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 - $Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - - $Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 - $Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - - $Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 - $Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - - $Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 - $Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - - $Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 - $Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - - $Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 - $Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$BIA_Enable 1 bit ; DPST support enable bit -$BIA_Aggress_Level 3 bits ; Power Conservation Preference level -SKIP 3 bits ; Reserved -$ALS_Enable 1 bit ; ALS enable bit -$ALS_Response_Data 20 bytes ; ALS Response Data - - ;============================================================================== - ; Block 46 - Chromaticity Support - ;------------------------------------------------------------------------------ - - SKIP 3 bytes ; Skip block ID and size - - - $Chromacity_Enable_1 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_1 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_1 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_1 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_1 1 byte ; Red x coordinate at 1Bh - $Red_y_1 1 byte ; Red y coordinate at 1Ch - $Green_x_1 1 byte ; Green x coordinate at 1Dh - $Green_y_1 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_1 1 byte ; Blue x coordinate at 1Fh - $Blue_y_1 1 byte ; Blue y coordinate at 20h - $White_x_1 1 byte ; White x coordiante at 21h - $White_y_1 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_2 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_2 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_2 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_2 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_2 1 byte ; Red x coordinate at 1Bh - $Red_y_2 1 byte ; Red y coordinate at 1Ch - $Green_x_2 1 byte ; Green x coordinate at 1Dh - $Green_y_2 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_2 1 byte ; Blue x coordinate at 1Fh - $Blue_y_2 1 byte ; Blue y coordinate at 20h - $White_x_2 1 byte ; White x coordiante at 21h - $White_y_2 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_3 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_3 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_3 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_3 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_3 1 byte ; Red x coordinate at 1Bh - $Red_y_3 1 byte ; Red y coordinate at 1Ch - $Green_x_3 1 byte ; Green x coordinate at 1Dh - $Green_y_3 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_3 1 byte ; Blue x coordinate at 1Fh - $Blue_y_3 1 byte ; Blue y coordinate at 20h - $White_x_3 1 byte ; White x coordiante at 21h - $White_y_3 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_4 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_4 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_4 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_4 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_4 1 byte ; Red x coordinate at 1Bh - $Red_y_4 1 byte ; Red y coordinate at 1Ch - $Green_x_4 1 byte ; Green x coordinate at 1Dh - $Green_y_4 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_4 1 byte ; Blue x coordinate at 1Fh - $Blue_y_4 1 byte ; Blue y coordinate at 20h - $White_x_4 1 byte ; White x coordiante at 21h - $White_y_4 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_5 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_5 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_5 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_5 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_5 1 byte ; Red x coordinate at 1Bh - $Red_y_5 1 byte ; Red y coordinate at 1Ch - $Green_x_5 1 byte ; Green x coordinate at 1Dh - $Green_y_5 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_5 1 byte ; Blue x coordinate at 1Fh - $Blue_y_5 1 byte ; Blue y coordinate at 20h - $White_x_5 1 byte ; White x coordiante at 21h - $White_y_5 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_6 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_6 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_6 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_6 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_6 1 byte ; Red x coordinate at 1Bh - $Red_y_6 1 byte ; Red y coordinate at 1Ch - $Green_x_6 1 byte ; Green x coordinate at 1Dh - $Green_y_6 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_6 1 byte ; Blue x coordinate at 1Fh - $Blue_y_6 1 byte ; Blue y coordinate at 20h - $White_x_6 1 byte ; White x coordiante at 21h - $White_y_6 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_7 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_7 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_7 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_7 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_7 1 byte ; Red x coordinate at 1Bh - $Red_y_7 1 byte ; Red y coordinate at 1Ch - $Green_x_7 1 byte ; Green x coordinate at 1Dh - $Green_y_7 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_7 1 byte ; Blue x coordinate at 1Fh - $Blue_y_7 1 byte ; Blue y coordinate at 20h - $White_x_7 1 byte ; White x coordiante at 21h - $White_y_7 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_8 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_8 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_8 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_8 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_8 1 byte ; Red x coordinate at 1Bh - $Red_y_8 1 byte ; Red y coordinate at 1Ch - $Green_x_8 1 byte ; Green x coordinate at 1Dh - $Green_y_8 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_8 1 byte ; Blue x coordinate at 1Fh - $Blue_y_8 1 byte ; Blue y coordinate at 20h - $White_x_8 1 byte ; White x coordiante at 21h - $White_y_8 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_9 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_9 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_9 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_9 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_9 1 byte ; Red x coordinate at 1Bh - $Red_y_9 1 byte ; Red y coordinate at 1Ch - $Green_x_9 1 byte ; Green x coordinate at 1Dh - $Green_y_9 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_9 1 byte ; Blue x coordinate at 1Fh - $Blue_y_9 1 byte ; Blue y coordinate at 20h - $White_x_9 1 byte ; White x coordiante at 21h - $White_y_9 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_10 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_10 1 byte ; Red x coordinate at 1Bh - $Red_y_10 1 byte ; Red y coordinate at 1Ch - $Green_x_10 1 byte ; Green x coordinate at 1Dh - $Green_y_10 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_10 1 byte ; Blue x coordinate at 1Fh - $Blue_y_10 1 byte ; Blue y coordinate at 20h - $White_x_10 1 byte ; White x coordiante at 21h - $White_y_10 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_11 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_11 1 byte ; Red x coordinate at 1Bh - $Red_y_11 1 byte ; Red y coordinate at 1Ch - $Green_x_11 1 byte ; Green x coordinate at 1Dh - $Green_y_11 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_11 1 byte ; Blue x coordinate at 1Fh - $Blue_y_11 1 byte ; Blue y coordinate at 20h - $White_x_11 1 byte ; White x coordiante at 21h - $White_y_11 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_12 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_12 1 byte ; Red x coordinate at 1Bh - $Red_y_12 1 byte ; Red y coordinate at 1Ch - $Green_x_12 1 byte ; Green x coordinate at 1Dh - $Green_y_12 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_12 1 byte ; Blue x coordinate at 1Fh - $Blue_y_12 1 byte ; Blue y coordinate at 20h - $White_x_12 1 byte ; White x coordiante at 21h - $White_y_12 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_13 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_13 1 byte ; Red x coordinate at 1Bh - $Red_y_13 1 byte ; Red y coordinate at 1Ch - $Green_x_13 1 byte ; Green x coordinate at 1Dh - $Green_y_13 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_13 1 byte ; Blue x coordinate at 1Fh - $Blue_y_13 1 byte ; Blue y coordinate at 20h - $White_x_13 1 byte ; White x coordiante at 21h - $White_y_13 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_14 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_14 1 byte ; Red x coordinate at 1Bh - $Red_y_14 1 byte ; Red y coordinate at 1Ch - $Green_x_14 1 byte ; Green x coordinate at 1Dh - $Green_y_14 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_14 1 byte ; Blue x coordinate at 1Fh - $Blue_y_14 1 byte ; Blue y coordinate at 20h - $White_x_14 1 byte ; White x coordiante at 21h - $White_y_14 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_15 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_15 1 byte ; Red x coordinate at 1Bh - $Red_y_15 1 byte ; Red y coordinate at 1Ch - $Green_x_15 1 byte ; Green x coordinate at 1Dh - $Green_y_15 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_15 1 byte ; Blue x coordinate at 1Fh - $Blue_y_15 1 byte ; Blue y coordinate at 20h - $White_x_15 1 byte ; White x coordiante at 21h - $White_y_15 1 byte ; White y coordinate at 22h - - - $Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_16 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_16 1 byte ; Red x coordinate at 1Bh - $Red_y_16 1 byte ; Red y coordinate at 1Ch - $Green_x_16 1 byte ; Green x coordinate at 1Dh - $Green_y_16 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_16 1 byte ; Blue x coordinate at 1Fh - $Blue_y_16 1 byte ; Blue y coordinate at 20h - $White_x_16 1 byte ; White x coordiante at 21h - $White_y_16 1 byte ; White y coordinate at 22h - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Feature_Enable 1 byte ; enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -;============================================================================== -; Block 52 - MIPI DSI Configuration Block -;----------------------------------------------------------------------------- - -$MIPI_DSI_CONF_BLOCKID 1 byte -$MIPI_DSI_CONF_BLOCKSIZE 2 bytes - - ;MIPI DSI CONF Panel#1 -$PanelIdentifier_1 2 bytes ;PanelIdentifier - -$Dithering_1 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_1 1 bit -$MIPI_DSI_Panel_Architecture_Type_1 2 bits -$Video_Command_Mode_1 1 bit -$Packet_Sequence_Video_Mode_1 2 bits -$CABC_Support_1 1 bit -$PmicSocSelection_1 1 bit -$Colour_Format_Video_Mode_1 4 bits -$Panel_Rotation_1 2 bits -$Bta_Disable_1 1 bit -SKIP 15 bits - -$Dual_Link_1 2 bits ;PortDesc -$Number_Of_Lanes_1 2 bits -$Pixel_Overlap_Count_1 3 bits -$RGBFlip_1 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_1 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_1 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_1 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_1 1 bit ;DphyFlags -$EoTpSupport_1 1 bit ;EoTpSupport -$ClockStop_1 1 bit -SKIP 13 bits - -$HsTxTimeOut_1 4 bytes ;HsTxTimeOut -$LpRxTimeOut_1 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_1 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_1 4 bytes ;DeviceResetTimer -$MasterInitTimer_1 4 bytes ;MasterInitTimer -$DbiBwTimer_1 32 bits ;DbiBwTimer - -$LpByteClkRegValue_1 32 bits ;LpByteClkRegValue -$DphyParamRegValue_1 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_1 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_1 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_1 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_1 1 byte ;TClkTrail -$TClkPrepareTClkZero_1 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_1 1 byte ;THsPrepare -$THsPrepareTHsZero_1 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_1 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_1 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_1 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_1 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_1 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_1 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_1 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#2 -$PanelIdentifier_2 2 bytes ;PanelIdentifier - -$Dithering_2 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_2 1 bit -$MIPI_DSI_Panel_Architecture_Type_2 2 bits -$Video_Command_Mode_2 1 bit -$Packet_Sequence_Video_Mode_2 2 bits -$CABC_Support_2 1 bit -$PmicSocSelection_2 1 bit -$Colour_Format_Video_Mode_2 4 bits -$Panel_Rotation_2 2 bits -$Bta_Disable_2 1 bit -SKIP 15 bits - -$Dual_Link_2 2 bits ;PortDesc -$Number_Of_Lanes_2 2 bits -$Pixel_Overlap_Count_2 3 bits -$RGBFlip_2 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_2 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_2 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_2 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_2 1 bit ;DphyFlags -$EoTpSupport_2 1 bit ;EoTpSupport -$ClockStop_2 1 bit -SKIP 13 bits - -$HsTxTimeOut_2 4 bytes ;HsTxTimeOut -$LpRxTimeOut_2 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_2 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_2 4 bytes ;DeviceResetTimer -$MasterInitTimer_2 4 bytes ;MasterInitTimer -$DbiBwTimer_2 32 bits ;DbiBwTimer - -$LpByteClkRegValue_2 32 bits ;LpByteClkRegValue -$DphyParamRegValue_2 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_2 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_2 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_2 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_2 1 byte ;TClkTrail -$TClkPrepareTClkZero_2 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_2 1 byte ;THsPrepare -$THsPrepareTHsZero_2 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_2 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_2 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_2 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_2 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_2 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_2 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_2 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#3 -$PanelIdentifier_3 2 bytes ;PanelIdentifier - -$Dithering_3 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_3 1 bit -$MIPI_DSI_Panel_Architecture_Type_3 2 bits -$Video_Command_Mode_3 1 bit -$Packet_Sequence_Video_Mode_3 2 bits -$CABC_Support_3 1 bit -$PmicSocSelection_3 1 bit -$Colour_Format_Video_Mode_3 4 bits -$Panel_Rotation_3 2 bits -$Bta_Disable_3 1 bit -SKIP 15 bits - -$Dual_Link_3 2 bits ;PortDesc -$Number_Of_Lanes_3 2 bits -$Pixel_Overlap_Count_3 3 bits -$RGBFlip_3 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_3 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_3 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_3 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_3 1 bit ;DphyFlags -$EoTpSupport_3 1 bit ;EoTpSupport -$ClockStop_3 1 bit -SKIP 13 bits - -$HsTxTimeOut_3 4 bytes ;HsTxTimeOut -$LpRxTimeOut_3 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_3 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_3 4 bytes ;DeviceResetTimer -$MasterInitTimer_3 4 bytes ;MasterInitTimer -$DbiBwTimer_3 32 bits ;DbiBwTimer - -$LpByteClkRegValue_3 32 bits ;LpByteClkRegValue -$DphyParamRegValue_3 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_3 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_3 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_3 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_3 1 byte ;TClkTrail -$TClkPrepareTClkZero_3 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_3 1 byte ;THsPrepare -$THsPrepareTHsZero_3 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_3 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_3 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_3 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_3 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_3 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_3 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_3 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#4 -$PanelIdentifier_4 2 bytes ;PanelIdentifier - -$Dithering_4 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_4 1 bit -$MIPI_DSI_Panel_Architecture_Type_4 2 bits -$Video_Command_Mode_4 1 bit -$Packet_Sequence_Video_Mode_4 2 bits -$CABC_Support_4 1 bit -$PmicSocSelection_4 1 bit -$Colour_Format_Video_Mode_4 4 bits -$Panel_Rotation_4 2 bits -$Bta_Disable_4 1 bit -SKIP 15 bits - -$Dual_Link_4 2 bits ;PortDesc -$Number_Of_Lanes_4 2 bits -$Pixel_Overlap_Count_4 3 bits -$RGBFlip_4 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_4 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_4 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_4 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_4 1 bit ;DphyFlags -$EoTpSupport_4 1 bit ;EoTpSupport -$ClockStop_4 1 bit -SKIP 13 bits - -$HsTxTimeOut_4 4 bytes ;HsTxTimeOut -$LpRxTimeOut_4 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_4 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_4 4 bytes ;DeviceResetTimer -$MasterInitTimer_4 4 bytes ;MasterInitTimer -$DbiBwTimer_4 32 bits ;DbiBwTimer - -$LpByteClkRegValue_4 32 bits ;LpByteClkRegValue -$DphyParamRegValue_4 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_4 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_4 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_4 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_4 1 byte ;TClkTrail -$TClkPrepareTClkZero_4 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_4 1 byte ;THsPrepare -$THsPrepareTHsZero_4 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_4 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_4 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_4 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_4 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_4 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_4 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_4 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#5 -$PanelIdentifier_5 2 bytes ;PanelIdentifier - -$Dithering_5 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_5 1 bit -$MIPI_DSI_Panel_Architecture_Type_5 2 bits -$Video_Command_Mode_5 1 bit -$Packet_Sequence_Video_Mode_5 2 bits -$CABC_Support_5 1 bit -$PmicSocSelection_5 1 bit -$Colour_Format_Video_Mode_5 4 bits -$Panel_Rotation_5 2 bits -$Bta_Disable_5 1 bit -SKIP 15 bits - -$Dual_Link_5 2 bits ;PortDesc -$Number_Of_Lanes_5 2 bits -$Pixel_Overlap_Count_5 3 bits -$RGBFlip_5 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_5 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_5 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_5 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_5 1 bit ;DphyFlags -$EoTpSupport_5 1 bit ;EoTpSupport -$ClockStop_5 1 bit -SKIP 13 bits - -$HsTxTimeOut_5 4 bytes ;HsTxTimeOut -$LpRxTimeOut_5 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_5 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_5 4 bytes ;DeviceResetTimer -$MasterInitTimer_5 4 bytes ;MasterInitTimer -$DbiBwTimer_5 32 bits ;DbiBwTimer - -$LpByteClkRegValue_5 32 bits ;LpByteClkRegValue -$DphyParamRegValue_5 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_5 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_5 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_5 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_5 1 byte ;TClkTrail -$TClkPrepareTClkZero_5 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_5 1 byte ;THsPrepare -$THsPrepareTHsZero_5 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_5 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_5 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_5 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_5 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_5 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_5 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_5 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#6 -$PanelIdentifier_6 2 bytes ;PanelIdentifier - -$Dithering_6 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_6 1 bit -$MIPI_DSI_Panel_Architecture_Type_6 2 bits -$Video_Command_Mode_6 1 bit -$Packet_Sequence_Video_Mode_6 2 bits -$CABC_Support_6 1 bit -$PmicSocSelection_6 1 bit -$Colour_Format_Video_Mode_6 4 bits -$Panel_Rotation_6 2 bits -$Bta_Disable_6 1 bit -SKIP 15 bits - -$Dual_Link_6 2 bits ;PortDesc -$Number_Of_Lanes_6 2 bits -$Pixel_Overlap_Count_6 3 bits -$RGBFlip_6 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_6 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_6 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_6 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_6 1 bit ;DphyFlags -$EoTpSupport_6 1 bit ;EoTpSupport -$ClockStop_6 1 bit -SKIP 13 bits - -$HsTxTimeOut_6 4 bytes ;HsTxTimeOut -$LpRxTimeOut_6 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_6 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_6 4 bytes ;DeviceResetTimer -$MasterInitTimer_6 4 bytes ;MasterInitTimer -$DbiBwTimer_6 32 bits ;DbiBwTimer - -$LpByteClkRegValue_6 32 bits ;LpByteClkRegValue -$DphyParamRegValue_6 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_6 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_6 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_6 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_6 1 byte ;TClkTrail -$TClkPrepareTClkZero_6 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_6 1 byte ;THsPrepare -$THsPrepareTHsZero_6 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_6 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_6 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_6 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_6 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_6 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_6 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_6 1 bit ;StbyRN -SKIP 7 bits - - ; MIPI DSI PPS for Panel#1 -$PowerUpDelay_1 16 bits -$DataTurnOnToPanelBacklightEnableDelay_1 16 bits -$BacklightOffToDataTurnOffDelay_1 16 bits -$PowerDownDelay_1 16 bits -$PowerCycleDelay_1 16 bits - - ; MIPI DSI PPS for Panel#2 -$PowerUpDelay_2 16 bits -$DataTurnOnToPanelBacklightEnableDelay_2 16 bits -$BacklightOffToDataTurnOffDelay_2 16 bits -$PowerDownDelay_2 16 bits -$PowerCycleDelay_2 16 bits - - ; MIPI DSI PPS for Panel#3 -$PowerUpDelay_3 16 bits -$DataTurnOnToPanelBacklightEnableDelay_3 16 bits -$BacklightOffToDataTurnOffDelay_3 16 bits -$PowerDownDelay_3 16 bits -$PowerCycleDelay_3 16 bits - - ; MIPI DSI PPS for Panel#4 -$PowerUpDelay_4 16 bits -$DataTurnOnToPanelBacklightEnableDelay_4 16 bits -$BacklightOffToDataTurnOffDelay_4 16 bits -$PowerDownDelay_4 16 bits -$PowerCycleDelay_4 16 bits - - ; MIPI DSI PPS for Panel#5 -$PowerUpDelay_5 16 bits -$DataTurnOnToPanelBacklightEnableDelay_5 16 bits -$BacklightOffToDataTurnOffDelay_5 16 bits -$PowerDownDelay_5 16 bits -$PowerCycleDelay_5 16 bits - - ; MIPI DSI PPS for Panel#6 -$PowerUpDelay_6 16 bits -$DataTurnOnToPanelBacklightEnableDelay_6 16 bits -$BacklightOffToDataTurnOffDelay_6 16 bits -$PowerDownDelay_6 16 bits -$PowerCycleDelay_6 16 bits - -$Mipi_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 -$Mipi_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 -$Mipi_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 -$Mipi_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 -$Mipi_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 -$Mipi_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 -$Mipi_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 - -$Mipi_PmicI2cBusNo_1 1 byte -$Mipi_PmicI2cBusNo_2 1 byte -$Mipi_PmicI2cBusNo_3 1 byte -$Mipi_PmicI2cBusNo_4 1 byte -$Mipi_PmicI2cBusNo_5 1 byte -$Mipi_PmicI2cBusNo_6 1 byte - -EndStruct - - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -List &Cls_After_Signon_List - Selection 0x00, "No CLS" - Selection 0x01, "0.5 Second Delay + CLS" - Selection 0x02, "1.0 Second Delay + CLS" - Selection 0x03, "1.5 Second Delay + CLS" - Selection 0x04, "2.0 Second Delay + CLS" - Selection 0x05, "2.5 Second Delay + CLS" - Selection 0x06, "3.0 Second Delay + CLS" - Selection 0x07, "3.5 Second Delay + CLS" -EndList - -List &Int_CRT_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x0001, "CRT" - ;Selection 0x0011, "DVI with CRT" -EndList - -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "DisplayPort" - Selection 0x60D2, "HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" - Selection 0x60D6, "DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "DisplayPort with DVI Compatible" - ; Selection 0x68D3, "DVI with CRT" -EndList - -List &CRT_Device_Id_List - Selection 01h, "CRT" -EndList - -List &EFP1_Device_Id_List - Selection 04h, "EFP 1" - Selection 40h, "EFP 2" - Selection 08h, "LFP" - ;Selection 80h, "LFP 2" -EndList - -List &EFP2_Device_Id_List - Selection 04h, "EFP 1" - Selection 40h, "EFP 2" - Selection 08h, "LFP" - ;Selection 80h, "LFP 2" -EndList - -List &LVDS_Device_Id_List - Selection 08h, "LFP" -EndList - -List &DOS_Boot_Mode_List - Selection 0x03, "03h" - Selection 0x12, "12h" - Selection 0x13, "13h" - Selection 0x30, "30h" - Selection 0x32, "32h" - Selection 0x34, "34h" - Selection 0x40, "40h" - Selection 0x41, "41h" - Selection 0x42, "42h" - Selection 0x43, "43h" - Selection 0x44, "44h" - Selection 0x45, "45h" - Selection 0x50, "50h" - Selection 0x52, "52h" - Selection 0x54, "54h" -EndList - -List &LFP_Port_List - Selection 0x07, "eDP Port B" - Selection 0x08, "eDP Port C" - ; Selection 0x15, "MIPI Port A" - ;Selection 0x17, "MIPI Port C" - -EndList - -List &LVDS_eDP_Port_List - Selection 0x04, "LVDS" - Selection 0x07, "Port B" - Selection 0x08, "Port C" -EndList - - - -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "Port B" - Selection 0x02, "Port C" - Selection 0x03, "Port D" - -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x10, "eDP-B AUX Channel" - Selection 0x20, "eDP-C AUX Channel" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x10, "DisplayPort-B AUX Channel" - Selection 0x20, "DisplayPort-C AUX Channel" - Selection 0x30, "DisplayPort-D AUX Channel" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" - Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" - Selection 0x03, "Integrated HDMI-D DDC GPIO Pins" ; as mentioned in CHV Bspec - Selection 0x01, "I2C GPIO pins" -; Selection 0x02, "Analog CRT DDC GPIO pins" -EndList - - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x01, "I2C" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &IntXXh_List - Selection 0x00, "Disabled" - Selection 0x01, "Use Interrupt 15h" -EndList - -List &LVDS_Channel_List - Selection 0x00, "Single Channel" - Selection 0x01, "Dual Channel" -EndList - -List &INT_LVDS_Channel_List - Selection 0x00, "Automatic Selection" - Selection 0x01, "Single Channel" - Selection 0x02, "Dual Channel" -EndList - -List &LVDS_Config_List - Selection 0x00, "No Device" - Selection 0x1020, "LVDS" -EndList - -List &eDP_Config_List - Selection 0x00, "No Device" - Selection 0x1806, "eDP" - ; Selection 0x1400, "MIPI" -EndList - -List &eDP_LVDS_Config_List - Selection 0x00, "No Device" - Selection 0x1020, "LVDS" - Selection 0x1806, "eDP" -EndList - - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &OS_DriverP_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Persistence Algorithm" -EndList - -List &Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &eDP_Link_PreEmp_List - Selection 0x00, "Level 0" - Selection 0x01, "Level 1" - Selection 0x02, "Level 2" - Selection 0x03, "Level 3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Level 0" - Selection 0x01, "Level 1" - Selection 0x02, "Level 2" - Selection 0x03, "Level 3" -EndList - - -List &Panel_Connector_List - Selection 0x00, "SPGW" - Selection 0x01, "OpenLDI" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" -EndList - - -List &Panel_Stretch_List - Selection 0x00, "Disable Panel Fitting" - Selection 0x01, "Enabled for Text Modes Only" - Selection 0x02, "Enabled for Graphics Modes Only" - Selection 0x03, "Enabled for Both Text and Graphics Modes" -EndList - -List &PCI_BIOS_Disabled_Enabled_List - Selection 0x00, "Disabled" - Selection 0x01, "Resize to 0.5K boundary" - Selection 0x20, "Resize to 16K boundary" -EndList - -List &RelStage - Selection 1, "Production" - Selection 254, "Evaluation" -EndList - -List &Power_Scheme_List - Selection 0, "CUI" - Selection 1, "3rd Party Application" -EndList - -List &Render_Freq_List - Selection 0, "High Frequency" - Selection 1, "Low Frequency" -EndList - -List &SSC_List - Selection 0, "96 MHz" - Selection 1, "100 MHz" -EndList - -List &SDVO_Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Sprite_Display_List - Selection 0, "Secondary Display" - Selection 1, "Primary Display" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &Inter_Exter_List - Selection 0, "External Termination" - Selection 1, "Internal Termination" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &MSA_TimingDelay_List - Selection 0x00, "Line 1" - Selection 0x01, "Line 2" - Selection 0x02, "Line 3" - Selection 0x03, "Line 4" -EndList - -List &Blt_Control_Type_List - ;Selection 0x00, "Default" - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - - -List &Mode_Preferred_List - Selection 0x00, "Mode Timing" - Selection 0x01, "Preferred Timing" -EndList - -List &DisplayList - Selection 0x08, "LFP" - ;Selection 0x80, "LFP 2" - ;Selection 0x01, "CRT" - Selection 0x04, "EFP 1" - Selection 0x40, "EFP 2" - Selection 0x20, "EFP 3" - Selection 0x00, "None" -EndList - -List &Dither_Select_Bit - Selection 0, "Dithering in Panel controller" - Selection 1, "Dithering in Display Controller" -EndList - -List &MIPI_Bridge_Ref_Clock_List - Selection 0, "19.2" - Selection 1, "26" -EndList - -List &Panel_Identifier_List - Selection 0x0, "Use Sequence Block" - Selection 0x1, "MIPI DSI Panel-1" - Selection 0x2, "MIPI DSI Panel-2" - Selection 0x3, "MIPI DSI Panel-3" - Selection 0x4, "MIPI DSI Panel-4" - Selection 0x5, "MIPI DSI Panel-5" - Selection 0x6, "MIPI DSI Panel-6" - Selection 0x7, "MIPI DSI Panel-7" - Selection 0x8, "MIPI DSI Panel-8" - ;Selection 0x9, "MIPI DSI Panel-9" - ;Selection 0xA, "MIPI DSI Panel-10" - ;Selection 0xB, "MIPI DSI Panel-11" - ;Selection 0xC, "MIPI DSI Panel-12" - ;Selection 0xD, "MIPI DSI Panel-13" - ;Selection 0xE, "MIPI DSI Panel-14" - ;Selection 0xF, "MIPI DSI Panel-15" - ;Selection 0x10, "MIPI DSI Panel-16" -EndList - -List &Panel_Type_List - Selection 0, "Native MIPI DSI" - Selection 1, "MIPI DSI to LVDS Bridge" -EndList - -List &MIPI_DSI_Panel_Architecture_Type_List - Selection 0x0, "Type 1" - Selection 0x1, "Type 2" - Selection 0x2, "Type 3" - Selection 0x3, "Type 4" -EndList - -List &Video_Command_Mode_List - Selection 0, "Video Mode" - Selection 1, "Command Mode" -EndList - -List &Packet_Sequence_Video_Mode_List - ;Selection 0x0, "Reserved" - Selection 0x1, "Non-burst with sync pulse" - Selection 0x2, "Non-burst with sync events" - Selection 0x3, "Burst Mode" -EndList - -List &Colour_Format_Video_Mode_List - Selection 0x1, "RGB565" - Selection 0x2, "RGB666" - Selection 0x3, "RGB 666(Loosely Packed Format)" - Selection 0x4, "RGB888" -EndList - -List &Panel_Rotation_List - Selection 0x0, "0 degree" - Selection 0x1, "90 degree" - Selection 0x2, "180 degree" - Selection 0x3, "270 degree" -EndList - -List &Enable_Disable_List - Selection 0, "Enable" - Selection 1, "Disable" -EndList - -List &EscapeClk_List - Selection 0x0, "20 MHz" - Selection 0x1, "10 MHz" - Selection 0x2, "5 MHz" - ;Selection 0x3, "Undefined" -EndList - -List &DPhyParamFlag_List - Selection 0, "Dphy Param is not valid" - Selection 1, "Dphy Param is valid" -EndList - -List &MIPI_DSI_Panel_Color_Depth_List - Selection 0x0, "18Bpp" - Selection 0x1, "24Bpp" -EndList - -List &Lane_Count_List - Selection 0x0, "1" - Selection 0x1, "2" - Selection 0x2, "3" - Selection 0x3, "4" -EndList - -List &Dual_Link_List - Selection 0x0, "Dual Link Not Supported" - Selection 0x1, "Dual Link Front Back Mode" - Selection 0x2, "Dual Link Pixel Alternative Mode" - ;Selection 0x3, "Reserved" -EndList - -List &Hdmi_LS_List_CHV - Selection 0x00, "1.2V 3dB" - Selection 0x01, "1.0V 0dB" -EndList - -List &Edp_Pwm_Source_List - Selection 0x1, "LPSS PWM" - Selection 0x2, "DISPLAY PWM" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock - PPVer "2.01" - Image EOF Thru EOF At EOF -EndInfoBlock - - -;============================================================================== -; Page - VBT version -;------------------------------------------------------------------------------ - -Page "VBT version" - - Title "PLATFORM : CherryView" - Title "VBT version: 195" - -EndPage ; VBT version - - - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ - -Page "UEFI GOP Driver Configuration" - - ;Combo $Hotplug_Support_Enb, " Hot Plug Support:", &Disabled_Enabled_List, - ;Help "This feature is to enable/disable Hot Plug Suppport for CRT/DP/HDMI displays " - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Boot Display Algorithm - ;------------------------------------------------------------------------------ - - Page "Child Device List" - - Title "Select the child devices that the GOP driver should enumerate if detected." - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify " - "the child device to start, then GOP driver selects the highest priority child device" - - Link "Close Window", ".." - - Title "Child Device 1" - Combo $ChildDevice1Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - EndPage ;"Child Device List" - -;============================================================================ -; Page - Fixed Mode Configuration -;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set.\r\n" - "This field specifies if user wants to enable/disable the feature.\r\n" - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode. It should be always less than or equal to the native horizontal resolution.\r\n" - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode. It should be always less than or equal to the native vertical resolution.\r\n" - - EndPage -EndPage ; "UEFI GOP Driver Configuration" - - - -;============================================================================ -; Page - Windows Graphics Driver Configuration -;---------------------------------------------------------------------------- - -Page "Windows Graphics Driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, " VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version " - "number. The permissible values for VBT Customization version " - "is from 0 to 255.\r\n" - - Combo $Driver_Boot_Device, " First Boot Display Device:", &OS_Driver_List, - Help "This feature allows the OEM to select which algorithm to " - "follow on the first boot after the driver has been " - "installed.\r\n" - "\r\n" - "OS Default - If this is selected, the operating system's " - "algorithm will be used.\r\n" - "\r\n" - "Driver Default - If this is selected, the boot device will " - "follow the driver algorithm. The expected behavior can be " - "found in the Driver PRD chapter: 'First Boot Default " - "Display Resolutions'." - - ;Combo $Allow_FDOS_Disp_Switch, " Allow Full Screen DOS Display Switching:", &No_Yes_List, - ;Help "This feature allows display switching when the system is in " - ; "full screen DOS. When set to yes, display switching will be " - ; "allowed while system is in full screen DOS. When set to no, " - ; "display switching will be blocked when system is in full " - ;"screen DOS." - - ;Combo $Hot_Plug_DVO, " DVO/SDVO Hot Plug:", &Disabled_Enabled_List, - ;Help "This feature allows the OEM to disable the DVO/SDVO Hot Plug " - ; "capability." - - - Combo $Use_110h_for_LFP, " Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List, - Help "This feature when set to yes will use the legacy value " - "00000110h as the ID for primary LFP in the ACPI _DOD, _DGS " - "method. The ID is passed to the system BIOS through INT10h function 5F64h " - "The ID 00000110h is the backwards compatible ACPI ID " - "for LFP, which may be necessary in where Microsoft* WindowsXP " - "TabletPC*'s Graphical User Interface is required for Backlight " - "Control(hardcoded by some Windows OSes). In all other cases, " - "the default new ID is strongly preferred." - - - ;Combo $DVD_Sprite_Clone, " Disable Sprite (DVD) in Clone Mode:", &Yes_No_List, - ;Help "This feature when selected 'No', will allow the sprite to be " - ; "active during DVD playback when the platform is in a Dual " - ; "Display Clone configuration. Otherwise, when selected 'Yes', " - ; "the overlay sprite will be disabled during DVD playback when the " - ; "platform is in a Dual Display Clone configuration." - - Combo $GTF_Mode_Pruning, " Selective Mode Pruning:", &Disabled_Enabled_List, - Help "This feature when enabled will instruct driver software not " - "to enumerate or set specific display modes determined as " - "unsupported according to the EDID capabilities of the " - "display. If the display indicates support for all GTF/DMTS " - "timings in the display's EDID, then all modes supported by " - "the graphics host will be enumerated. If the display does " - "NOT indicate support for GTF/DMTS timings in the display's " - "EDID, then some modes/timings that may have been enumerated " - "by the display driver shall not be set." - "\r\n" - "\r\n" - "Note: This option applies for all display types. And in the " - "absence of other platform configuration information (e.g. " - "OEM Customizable Mode) requiring inclusion of that display " - "mode/timings." - - ;Combo $Sprite_Display_Assign, " Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_List, - ;Help "This feature when set to Primary Display, the driver will " - ; "assign the Sprite (2ndary overlay) to the primary display " - ; "defined in the current Dual Display Clone configuration, " - ; "otherwise when this feature is set to Secondary Display, the " - ;"driver will assign the Sprite (2ndary overlay) to the " - ;"secondary display defined in the current Dual Display Clone " - ;"configuration. Note: This bit will have no affect if an " - ;"application is using the VMR API. " - - - - Combo $CUIHotK_Static_Display, " Display must be attached for CUI/Hot Key:", &Yes_No_List, - Help "This feature allows a selectable option to determine whether " - "the display device must be attached for CUI Hot Key.\r\n" - "\r\n" - "With the 'No' option the display devices do not have to be " - "attached when enabling the displays via CUI Devices Pages, " - "CUI Hot Key. Note: This feature may cause the user to have " - "a blank display device due to switching to a display that is " - "not attached.\r\n" - "\r\n" - "With the 'Yes' option the display device must be attached or " - "the display switch attempt will be blocked." - EndPage - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, " Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain " - "Aspect Ratio' feature. When the option is set to Yes, the " - "feature will be enabled and CUI will show for end user " - "selection 'Maintain Aspect Ratio'. When the option is set to " - "No, the complete 'Maintain Aspect Ratio' feature will be disabled." - - Combo $Preserve_Aspect_Ratio, " Preserve Aspect Ratio:", &Disabled_Enabled_List, - Help "This feature allows the OEM to configure the default option " - "for aspect ratio settings. When enabled, the CUI will reflect " - "preserve the aspect ratio as active setting. Otherwise, when " - "disabled, the CUI will use the setting 'Panel Fitting Initial " - "States' as default aspect ratio setting. This option will " - "only be available for initial boot value. Any subsequent " - "change in CUI will have higher priority." - - Title " " - TitleB "Legacy Monitor Mode Limit" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is " - "specified by a maximum number of horizontal active pixels." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is " - "specified by a maximum number of vertical active pixels." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - - Title " " - TitleB "Rotation Support Configuration" - - - Combo $Rotation_Support_Enable, "Support Rotation Feature:", &No_Yes_List, - Help "This feature when set to yes, can cause the graphics driver to " - "support rotation feature, otherwise rotation feature support " - "will be disabled." - "\r\n" - "Note: Setting this field to Yes is a necessary condition for driver to " - "support rotation feature, but it is not sufficient." - - - Title " " - TitleB "Graphics Mode to Boot on Windows" - - - EditNum $Driver_Boot_Mode_X, " X Resolution (Pixels):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "X Resolution (Pixels)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_Y, " Y Resolution (Pixels):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Y Resolution (Pixels)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_BPP, " Color Depth (Bits/Pixel):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Color Depth (BPP)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_RR, " Refresh Rate (Hz):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Refresh Rate (Hz)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." -Title " " -TitleB "TV features" - - Combo $Under_Over_Scan_Via_YPrPb, " Enable underscanned modes for HDTV via Component (YPrPb):", &Under_Over_List, - Help "For 720p format when enable underscan and overscan modes " - "option is selected, expose 1184x666 and 1280x720 through CUI" - "\r\n" - "For 1080i format when enable underscan and overscan modes " - "option is selected, expose 1776x1080 and 1920x1080 through CUI" - - Combo $Under_Over_Scan_Via_DVI, " Enable underscanned modes for HDTV via HDMI:", &Under_Over_List, - Help "When 720p is found in the EDID structure of the active HDMI " - "display and enable underscan modes is selected, 1184x666 will " - "be available and be centered in 720p timings when enabled. " - "\r\n" - "When 1080i or 1080p is found in the EDID structure of the " - "active DVI display and enable underscan modes is selected, " - "1776x1000 will be centered in appropriate 1080 timings. " - - Title "\r\n" - Title " Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via HDMI:" - Combo $Add_Overscan_Mode, " ", &Disabled_Enabled_List, - Help "For 1080i format, 1776x1000 will be made available in CUI " - "along with native resolution 1920x1080. For 720p format, " - "1184x666 will be made available in CUI along with native " - "resolution 1280x720. These resolutions are exposed to get the " - "HDMI image under scanned with task bar visible." - EndPage ; Display features - - - - - Page "Power Conservation" - Link "Close Table" , ".." - - ;Combo $SDVO_Device_Power_Down, " SDVO device power down:", &Disabled_Enabled_List, - ;Help "This feature powers down the SDVO device when the system is " - "running in battery mode (DC) and the corresponding display " - "not connected." - - Combo $BIA_Enable, " Intel® Display Power Saving Technology Support for the LFP:", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power " - "Savings Technology (DPST) is enabled or disabled. Intel® DPST " - "is a display power savings technology that changes the " - "intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system " - "is running in battery mode and the LFP is the only active " - "display device." - - Combo $BIA_Aggress_Level, " Power Conservation Preference Level for the LFP:", &Pwr_Pref_List, - Help "This feature defines the Intel® Display Power Saving Technology " - "aggressiveness level if and only if the feature Intel® Display Power Saving " - "Technology is enabled." - "\r\n\r\nThe following are the definitions for each level:" - "\r\n1 - Maximum Quality - shall use no DPST " - "\r\n2 - Provides the user the maximum " - "brightness for their embedded Local Flat Panel (LFP)while DPST is in use" - "\r\n3 - This level defines maximum amount of brightness with " - "minimal power savings" - "\r\n4 - This level defines an intermediate value for brightness amount" - "\r\n5 - This level defines an intermediate value for the brightness amount" - "\r\n6 - Maximum Battery - Provided the user with the minimum amount of " - "brightness capable for their LFP with the maximum power savings" - - Combo $Panel_Self_Refresh, " Panel Self Refresh (PSR):", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled. " - - Combo $PM_DRRS_Enable, " Intel ® Display Refresh Rate Switching (DRRS):", &Disabled_Enabled_List, - Help "This feature determines whether Intel ® Display Refresh Rate Switching (DRRS) is to be " - "enabled or not. " - - Combo $ALS_Enable, " Intel ® Automatic Display Brightness Support for the LFP:", &Disabled_Enabled_List, - Help "This feature determines whether Intel ® Automatic Display Brightness is to be " - "enabled. Intel ® Automatic Display Brightness adjusts the brightness of the " - "embedded Local Flat Panel (LFP) depending on the current " - "ambient light environment. When enabled, the driver and VBIOS" - " will control the backlight brightness of the LFP depending " - "on the ambient environment if and only if the LFP is the only " - "active display. When disabled, the driver and VBIOS will " - "perform no action." - - Combo $DMRRS, " Dynamic Media Refresh Rate Switching (DMRRS):", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Media Refresh Rate Switching feature is to be enabled. " - - Link "Ambient Light Response Data" , "Ambient Light Response Data" - - Page "Ambient Light Response Data" - Link "Close Table" , ".." - - Table $ALS_Response_Data " Ambient Light Response Data", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the " - "Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation " - "details such as sensor placement and optics. Up to five " - "points can be specified, where each point indicates a given " - "ambient light illuminance to display luminance mapping " - "specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light " - "illuminance (lux). A minimum of two points are required " - "(min and max)." - EndPage - - EndPage - EndPage -;============================================================================== -; Page - Display Configuration -;------------------------------------------------------------------------------ - -Page "Display Configuration" - - Link "LFP" , "LFP" - Link "EFP 1" , "EFP 1" - Link "EFP 2" , "EFP 2" - Link "EFP 3" , "EFP 3" - - TitleB "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC. " - "\r\n" - - Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC\r\n" - - - Page "LFP" - Link "Close Table", ".." - - Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration", &eDP_Config_List, - Help "This option select Device type." - - ; #IF ($Int_LFP1_Type == 0x1806) - Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_List, - Help "This feature specifies which DVO port to use for the selected LFP Device." - ;#ENDIF - - Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-Embedded DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List, - ;Help "This feature will select if the panel is primary or not. " - ;"The VLV platform has only one panel fitter. So, stretched mode will be only applicable " - ;"to primary panel . In secondary panel only native mode or " - ;"centering modes will be supported." - - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "This feature selects the Local Flat Panel (LFP) the VBIOS " - "and driver is to enable.\r\n" - "\r\n" - "Note, a valid return from the system BIOS hook 5F40h will " - "replace this default value.\r\n" - "\r\n" - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LVDS\r\n" - "\tPANEL #02: 800x600 LVDS\r\n" - "\tPANEL #03: 1024x768 LVDS\r\n" - "\tPANEL #04: 1280x1024 LVDS\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n" - "\tPANEL #07: 1600x1200 LVDS\r\n" - "\tPANEL #08: 1280x768 LVDS\r\n" - "\tPANEL #09: 1680x1050 LVDS\r\n" - "\tPANEL #10: 1920x1200 LVDS\r\n" - "\tPANEL #11: Reserved\r\n" - "\tPANEL #12: Reserved\r\n " - "\tPANEL #13: Reserved\r\n" - "\tPANEL #14: 1280x800 LVDS\r\n" - "\tPANEL #15: 1280x600 LVDS\r\n" - "\tPANEL #16: Reserved" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP " - "with an EDID. The video BIOS and drivers will load the EDID " - "and use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and other methods " - "will be used to set panel timing." - "\r\n\r\nNote: The backlight data may need to be updated." - "\r\n The option on page General" - " Features must be correct for platform." - - Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List, - Help "This feature when set to yes, will enable 180 Degree rotation " - "otherwise, the rotation functionality will be disabled." - - - EndPage - - - ;Page "CRT" - ; Link "Close Window" , ".." - - ; Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_List, - ; Help "This option select CRT Device." - - ;Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - ;Help "This feature specifies the GPIO pin pair " - ; "used as DDC bus by this device. If this device " - ; "doesn't support DDC bus, this field will be ignored." - - ;EndPage - - Page "EFP 1" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - ; "This option is used only by the GFX driver." - - Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP1_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP1_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - - EndPage - - - Page "EFP 2" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - - ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - ; "This option is used only by the GFX driver." - - Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP2_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP2_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - - - EndPage - - Page "EFP 3" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Device Type:", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - ;Combo $Int_EFP3_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - Combo $Int_EFP3_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP3_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP3_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP3_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP3_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP3_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP3_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP3_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP3_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - ; "This option is used only by the GFX driver." - - EndPage - - -EndPage - - - - -;============================================================================ -; Page - LFP Panel configuration -;---------------------------------------------------------------------------- -Page "LFP Panel configuration" - Link "Panel #1 ", "Panel #1 " - Link "Panel #2 ", "Panel #2 " - Link "Panel #3 ", "Panel #3 " - Link "Panel #4 ", "Panel #4 " - Link "Panel #5 ", "Panel #5 " - Link "Panel #6 ", "Panel #6 " - Link "Panel #7 ", "Panel #7 " - Link "Panel #8 ", "Panel #8 " - Link "Panel #9 ", "Panel #9 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - -;============================================================================== -; Page - Panel #1 (640x480) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #1 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_01, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - "lines) for this panel." - - - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_1, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_01, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_1, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_1, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_1, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_1, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_1, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_1, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_1, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_1, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_1, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_1, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_1, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_1, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - - -EndPage - -;============================================================================== -; Page - Panel #2 (800x600) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #2 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_02, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_2, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_02, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_2, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_2, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_2, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_2, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_2, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_2, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_2, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_2, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_2, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_2, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_2, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_2, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - -EndPage - - -;============================================================================== -; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #3 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_03, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_3, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_03, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_3, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_3, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_3, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_3, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_3, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_3, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_3, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_3, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_3, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_3, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_3, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_3, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - -EndPage - - -;============================================================================== -; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #4 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_04, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_4, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_04, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_4, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_4, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_4, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_4, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_4, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_4, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_4, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_4, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_4, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_4, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_4, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_4, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - -EndPage - - -;============================================================================== -; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #5 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_05, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - - Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_5, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_05, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_5, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_5, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_5, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_5, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_5, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_5, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_5, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_5, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_5, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_5, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_5, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_5, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - - -;============================================================================== -; Page - Panel #6 (1400x1050) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #6 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_06, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_6, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_06, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_6, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_6, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_6, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_6, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_6, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_6, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_6, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_6, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_6, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_6, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_6, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_6, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - - -EndPage - -; -; Panel#7 to Panel#16 are not shown in BMP UI for MIPI panels -; -#if ($Int_LFP1_Type != 0x1400) -;============================================================================== -; Page - Panel #7 (1600x1200) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #7 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_07, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_7, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_07, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_7, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_7, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_7, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_7, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_7, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_7, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_7, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_7, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_7, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_7, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_7, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_7, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage - - - -;============================================================================== -; Page - Panel #8 (1280x768) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #8 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_08, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_8, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_08, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_8, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_8, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_8, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_8, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_8, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_8, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_8, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_8, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_8, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_8, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_8, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_8, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage - -;============================================================================== -; Page - Panel #9 (1680x1050) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #9 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_09, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_9, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Support | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_09, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_9, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_9, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_9, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_9, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_9, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_9, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_9, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_9, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_9, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_9, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_9, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_9, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #10 (1920x1200) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #10 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_10, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_10, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_10, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_10, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_10, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_10, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_10, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_10, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_10, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_10, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_10, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_10, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_10, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #11 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #11 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_11, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_11, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_11, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_11, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_11, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_11, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_11, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_11, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_11, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_11, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_11, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_11, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_11, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage -;============================================================================== -; Page - Panel #12 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #12 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_12, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_12, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_12, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_12, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_12, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_12, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_12, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_12, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_12, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_12, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_12, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_12, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_12, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage -;============================================================================== -; Page - Panel #13 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #13 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_13, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_13, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_13, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_13, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_13, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_13, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_13, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_13, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_13, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_13, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_13, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_13, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_13, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #14 (1280x800) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #14 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_14, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_14, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_14, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_14, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_14, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_14, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_14, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_14, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_14, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_14, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_14, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_14, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_14, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - -;============================================================================== -; Page - Panel #15 (1280x600) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #15 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_15, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_15, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_15, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - - EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_15, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_15, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_15, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_15, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_15, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_15, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_15, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_15, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_15, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_15, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - -;============================================================================== -; Page - Panel #16 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #16 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_16, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_16, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_16, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_16, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_16, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_16, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_16, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_16, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_16, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_16, " Blue_x (Bits 9->2 at 1F)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_16, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_16, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_16, " White_y (Bits 9->2 at 22h)h" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - -EndPage -#endif - -EndPage ; "Integrated LFP Features" - - - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ - -Page "Display Device Toggle Lists" - - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 2" - - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 3" - - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 4" - - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - EndPage - -EndPage - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - Help "This feature allows removing support for selected modes " - "resolutions.\r\n" - "\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or " - "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n" - "\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = " - "Remove):\r\n" - "\r\n" - "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n" - "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n" - "\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = " - "Remove):\r\n" - "\r\n" - "\tBit 7 6 5 4 3 2 1 0 \r\n" - "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n" - "\r\n" - "\tNote: 1) In order to remove mode from both Windows and DOS, " - "both Bit 1 and Bit 0 must be set to 1.\r\n" - "\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not " - "remove, 1 = Remove if panel is active):/r/n" - "\r\n" - "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "\r\n" - "\tNote: Default is to remove a mode resolution from all " - "panel types." -EndPage - - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ - -Page "Display Configuration Removal Table" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Pipe B" , 1 byte , BIN - Column "Pipe A" , 1 byte , BIN, - - Help "This feature allows blocking selected display configurations " - "by the video BIOS and driver.\r\n" - "\r\n" - "Display Devices are specified in the following bit patterns " - "(pipe A and B use the same bit pattern):\r\n" - "\r\n" - "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n" - "\r\n" - "Examples:\r\n" - "\tPipe B Pipe A\r\n" - "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n" - "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on " - "Pipe A" -EndPage - - -;============================================================================== -; Page - OEM Customizable Mode 2.0 -;------------------------------------------------------------------------------ - -Page "OEM Customizable Modes 2.0" - - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - EditNum $OEM_Mode_X1, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #2" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X2, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #3" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X3, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #4" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X4, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #5" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X5, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #6" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X6, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage -EndPage - - -;============================================================================ -; End of File -;------------------------------------------------------------------------------ - diff --git a/CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec b/CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec deleted file mode 100644 index 68fb386..0000000 --- a/CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# Component description file for CoffeeLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = CoffeeLakeFspBinPkg - PACKAGE_GUID = 8C3989BC-3C66-44A2-B290-23848EF42970 - PACKAGE_VERSION = 1.02 - -[Includes] - Include - -[Guids] - gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }} diff --git a/CoffeeLakeFspBinPkg/Docs/CoffeeLake_FSP_Gold_Release_Note.pdf b/CoffeeLakeFspBinPkg/Docs/CoffeeLake_FSP_Gold_Release_Note.pdf deleted file mode 100644 index 36802f09bb47ecd611aca406a45b54394f046238..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 556538 zcmeFa1z42b7C(xBASDta0>Xf_)XdP`-Hm{NbayI9NC-%W0!mAFhjcfB(k2p zzE6&EJm>iQ|IfYm^HC?>z4!Zj*V=pSm3zo!1%+vWbWCW-WF?S4XvjbS1HkgW2^umd zC%vMxl|H?Ij-8H~r6Iknj-kFS00g-#PcNxsVMwWOL93)d1)x{3v$5B;Q?$|7m$$UE z0|3FS&^A&!Hl|`029}Uw6}l^#6&M) ztY@nZ0H2Nr0J1?}z^4G^0br)H7iQ=S9F%zYDmUAxnV)wk1O0zhxd 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Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "CFLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUart0PinMuxing 1 bytes $_DEFAULT_ = 0x00 - Skip 5 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - - Find "CFLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gPlatformFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize 1 bytes $_DEFAULT_ = 0x0C - $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPreMemRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x03 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvMid 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 - Skip 15 bytes - $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort 1 bytes $_DEFAULT_ = 0x99 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 10 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - $gPlatformFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGpioData 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xD0000000 - $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xCF000000 - $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DpSscMarginEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem 13 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x001 - $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MemoryTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableCltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableOltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhPrevention 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 - $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A - $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B - $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RhActProbability 1 bytes $_DEFAULT_ = 0xB - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr 2 bytes $_DEFAULT_ = 0xDE - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x30 - $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping 1 bytes $_DEFAULT_ = 0xAA - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhSolution 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax 1 bytes $_DEFAULT_ = 0x69 - $gPlatformFspPkgTokenSpaceGuid_TsodEventMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodThigMax 1 bytes $_DEFAULT_ = 0x5D - $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_GdxcEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_FivrFaults 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 - $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnBER 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4MixedUDimm2DpcLimit 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x40 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm 1 bytes $_DEFAULT_ = 0x08 - Skip 8 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 - $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitMessage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BypassPhySyncReset 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableHeciRetry 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 - - Find "CFLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled 1 bytes $_DEFAULT_ = 0x01 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoDevMode 12 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03 - $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult 10 bytes $_DEFAULT_ = 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C - $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd 18 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchCnviMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WatchDog 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AsfEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F - $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis 4 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01 - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 4 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 8 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 34 bytes $_DEFAULT_ = 0x00 - $gCoffeeLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 10 bytes - $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Reserved2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 8 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 5 bytes - $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters 10 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable 6 bytes $_DEFAULT_ = 0x01, 0x00, 0x01, 0x00, 0x01, 0x00 - Skip 7 bytes - $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x04, 0x08, 0x02, 0x0A - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SlpS0Override 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUart0PinMuxing 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartHwFlowCtrl 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoEnableDebugUartAfterPost 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedForFuture1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 - Skip 5 bytes - $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload 4 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF - $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0F - $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4B - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 19 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbiUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 - Skip 17 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipPostBootSai 1 bytes $_DEFAULT_ = 0x00 - $gCoffeeLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , " HALT loop" - Selection 2 , " MWAIT loop" - Selection 3 , " RUN loop" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency - Selection 100000000 , "100Hz" - Selection 125000000 , "125Hz" - Selection 167000000 , "167Hz" - Selection 250000000 , "250Hz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnableSgx - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Software Control" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear - Selection 0 , " Disable ME Unconfig On Rtc Clear" - Selection 1 , " Enable ME Unconfig On Rtc Clear" - Selection 2 , " Cmos is clear" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl - Selection 0 , "Disabled" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" - Selection 4 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug - Selection 0 , "No Change" - Selection 1 , "DCI OOB" - Selection 2 , "USB2 DbC" - Selection 3 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency - Selection 4 , " 96MHz" - Selection 3 , " 48MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BdatTestType - Selection 0 , "Rank Margin Tool" - Selection 1 , "Margin2D" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1400 , "1400" - Selection 1600 , "1600" - Selection 1800 , "1800" - Selection 1867 , "1867" - Selection 2000 , "2000" - Selection 2133 , "2133" - Selection 2200 , "2200" - Selection 2400 , "2400" - Selection 2600 , "2600" - Selection 2667 , "2667" - Selection 2800 , "2800" - Selection 2933 , "2933" - Selection 3000 , "3000" - Selection 3200 , "3200" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize - Selection 0 , "Default" - Selection 1 , " 1 Byte" - Selection 2 , " 1 KB" - Selection 3 , " Max value" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme - Selection 0 , " Single Range Output" - Selection 1 , " ToPA Output" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode - Selection 0 , " Disable" - Selection 1 , "Target Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUart0PinMuxing - Selection 0 , "default pins" - Selection 1 , "pins muxed with CNV_BRI/RGI" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber - Selection 0 , "UART0" - Selection 1 , "UART1" - Selection 2 , "UART2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode - Selection 0 , " Disable" - Selection 1 , " Target Debugger Mode" - Selection 2 , " Host Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage - Selection 0 , "Disable" - Selection 1 , "Send in PEI" - Selection 2 , "Send in DXE" - Selection 3 , "Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvMid - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength - Selection 0 , "33 Ohm" - Selection 1 , "40 Ohm" - Selection 2 , "50 Ohm" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent - Selection 0 , "Disabled" - Selection 1 , "Enabled (DCI OOB+[DbC])" - Selection 2 , "Enabled (DCI OOB)" - Selection 3 , "Enabled (USB3 DbC)" - Selection 4 , "Enabled (XDP/MIPI60)" - Selection 5 , "Enabled (USB2 DbC)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh - Selection 0 , " Active low" - Selection 1 , " Active high" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType - Selection 0 , "1DPC" - Selection 1 , "2DPC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration - Selection 0 , "IPU Camera" - Selection 1 , "IPU Gen" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type - Selection 0 , "ISH Uart0" - Selection 1 , "SerialIO Uart2" - Selection 2 , "Uart over external pads" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RhSolution - Selection 0 , "Hardware RHP" - Selection 1 , "2x Refresh" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt - Selection 0 , "Msix" - Selection 1 , "Msi" - Selection 2 , "Legacy" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate - Selection 0 , "Disable" - Selection 1 , "1 CMD" - Selection 2 , "2 CMDS" - Selection 3 , "3 CMDS" - Selection 4 , "4 CMDS" - Selection 5 , "5 CMDS" - Selection 6 , "6 CMDS" - Selection 7 , "7 CMDS" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RefClk - Selection 0 , "133MHz" - Selection 1 , "100MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode - Selection 0 , " 2T" - Selection 1 , " 1T" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse - Selection 0 , " PchSfpw4Clk" - Selection 1 , " PchSfpw6Clk" - Selection 2 , " PchSfpw8Clk" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" - Selection 30 , "30" - Selection 34 , "34" - Selection 40 , "40" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize - Selection 0 , "32MB" - Selection 1 , "288MB" - Selection 2 , "544MB" - Selection 3 , "800MB" - Selection 4 , "1024MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit - Selection 0 , "BIT6" - Selection 1 , "BIT7" - Selection 2 , "BIT8" - Selection 3 , "BIT9" - Selection 4 , "BIT10" - Selection 5 , "BIT11" - Selection 6 , "BIT12" - Selection 7 , "BIT13" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUart0PinMuxing - Selection 0 , "default pins" - Selection 1 , "pins muxed with CNV_BRI/RGI" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Refresh2X - Selection 0 , "Disable" - Selection 1 , "Enabled for WARM or HOT" - Selection 2 , "Enabled HOT only" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType - Selection 0 , " VC0" - Selection 1 , " VC1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0Override - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchCnviMode - Selection 0 , "Disable" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 3 , "512 MB" - Selection 7 , "1024 MB" - Selection 15 , " 2048 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode - Selection 0 , " Disabled" - Selection 1 , " Static Configuration" - Selection 2 , " Dynamic Configuration" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Coffee Lake Platform" -EndInfoBlock - -Page "Memory Reference Code 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResister settings", HEX, - Help "Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, - Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." - Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, - Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." - Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100" - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, - Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvMid, "Mid Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvMid, - Help "SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, - Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, - Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B." - Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, - Help "This option enables data scrambling in memory." - Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, - Help "100MHz, 133MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34" - "Valid range: 0x00 ~ 0x22" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX, - Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS, - Help "Enables/Disable MRC Safe Config" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, - Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." - Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, - Help "Enables/Disable Early Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, - Help "Enables/Disable SenseAmp Offset Training" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Early ReadMPR Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, - Help "Enables/Disable Read MPR Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, - Help "Enables/Disable Receive Enable Training" - Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, - Help "Enables/Disable Jedec Write Leveling" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Write Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Read Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, - Help "Enables/Disable Dimm ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, - Help "Enables/Disable DIMM RON Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, - Help "Enables/Disable Write Drive Strength/Equalization 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, - Help "Enables/Disable Write Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, - Help "Enables/Disable Read ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, - Help "Enables/Disable Read Equalization Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, - Help "Enables/Disable Read Amplifier Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Read Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, - Help "Enables/Disable Command Voltage Centering" - Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, - Help "Enables/Disable Late Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, - Help "Enables/Disable Round Trip Latency Training" - Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, - Help "Enables/Disable Turn Around Timing Training" - Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, - Help "Enables/Disable Memory Test" - Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, - Help "Enables/Disable DIMM SPD Alias Test" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, - Help "Enables/Disable Receive Enable Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, - Help "Enables/Disable Retrain Margin Check" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, - Help "Enables/Disable Write Drive Strength Up/Dn independently" - Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, - Help "Enables/Disable ECC Support" - Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, - Help "Enables/Disable Memory Remap" - Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, - Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." - Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, - Help "Enables/Disable Enhanced Interleave support" - Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS, - Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed." - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, - Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, - Help "Enables/Disable Extern Therm Status" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Closed Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Open Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS, - Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS, - Help "Enables/Disable RAPL PL Lock" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 2 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 1 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, - Help "Enables/Disable SelfRefresh Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature" - Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS, - Help "Enables/Disable RH Prevention" - Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, - Help "Enables/Disable Exit On Failure (MRC)" - Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS, - Help "Enables/Disable LPDDR Thermal Sensor" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, - Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6" - "Valid range: 0x0000 ~ 0x3FFF" - Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, - Help "Base reference clock value, in Hertz(Default is 125Hz)" - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, - Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX, - Help "Energy Scale Factor, Default is 4" - "Valid range: 0x01 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, - Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, - Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" - "Valid range: 0x00 ~ 0x7D0" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, - Help "Enable/Disable CMD Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, - Help "Enable/Disable CMD Drive Strength and Tx Equalization" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, - Help "Enable/Disable CMD Normalization" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, - Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" - EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX, - Help "RH Activation Probability, Probability value is 1/2^(inputvalue)" - "Valid range: 0x01 ~ 0xF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX, - Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX, - Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX, - Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX, - Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, - Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX, - Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, - Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" - Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, - Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" - Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, - Help "Enable/disable(default) Energy Performance Gain." - Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution, - Help "Type of method used to prevent Row Hammer. Default is Hardware RHP" - Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, - Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." - Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, - Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, " TcritMax", HEX, - Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax" - "Valid range: 0x0 ~ 0x7F" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS, - Help "Disable:Comparator mode.\n Enable:Interrupt mode" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS, - Help "Disable:Active LOW.\nEnable:Active HIGH" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS, - Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS, - Help "Disable:Event output disable.\nEnable:Event output enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS, - Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS, - Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS, - Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX, - Help "Thigh = ThighMax (Default is 93)" - "Valid range: 0x0 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS, - Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit." - Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS, - Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh." - EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, - Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, - Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC MOT enable", &EN_DIS, - Help "GDXC MOT enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS, - Help "Fivr Faults; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS, - Help "Fivr Efficiency Management; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, - Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" - Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, - Help "Enables/Disable LpDdrDqDqsReTraining" - EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, - Help "This option configures Post Code Output Port" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, - Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" - "Valid range: 0 ~ 0x20" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX, - Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation." - "Valid range: 0 ~ 0x20" - Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, - Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs." - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4MixedUDimm2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS, - Help "Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. Disable=0, Enable(Default)=1" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS, - Help "Reserved FspmConfig CFL" - Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, - Help "Run Base Memory Test on Warm Boot" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX, - Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS, - Help "Enables/Disable the MRC training on warm boot" - Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, - Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, - Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset, "Late Command Training Relaxed Reset", &gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset, - Help "Enable/Disable Relaxed JEDEC Reset during Late Command Training (Only for DDR4)" - EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm, "REFRESH_PANIC_WM", HEX, - Help "Refresh Panic Watermark, range 1-9" - "Valid range: 0x01 ~ 0x9" - EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm, "REFRESH_HP_WM", HEX, - Help "Refresh High Priority Watermark, range 1-9" - "Valid range: 0x01 ~ 0x9" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, - Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX, - Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX, - Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX, - Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX, - Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX, - Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86." - "Valid range: 0x00 ~ 0x56" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX, - Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX, - Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX, - Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX, - Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX, - Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX, - Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX, - Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX, - Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX, - Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX, - Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX, - Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, - Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, - Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, - Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, - Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" -EndPage - -Page "System Agent 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, - Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, - Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, - Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, - Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's" - Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, - Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX, - Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX, - Help "Root port Index number to indicate which PCIe root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, - Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, - Help "0:IPU Camera, 1:IPU Gen Default is 0" - Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, - Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" - Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." - Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS, - Help "Program Cache Attributes; 0: Program; 1: Disable Program." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, - Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, - Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, - Help "Ring voltage mode; 0: Adaptive; 1: Override." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, - Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, - Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" - "Valid range: 0x0A ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control" - Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DpSscMarginEnable, "DpSscMarginEnable TYPE:{Combo", &EN_DIS, - Help "Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used on systems that exceeds allowed SSC modulation range as defined in VESA's spec" - EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, - Help "IsTPMPresence default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, - Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms" -EndPage - -Page "PCH 2" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable Write Protect SD Card Pin", &EN_DIS, - Help "Enable/disable Write Protect SD Card Pin." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS, - Help "Enable/disable eMMC Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS, - Help "Enable eMMC HS400 Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS, - Help "Enable/disable SD Card Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, - Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoDevMode, "Enable SerialIo Device Mode", HEX, - Help "0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. For FSP default setting, the IRQ 16~23 are shared with internal PCI devices, and IRQ24 is assinged to SerialIo SPI2 (0:18:6), IRQ32 is assigned to SerialIo I2C4 (0:25:0), IRQ33 is assigned to SerialIo I2C4 (0:25:1), IRQ34 is assigned to SerialIo UART2 (0:25:2). " - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0x17" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0x17" - Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, - Help "Enable/disable TCO IRQ" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC0 link. Muxed with SNDW4." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask, "PTM for PCIE RP Mask", HEX, - Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask, "DPC for PCIE RP Mask", HEX, - Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask, "DPC Extensions PCIE RP Mask", HEX, - Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, - Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, - Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" - "Valid range: 0x00 ~ 0x009C4000" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Master and Slave BME enabled", &EN_DIS, - Help "PCH eSPI Master and Slave BME enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom, "PCH SATA use RST Legacy OROM", &EN_DIS, - Help "Use PCH SATA RST Legacy OROM when CSM is Enabled" - EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX, - Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, - Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Pointer." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Length." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, - Help "Central Write Buffer feature configurable and disabled by default" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult, "CTLE Rate control CPR RCOMP multiplier (Double Rate)", HEX, - Help "CTLE Rate control CPR RCOMP multiplier (Double Rate), HSIO_RX_DWORD27 [31:24], One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd, "PchPostMemRsvd", &EN_DIS, - Help "Reserved for PCH Post-Mem" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled, "Enable Ufs Controller", &EN_DIS, - Help "Enable/disable Ufs 2.0 Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_PchCnviMode, - Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, "SdCard power enable polarity", &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, - Help "Choose SD_PWREN# polarity" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, - Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, - Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" - Combo $gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type, "CNVi MfUart1 Type", &gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type, - Help "This option configures Uart type which connects to MfUart1" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode", &EN_DIS, - Help "This option enables or disables espi lgmr" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS, - Help "Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, - Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, - Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, - Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl, "SLP_S0 VM Dynamic Control", &EN_DIS, - Help "SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport, "SLP_S0 VM 0.70V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport, "SLP_S0 VM 0.75V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDog, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer." - Combo $gPlatformFspPkgTokenSpaceGuid_AsfEnabled, "ASF Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx" - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", &EN_DIS, - Help "16 bits Value, Set OS watchdog timer." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", &EN_DIS, - Help "16 bits Value, Set BIOS watchdog timer." - Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx" - Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx" - Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, - Help "0: built-in device, 1:slot" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, - Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, - Help "Number of ClkReq signal assigned to ClkSrc" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, - Help "Enable/Disable PCIE RP Access Control Services Extended Capability" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, - Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, - Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, - Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &EN_DIS, - Help "Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping CPU and 1 for all other CPUs. 0: Disable, 1: Enable" - EditNum $gCoffeeLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX, - Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm, "Enable DMI ASPM", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel, "USB LFPS Filter selection", HEX, - Help "For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS, - Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters, "PCH USB3 RX HSIO Tuning parameters", HEX, - Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX, - Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable, 4 - HsioCtrlCompMultEnable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, - Help "Enables override of recommended LTR values for xHCI" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable, "SPI ChipSelect Enable", HEX, - Help "SPI0-2 CS0/1 Enable,Default CS0 Enabled, CS1 Disabled = 0x1 0x0. Two bytes for each Spi Controller." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierSupport, "Teton Glacier Support", &EN_DIS, - Help "Deprecated" - EditNum $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR, "Teton Glacier Cycle Router", HEX, - Help "Deprecated" - "Valid range: 0x0 ~ 0x02" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity, "SPI ChipSelect signal polarity", HEX, - Help "Selects SPI ChipSelect signal polarity." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, - Help "Enables Isolated Memory Region for PCIe." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, - Help "Selects PCIE root port number for IMR feature." - "Valid range: 0x0 ~ 23" - Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, "Teton Glacier Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, - Help "Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Deprecated 2: Dynamic Configuration. Default is 0: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0Override, "SLP_S0# Override", &gPlatformFspPkgTokenSpaceGuid_SlpS0Override, - Help "Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, "S0ix Override Settings", &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, - Help "Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\nReminder: DCI OOB (aka BSSB) uses CCA probe.\nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for DbC", &EN_DIS, - Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, - Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Device Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, - Help "Enable RAID Alternate ID." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS, - Help "Set if HS400 Tuning Data Valid." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX, - Help "Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX, - Help "Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, - Help "Deprecated." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, - Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUart0PinMuxing, "PcdSerialIoUart0PinMuxing", &gPlatformFspPkgTokenSpaceGuid_SerialIoUart0PinMuxing, - Help "Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartHwFlowCtrl, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS linesh." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoEnableDebugUartAfterPost, "Enable Debug UART Controller", &EN_DIS, - Help "Enable debug UART controller after post." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedForFuture1, "Reserved", &EN_DIS, - Help "Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, - Help "Thermal Sensor 1 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, - Help "Thermal Sensor 2 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, - Help "Thermal Sensor 3 Target Width." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode, "Enable xHCI Compliance Mode", &EN_DIS, - Help "Compliance Mode can be enabled for testing through this option but this is disabled by default." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, - Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH Sata Rst CPU Attached Storage", &EN_DIS, - Help "CPU Attached Storage" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, - Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, - Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." - Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, - Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, - Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, - Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, - Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" - Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX, - Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, - Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, - Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, - Help "Force all GPIO pads to be unlocked for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSbiUnlock, "PCH Unlock SBI access", &EN_DIS, - Help "Deprecated" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, - Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 5." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, - Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, - Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, - Help "Disable/Enable PCH to CPU energy report feature." - Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, - Help "Allow entrance to the PCH SATA test modes." - Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, - Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPostBootSai, "Skip POSTBOOT SAI", &EN_DIS, - Help "Deprecated" - Combo $gCoffeeLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, - Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." -EndPage - -Page "PCH 1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUart0PinMuxing, "PcdSerialIoUart0PinMuxing - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUart0PinMuxing, - Help "Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is set to UART0." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, - Help "To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting" - Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, - Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, - Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, - Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, - Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPreMemRsvd, "PchPreMemRsvd", &EN_DIS, - Help "Reserved for PCH Pre-Mem Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, - Help "0: Disable, 1: Enable (Default) Azalia controller" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "0: Disable, 1: Enable (Default) ISH Controller" - Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "0: Disable, 1: Enable (Default) timeout check for HECI" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, - Help "Enable PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, - Help "PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, - Help "Original LPC only decodes one byte of port 80h." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, - Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, - Help "Enable SMBus ARP support." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, - Help "The number of elements in the RsvdSmbusAddressTable." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, - Help "SMBUS Base Address (IO space)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, - Help "Size of PCIe IMR in megabytes" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, - Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, - Help "0:Disable, 1:Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection, "Root port number for IMR.", HEX, - Help "Root port number for IMR." - "Valid range: 0x00 ~ 0x18" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, - Help "Enable SMBus Alert Pin." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem, "ReservedPchPreMem", &EN_DIS, - Help "Reserved for Pch Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS, - Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once." - Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, - Help "Disable or Enable Smbus dynamic power gating." - Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, - Help "Set 1 to clear WDT status, then disable and lock WDT registers." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, - Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." - Combo $gPlatformFspPkgTokenSpaceGuid_ChipsetInitMessage, "ChipsetInit HECI message", &EN_DIS, - Help "DEPRECATED" - Combo $gPlatformFspPkgTokenSpaceGuid_BypassPhySyncReset, "Bypass ChipsetInit sync reset.", &EN_DIS, - Help "DEPRECATED" - Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, - Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" - Combo $gPlatformFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableHeciRetry, "Retry mechanism for HECI APIs", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable HECI retry." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable message check." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, - Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." - Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable KT device." -EndPage - -Page "System Agent 2" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "The Device 4 default value is 1: Enable for WHL, and 0: disable for all other CPU's" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS, - Help "0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS, - Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, - Help "DEPRECATED" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, - Help "Address of Blt buffer" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, - Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chickent bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, - Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "DEPRECATED" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, - Help "Enable or Disable TXT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS, - Help "@deprecated SkipMpInit has been moved to FspmUpd" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX, - Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, - Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, - Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, - Help "Pointer CPU BIST Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 3.6.4 of the FSP Integration Guide for more details." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Optional pointer for CpuMpHob. If the boot loader is a UEFI boot loader, and FspsUpd->FspsConfig.CpuMpPpi != NULL, then FspsUpd->FspsConfig.CpuMpHob must be != NULL. See section 3.6.4 of the FSP Integration Guide for more details." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Enable or Disable processor debug features", &EN_DIS, - Help "Enable or Disable processor debug features; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, - Help "Reserved for CPU Post-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS, - Help "Platform specific common policies that used by several silicon components. CSM status flag." - EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, - Help "The address of the table of SVID SDID to customize each SVID SDID entry." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, - Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, - Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX, - Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX, - Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX, - Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX, - Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy from 0 to 64ms" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0x00 ~ 0x64" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS, - Help "@deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX, - Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX, - Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &EN_DIS, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio, Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, - Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, - Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xF9F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, - Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, - Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, - Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, - Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, - Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS, - Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C3 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" -EndPage - diff --git a/CoffeeLakeFspBinPkg/Fsp.fd b/CoffeeLakeFspBinPkg/Fsp.fd deleted file mode 100644 index bcc5789ab9bb7ca41e165c139e823c8cfe01c421..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 790528 zcmbsRc|4Tg-#CuXFc|9$A%xJ7knCBrFA(Lb8+Jx#;!2U-$jF@9#gq>(N|id!FZc?&o=~;}HV!-=BcVxHz>~-qXqQWar4r zqa6r5^)7&;o|VDQ9~8m>ar~YW0zoAY_hNU4c3(UHzx99xIJ2yc8~~asR$D)L^#8Ltq<3FkpI;l19dP*7tnw}B2McX#!fQ-(f>$9tI?V)L zGk+>~|22XKPpU$x=-{?|=?Vcwp)*`gJH9v^p7IumfK-Jhts#7A$vQY*=SpYN8nrJ2 zg$Kr>48J}C@ie{%a1>h5B$e?(h)N2mAMyA>Km(A@bhT{c5C zgTO!9a3am3F-Rty1*Ha{AXj0Kyg0C+b1ERH5~ghLv9gAIaaiaEjtR2BvB&Fh?kN57 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z_A~Y#`#F1`z27cUjj6Gzrc`rkVro)qa;hcOnwpY234cnQp6W`Snwp)Oo0^|mkm^n? zPF<4PmGNfA(TsO9j%S?8P&3YC^kkgN=*#HO5Dudw)?sp(9f^)4N3z4>usTv4lN>fj zy2Is|>d1EFI`SO_4!5J&vBYtQW4U9cW0hl*<7vlc#}>y{N1LO|aoo}45Kgl*$!T%g zoY~HNr`x&Qxyo7VT+~VBoY<0FdyPU_JJx<{=yDY90m(7*!%6GY4 zOI*uct6a6NwXO!&Mi&STUN4;ARr_-A=$w~-{ppA9f12>|ukiPA|Aq&F@8R#C@#okj n?%eX?!NmWl1ASRo@aGgl9H$#DwEo|Jy;u@?l4Se8OW^+j1VA0Y diff --git a/CoffeeLakeFspBinPkg/FspPcds.dsc b/CoffeeLakeFspBinPkg/FspPcds.dsc deleted file mode 100644 index d641753..0000000 --- a/CoffeeLakeFspBinPkg/FspPcds.dsc +++ /dev/null @@ -1,10 +0,0 @@ -## @file -# FSP description for DynamicEx PCDs. -# -# @copyright -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## diff --git a/CoffeeLakeFspBinPkg/Include/FirmwareVersionInfoHob.h b/CoffeeLakeFspBinPkg/Include/FirmwareVersionInfoHob.h deleted file mode 100644 index c4aea4b..0000000 --- a/CoffeeLakeFspBinPkg/Include/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/Include/FspInfoHob.h b/CoffeeLakeFspBinPkg/Include/FspInfoHob.h deleted file mode 100644 index bcbabd2..0000000 --- a/CoffeeLakeFspBinPkg/Include/FspInfoHob.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @file - Header file for FSP Information HOB. - - @copyright - Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _FSP_INFO_HOB_H_ -#define _FSP_INFO_HOB_H_ - -extern EFI_GUID gFspInfoGuid; - -#pragma pack (push, 1) - -typedef struct { -UINT8 SiliconInitVersionMajor; -UINT8 SiliconInitVersionMinor; -UINT8 SiliconInitVersionRevision; -UINT8 SiliconInitVersionBuild; -UINT8 FspVersionRevision; -UINT8 FspVersionBuild; -UINT8 TimeStamp [12]; -} FSP_INFO_HOB; - -#pragma pack (pop) - -#endif // _FSP_INFO_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/Include/FspUpd.h b/CoffeeLakeFspBinPkg/Include/FspUpd.h deleted file mode 100644 index a52ed00..0000000 --- a/CoffeeLakeFspBinPkg/Include/FspUpd.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */ - -#pragma pack() - -#endif diff --git a/CoffeeLakeFspBinPkg/Include/FspmUpd.h b/CoffeeLakeFspBinPkg/Include/FspmUpd.h deleted file mode 100644 index 0e3538e..0000000 --- a/CoffeeLakeFspBinPkg/Include/FspmUpd.h +++ /dev/null @@ -1,2879 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResister settings - Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design - Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide - the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0096 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0097 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0098 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x009C - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A0 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A2 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A3 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A4 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A5 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x00A6 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AA - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x00AC - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x00AF - PchPreMemRsvd - Reserved for PCH Pre-Mem Reserved - $EN_DIS -**/ - UINT8 PchPreMemRsvd[9]; - -/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00B9 - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00BA - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB (deprecated), 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00BB - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00BC - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x00BE - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00C0 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00C2 - Mid Frequency - SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvMid; - -/** Offset 0x00C4 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00C5 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00C6 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00C7 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00C8 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00C9 -**/ - UINT8 UnusedUpdSpace1[15]; - -/** Offset 0x00D8 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00D9 - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00DA - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00DC - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00DD - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00DE - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00DF - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00E0 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00E1 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00E2 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00E4 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00E6 - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00E8 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00EA - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00EB - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00EC - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00ED - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00EE - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00EF - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00F0 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00F1 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00F2 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00F3 - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00F4 - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00F5 - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00F8 -**/ - UINT8 UnusedUpdSpace2[4]; - -/** Offset 0x00FC - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x00FD - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x00FE - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00FF -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x0100 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x0104 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x0108 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x010C - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x010E - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x0110 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x0113 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x0114 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x0115 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x0116 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x0117 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x0118 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x0119 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x011A - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x011B - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x011C - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x011D - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x011E - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x011F - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0120 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0121 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0122 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0125 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0128 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x0130 - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0138 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0145 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0146 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x0152 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0156 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0176 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0177 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0178 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x017A - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x017E - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0182 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01E3 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01E4 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01E5 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01E6 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01E7 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01EB - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01ED - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01F0 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01F1 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01F2 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01F3 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01F4 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01F5 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01FB - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01FC - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[4]; - -/** Offset 0x0200 - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x0202 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x0203 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x0204 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x0205 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x0206 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x0207 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x0208 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x0209 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x020A - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x020B - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x020C - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x020D - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x020E - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x020F - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0210 - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x0211 - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x0212 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x0213 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x0214 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x0216 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x0218 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x021A - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x021B - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x021C - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x021E - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x0220 - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0222 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0223 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0224 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0225 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0226 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0227 - DpSscMarginEnable TYPE:{Combo - Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down - spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used - on systems that exceeds allowed SSC modulation range as defined in VESA's spec - $EN_DIS -**/ - UINT8 DpSscMarginEnable; - -/** Offset 0x0228 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x022C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0230 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0234 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0238 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0240 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0244 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0248 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x024C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0250 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0258 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0260 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0261 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[3]; - -/** Offset 0x0264 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0451 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x0452 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x0453 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x0454 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0456 - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0458 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x045C - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0460 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0461 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x0462 - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x0463 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[13]; - -/** Offset 0x0470 - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x0471 - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0472 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0473 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0474 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0475 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0476 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0477 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x0478 - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x0479 - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x047A - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x047B - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x047C - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x047D - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x047E - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x047F - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0480 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0481 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0482 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0483 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0484 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x0485 - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x0486 - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x0487 - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x0488 - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x0489 - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x048A - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x048B - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x048C - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x048D - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x048E - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x048F - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0490 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0491 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0492 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0493 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0494 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x0495 - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x0496 - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x0497 - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x0498 - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x0499 - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x049A - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x049B - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x049C - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x049D - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x049E - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x049F - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x04A0 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x04A1 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x04A2 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x04A5 - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x04A6 - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x04A7 - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x04A8 - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x04AA - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04AB - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04AC - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04AD - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04B0 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04B2 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04B6 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04B7 - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04B8 - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04BA - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04BC - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04BD - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04BE - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04C0 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04C1 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04C2 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04C3 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04C4 - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04C5 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04C7 - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04CA - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04CB - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04CC - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04CD - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04CE - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04CF - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04D1 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04D2 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04D3 - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04D4 - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04D5 - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04D6 - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04D7 - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04D8 - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D9 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04DA - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04DB - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04DC - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04DD - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04DE - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04DF - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04E0 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04E1 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04E2 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04E3 - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04E4 - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04E5 - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04E6 - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04E7 - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04E8 - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E9 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04EA - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04EB - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04EC - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04ED - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04EE - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04EF - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04F0 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04F1 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04F2 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04F3 - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04F4 - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04F5 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04F6 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04F7 - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04F8 - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F9 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04FA - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04FB - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04FC - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04FD - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04FE - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04FF - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x0500 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x0501 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x0502 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x0503 - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x0504 - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x0505 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x0506 - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x0507 - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x0508 - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0509 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x050A - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x050B - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x050D - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x050E - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x050F - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4MixedUDimm2DpcLimit; - -/** Offset 0x0511 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl[2]; - -/** Offset 0x0513 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x0515 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x0516 - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x0517 - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x0518 - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x0519 - Late Command Training Relaxed Reset - Enable/Disable Relaxed JEDEC Reset during Late Command Training (Only for DDR4) - 0:Disable, 1:Enable -**/ - UINT8 LctRelaxedReset; - -/** Offset 0x051A - REFRESH_PANIC_WM - Refresh Panic Watermark, range 1-9 -**/ - UINT8 RefreshPanicWm; - -/** Offset 0x051B - REFRESH_HP_WM - Refresh High Priority Watermark, range 1-9 -**/ - UINT8 RefreshHpWm; - -/** Offset 0x051C -**/ - UINT8 ReservedFspmUpd[3]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0520 -**/ - UINT32 Signature; - -/** Offset 0x0524 - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x0525 - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0527 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0528 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0529 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x052A - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x0537 - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0539 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x053B - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x053C - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x053D - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0551 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x0565 - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x0579 -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x0582 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x0583 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x0584 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x0585 - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x0587 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x0590 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x0592 - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x0594 - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x0595 - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x0598 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x0599 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x059A - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x059B - ChipsetInit HECI message - DEPRECATED - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x059C - Bypass ChipsetInit sync reset. - DEPRECATED - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x059D - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x059E - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x059F - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05A0 - Retry mechanism for HECI APIs - Test, 0: disable, 1: enable, Enable/Disable HECI retry. - $EN_DIS -**/ - UINT8 DisableHeciRetry; - -/** Offset 0x05A1 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05A2 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05A3 - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05A4 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05A5 - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05A6 - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05A7 - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05A8 - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05A9 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05AA - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05AB - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05AC - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05AD - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05AE - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05AF - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05B0 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05B1 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05B2 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05B3 - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05B4 - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05B5 - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05B6 - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05B7 - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05B8 - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x05B9 -**/ - UINT8 ReservedFspmTestUpd[3]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x051F -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x0520 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x05BC -**/ - UINT32 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/CoffeeLakeFspBinPkg/Include/FspsUpd.h b/CoffeeLakeFspBinPkg/Include/FspsUpd.h deleted file mode 100644 index 5692ed8..0000000 --- a/CoffeeLakeFspBinPkg/Include/FspsUpd.h +++ /dev/null @@ -1,3427 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - The Device 4 default value is 1: Enable for WHL, and 0: disable for - all other CPU's - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x002E - Enable Write Protect SD Card Pin - Enable/disable Write Protect SD Card Pin. - $EN_DIS -**/ - UINT8 ScsSdCardWpPinEnabled; - -/** Offset 0x002F -**/ - UINT8 UnusedUpdSpace0[2]; - -/** Offset 0x0031 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0032 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0033 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0034 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x0035 - PCH eSPI Link Configuration Lock (SBLCL) - Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves - addresseses from range 0x0 - 0x7FF - $EN_DIS -**/ - UINT8 PchEspiLockLinkConfiguration; - -/** Offset 0x0036 -**/ - UINT8 UnusedUpdSpace1[2]; - -/** Offset 0x0038 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x003C - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0040 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0041 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0042 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x004A - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0052 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0062 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x006C - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x006D -**/ - UINT8 UnusedUpdSpace2[2]; - -/** Offset 0x006F - Enable SerialIo Device Mode - 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable - SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device - mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, - and so on. -**/ - UINT8 SerialIoDevMode[12]; - -/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. For FSP default setting, - the IRQ 16~23 are shared with internal PCI devices, and IRQ24 is assinged to SerialIo - SPI2 (0:18:6), IRQ32 is assigned to SerialIo I2C4 (0:25:0), IRQ33 is assigned to - SerialIo I2C4 (0:25:1), IRQ34 is assigned to SerialIo UART2 (0:25:2). -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x007F - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0080 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0088 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0089 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x008A - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x008B - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x008C - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x008D - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x0092 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x0093 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0094 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x00A4 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x00FC - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x00FD - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x00FE - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x00FF - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0100 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0101 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x0102 - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0108 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x010C - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x0110 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x0114 - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x0115 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x011A - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x011B - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x011F - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x0120 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x0124 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x0128 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x0129 - CTLE Rate control CPR RCOMP multiplier (Double Rate) - CTLE Rate control CPR RCOMP multiplier (Double Rate), HSIO_RX_DWORD27 [31:24], One - byte for each port. -**/ - UINT8 Usb3HsioRxCtrlCompMult[10]; - -/** Offset 0x0133 - PchPostMemRsvd - Reserved for PCH Post-Mem - $EN_DIS -**/ - UINT8 PchPostMemRsvd[18]; - -/** Offset 0x0145 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x0146 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 PchCnviMode; - -/** Offset 0x0147 - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x0148 - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x0149 - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x014A -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x014B - CNVi MfUart1 Type - This option configures Uart type which connects to MfUart1 - 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads -**/ - UINT8 PchCnviMfUart1Type; - -/** Offset 0x014C - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x014D - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x014E - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x014F - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x0150 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x0151 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x0152 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x0153 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x0154 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x0155 - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x0156 - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. - $EN_DIS -**/ - UINT8 WatchDog; - -/** Offset 0x0157 - ASF Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. - $EN_DIS -**/ - UINT8 AsfEnabled; - -/** Offset 0x0158 - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x0159 - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x015A - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x015B - OS Timer - 16 bits Value, Set OS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x015D - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x015F - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0160 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0161 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0162 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x0163 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x017B - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x018B - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x019B - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x01B3 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x01CB - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x01FC - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping - CPU and 1 for all other CPUs. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x01FD -**/ - UINT8 UnusedUpdSpace5[3]; - -/** Offset 0x0200 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x0201 - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x0202 - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x0206 - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x020A - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x020E - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0216 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0217 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0219 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x021A - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x021C - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0228 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0229 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x022A - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x022B - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x022C - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x022D - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x022E - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x022F - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x0230 - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0234 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0238 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x023C - Program GT Chickent bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x023D - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x0277 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x0278 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x027D - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x0282 - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x0287 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x028C - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x0291 - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x0296 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x029B - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x02A0 - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x02A1 - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x02A2 - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x02A7 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x02B1 - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x02BB -**/ - UINT8 UnusedUpdSpace7[10]; - -/** Offset 0x02C5 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x02CF - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x02D9 - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x02E3 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x02ED - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x02F7 - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0303 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0304 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0305 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0306 -**/ - UINT8 UnusedUpdSpace8[6]; - -/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x030D - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x030E - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x030F - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x0311 - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x0312 - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0315 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x031A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0324 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0328 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0329 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x032A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x032B - CpuMpPpi - Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. - If not NULL, FSP will use the boot loader's implementation of multiprocessing. - See section 3.6.4 of the FSP Integration Guide for more details. -**/ - UINT32 CpuMpPpi; - -/** Offset 0x032F - CpuMpHob - Optional pointer for CpuMpHob. If the boot loader is a UEFI boot loader, - and FspsUpd->FspsConfig.CpuMpPpi != NULL, then FspsUpd->FspsConfig.CpuMpHob must - be != NULL. See section 3.6.4 of the FSP Integration Guide for more details. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0333 - Enable or Disable processor debug features - Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0334 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x033E - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0346 - Enable DMI ASPM - Deprecated. - $EN_DIS -**/ - UINT8 PchDmiAspm; - -/** Offset 0x0347 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x034D - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x0352 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x035C - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0366 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0367 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x0368 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0369 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x036A - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x036B - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x036D - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x036E - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x0378 -**/ - UINT8 UnusedUpdSpace10[5]; - -/** Offset 0x037D - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x037E - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x037F -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x038E - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x0390 -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x0394 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x0395 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x0396 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03AE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03C6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x040E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0426 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x043E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0456 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x046E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x0486 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x049E - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04B6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04CE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable, - 4 - HsioCtrlCompMultEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x04FA -**/ - UINT8 UnusedUpdSpace13[4]; - -/** Offset 0x04FE - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x052E - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0546 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x055E - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x055F - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x0563 - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0567 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x056B - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0575 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default - = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x057F - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x0589 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0593 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x059D - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x05A7 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x05B1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x05BB - SPI ChipSelect Enable - SPI0-2 CS0/1 Enable,Default CS0 Enabled, CS1 Disabled = 0x1 0x0. Two bytes - for each Spi Controller. -**/ - UINT8 SerialIoSpiCsEnable[6]; - -/** Offset 0x05C1 -**/ - UINT8 UnusedUpdSpace14[7]; - -/** Offset 0x05C8 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x05E0 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05F8 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x0610 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x065D - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0662 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0663 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0664 -**/ - UINT8 UnusedUpdSpace15; - -/** Offset 0x0665 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0666 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0667 - Teton Glacier Support - Deprecated - $EN_DIS -**/ - UINT8 TetonGlacierSupport; - -/** Offset 0x0668 - Teton Glacier Cycle Router - Deprecated -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x066A - SPI ChipSelect signal polarity - Selects SPI ChipSelect signal polarity. -**/ - UINT8 SerialIoSpiCsPolarity[3]; - -/** Offset 0x066D - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x066E - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x066F - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Deprecated - 2: Dynamic Configuration. Default is 0: Disabled - 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x0670 - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x0672 - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0675 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0676 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0677 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0678 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0679 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x067A - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x067B - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x067C - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x067D - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x067E -**/ - UINT8 UnusedUpdSpace16[2]; - -/** Offset 0x0680 - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x0681 - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x0682 - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x0683 - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0685 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x0686 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0687 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0688 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x068A - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x068B - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x068C -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x068D - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x068E - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x068F - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0690 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0698 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x06A0 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x06A8 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x06B0 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x06B8 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x06C0 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x06C8 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x06D8 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x06E0 - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x06E1 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x06E2 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x06E3 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x06E4 - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x06E5 - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x06E9 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x06EA - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x06EB - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x06F5 - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06F6 - Set HS400 Tuning Data Valid - Set if HS400 Tuning Data Valid. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06F7 - Rx Strobe Delay Control - Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06F8 - Tx Data Delay Control - Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06F9 - I/O Driver Strength - Deprecated. - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06FA - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x0700 -**/ - UINT8 UnusedUpdSpace19; - -/** Offset 0x0701 - PcdSerialIoUart0PinMuxing - Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled. - 0:default pins, 1:pins muxed with CNV_BRI/RGI -**/ - UINT8 SerialIoUart0PinMuxing; - -/** Offset 0x0702 -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS linesh. -**/ - UINT8 SerialIoUartHwFlowCtrl[3]; - -/** Offset 0x0706 - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x0707 - Enable Debug UART Controller - Enable debug UART controller after post. - $EN_DIS -**/ - UINT8 SerialIoEnableDebugUartAfterPost; - -/** Offset 0x0708 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x0709 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x070A - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x070B - Reserved - Reserved - $EN_DIS -**/ - UINT8 ReservedForFuture1; - -/** Offset 0x070C - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x070D - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x070F - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x0713 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x0714 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x0715 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x0716 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x0717 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x071A - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x071B - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x071C - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x071D - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x071E - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x071F - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x0720 - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x0721 - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x0722 - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x0723 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x0724 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x0725 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x0726 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x0728 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x072A - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x072B - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x072C - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x072E - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x0730 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x0732 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x0734 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x0735 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0745 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x074F - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x0750 - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x0753 -**/ - UINT8 UnusedUpdSpace21; - -/** Offset 0x0754 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x0758 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0759 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0779 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x077D - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0785 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x078D - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x078E - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x078F - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x0797 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x079F - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07A0 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07A1 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07A5 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07A7 - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07A8 - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07A9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x07AB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x07AC -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07AD -**/ - UINT32 Signature; - -/** Offset 0x07B1 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07B2 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07B3 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07B4 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07B5 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07B6 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07BA - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07BB - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07BC - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07BD - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07BE - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07BF - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07C0 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07CB - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07CC - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07CD - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07CE - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07CF - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07D0 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07D1 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07D2 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07D3 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07D4 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07D5 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07D6 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07D7 - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07D8 - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07DA - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07DB - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07DC - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07DD - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07DE - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07DF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07E0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07E1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07E2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07E3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07E4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07E5 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07E6 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07E7 - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07E8 - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07E9 - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x07ED - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x07EF - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x07F1 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x07F2 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x07F3 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x07FB - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x07FF - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0801 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0803 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x0806 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x0807 - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x0808 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x0809 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x080A - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x080B - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x080C - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x080D - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x080F - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0810 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0812 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0813 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0814 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x0815 - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x0816 - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x0817 - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x0818 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x0819 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x081A - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x081B - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x081C - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x081D - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x081E - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x0856 - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0864 - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0868 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x086C - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0870 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x0874 - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x0890 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x0894 - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x0898 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x089A - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x089B - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x089C - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x089D - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08A2 - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08A3 - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08A4 - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08A7 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[19]; - -/** Offset 0x08BA - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08BB - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08BC - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08BD - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08BF - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08C1 - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08C2 - PCH Unlock SBI access - Deprecated - $EN_DIS -**/ - UINT8 PchSbiUnlock; - -/** Offset 0x08C3 - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A5D - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A5E - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A5F - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A61 -**/ - UINT8 UnusedUpdSpace22[17]; - -/** Offset 0x0A72 - Skip POSTBOOT SAI - Deprecated - $EN_DIS -**/ - UINT8 SkipPostBootSai; - -/** Offset 0x0A73 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A74 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07AD -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0A80 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/CoffeeLakeFspBinPkg/Include/FsptUpd.h b/CoffeeLakeFspBinPkg/Include/FsptUpd.h deleted file mode 100644 index e16cffb..0000000 --- a/CoffeeLakeFspBinPkg/Include/FsptUpd.h +++ /dev/null @@ -1,114 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT - Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is - set to UART0. - 0:default pins, 1:pins muxed with CNV_BRI/RGI -**/ - UINT8 PcdSerialIoUart0PinMuxing; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 -**/ - UINT32 PcdSerialIoUartInputClock; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 -**/ - UINT8 ReservedFsptUpd1[44]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0080 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/CoffeeLakeFspBinPkg/Include/GpioConfig.h b/CoffeeLakeFspBinPkg/Include/GpioConfig.h deleted file mode 100644 index 2b88ffd..0000000 --- a/CoffeeLakeFspBinPkg/Include/GpioConfig.h +++ /dev/null @@ -1,328 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - -@copyright - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 9; - UINT32 RsvdBits : 10; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, - GpioPadModeNative5 = 0xB -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Configuration options for GPIO termination setting -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. - By default GPIO pads will be locked unless GPIO lib is explicitly - informed that certain pad is to be left unlocked. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controlled - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock - an already locked pad upon request for reconfiguration -**/ -typedef enum { - /** - Perform default action - - if pad is an GPO, lock configuration but leave output unlocked - - if pad is an GPI, lock everything - - if pad is in native, lock everything -**/ - GpioLockDefault = 0x0, - GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked - GpioPadConfigLock = 0x1, ///< Lock Pad configuration - GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked - GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked - GpioPadLock = 0x5 ///< Lock both Pad configuration and output control -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/CoffeeLakeFspBinPkg/Include/GpioSampleDef.h b/CoffeeLakeFspBinPkg/Include/GpioSampleDef.h deleted file mode 100644 index 1e1c2aa..0000000 --- a/CoffeeLakeFspBinPkg/Include/GpioSampleDef.h +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Sample enum definitions for GPIO table. - - @copyright - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/CoffeeLakeFspBinPkg/Include/HobUsageDataHob.h b/CoffeeLakeFspBinPkg/Include/HobUsageDataHob.h deleted file mode 100644 index 19c3e78..0000000 --- a/CoffeeLakeFspBinPkg/Include/HobUsageDataHob.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Definitions for Hob Usage data HOB - - @copyright - Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _HOB_USAGE_DATA_HOB_H_ -#define _HOB_USAGE_DATA_HOB_H_ - -extern EFI_GUID gHobUsageDataGuid; - -#pragma pack (push, 1) - -/** - Hob Usage Data Hob - - Revision 1: - - Initial version. -**/ -typedef struct { - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - UINTN FreeMemory; -} HOB_USAGE_DATA_HOB; - -#pragma pack (pop) - -#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/Include/MemInfoHob.h b/CoffeeLakeFspBinPkg/Include/MemInfoHob.h deleted file mode 100644 index 746f513..0000000 --- a/CoffeeLakeFspBinPkg/Include/MemInfoHob.h +++ /dev/null @@ -1,269 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef CPU_CFL//CNL -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#else//CFL -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif -#endif//CPU_CFL-endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -#ifdef CPU_CFL - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; -#endif //CPU_CFL -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/Include/SmbiosCacheInfoHob.h b/CoffeeLakeFspBinPkg/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index 3623b55..0000000 --- a/CoffeeLakeFspBinPkg/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 - // - // Add for smbios 3.1.0 - // - UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h b/CoffeeLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index f28250c..0000000 --- a/CoffeeLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/CoffeeLakeFspBinPkg/README.md b/CoffeeLakeFspBinPkg/README.md deleted file mode 100644 index 079a543..0000000 --- a/CoffeeLakeFspBinPkg/README.md +++ /dev/null @@ -1,12 +0,0 @@ -# CoffeeLakeFspBinPkg -This FSP binary is intended to be used with 8th Generation Intel® Core™ processors and chipsets formerly known as Coffee Lake and Whiskey Lake. It is ***not*** intended to be used with 8th Generation Intel® Core™ processors and chipsets formerly known as Kaby Lake Refresh or Amber Lake. - -In rare circumstances, AmberLakeFspBinPkg is used instead of CoffeeLakeFspBinPkg with 9th and 8th Generation Intel® Core™ processors and chipsets formerly known as Coffee Lake. Specifically, AmberLakeFspBinPkg is only used with Coffee Lake desktop processors when installed in a motherboard that utilizes a 22nm Platform Controller Hub (PCH). AmberLakeFspBinPkg is never used with mobile Coffee Lake or Whiskey Lake processors. The following Intel® 300 Series Chipsets use 22nm fabrication: - -* Intel® Z370 Chipset -* Intel® B365 Chipset -* Intel® H310C Chipset - -For all other Intel® 300 Series Chipsets, please use CoffeeLakeFspBinPkg. - -Note: Whiskey Lake support has been added starting with FSP release 7.0.58.40, previous versions of CoffeeLakeFspBinPkg do not support Whiskey Lake. diff --git a/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin b/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index cbe384b0afd836fe5bee85f75002f5cdfa3f812a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKUu;ul6hF7Oe{R2fZ+Ck~q^md&e**1b<90yBIpXcw;mQi_*0GFevH~r*P}tlb z9R{NOs zx!?WWbH4A~?>l!ze@7o?yLY5w-JNJt9yB=RKSu4X)R9bQ2NSWr*kDI09q-1U;4v8Y z-?$8r=ePzbqG^%jf$>5y)Eg$)6mA{fHB>CDO%%rVjSr7tCZ5FD?%joAVRYwsA&=Sq z=VEAJ%B*8zsF=rX6Z>}+M%$2pG#ZVO^)2hxBSzM?(qD^gAXRINMB6qzEwe;tJiRrO zOvU<=>1~+q#Y8e2%Vs;bcBFP-rZ?S{>`3-?CS*1jMtpeW;ONla7soLa4`VAmquB&C zUB>wE=tv93ibd=-#*ATaVXQFvav|R$GXvx-2u==wb3vUB9Q@e|WB@@20YOl}se=>2 zseq24D}V|J08RiM009)k2?ZRRI0xBQ3E&PGmRTZr-qdwtuuX&p7jmE|g6g$Q9(uf~ zDI8h~_2_Z%jX7+EJe}g!*6=N9MXi<9@3G1O6hn7NjpzW#xUG^~105S;wHq10V z=!WM2uD?o8C20@`oIwCSPJ<)fMo9A^IK(^P4SpjuInROSMaX&;*h74f_*)l)?};xF zUm?Cm>~b@xBW@sGPTWlV6mg8Wn|M3%An_2fdjhUk93`NYAS!XT^ji`XCmabw>4a@R zVcWgG(V`PETZ*36#(lRVoj=Ce_0hdJ}n}eR_!*%XWauNtuU9V19bXZBnJ#q%;kS zJ^**ny5wn}9W!74n^%Iy&hWUzpZ730@43nyuK#ap#+)e&{H%Gcrkd4%)IOSlyPJU} zU2wr$D&xf`6d||Fy0`J(EKj~bIqMK;8Tv(axyYJD%!+D3 zWWyr9BdQ;Y>{AiH6V+ct_PdA;lDb-A8zg*QQuj;j6$#&$)K4V#xr9GR>J^DylW?i5 zu9Mj&8F$O-gv_R7JSD52$?OXmFUjg3GUI(1_NmYKSf>y7`PA2Z>`kBCq`FFui(JX? zGwTy!RHFT9z#*CPDyNWi)vcnF@YaQiPEkQ%1ScUs;8+-8rVb%8umnS;Mb?xwMyISp zk=Bd0{Dl$n4WP$hr4~3GwGaZ)Dc&lp$W3q>2<=o{-98Gf36A%GrfVbhb3V|GhAvII zf;AybVoy-fm75T_vgvz!o`jMxDP!BsYE8EM8fT|+*+7oIuaGrdg9yt{Y~fd{jMmUMS52wIbVE;pUm z0zFpEX!yWWIuhM$PMQd^h2X*(qPQG{nG7!0BrRTzqD=22`B3s~H1oko^4n*%qpcKp zX=AfK&|F;$9_lO~=<8?U_adxAt_1ZtMe$dCppDe!nP zyZUu-Z#hSG{OSAGR_2jo9<7POTbs$rBvtp@=>W^a8txeU%+pqE5!J;ex#v-f#=+q^ ZdN@>TF=jtr9=Kd*e|+C5C;owJe*r(5+8+P_ diff --git a/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf b/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index d14a9ef..0000000 --- a/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11678 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2019). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Coffeelake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from CFL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x01, "Pin-Pair #1" - Selection 0x02, "Pin-Pair #2" - Selection 0x03, "Pin-Pair #3" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Coffeelake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if there’s no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel® Rapid Memory Power Management (RMPM)\r\n" - "2. Intel® Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel® Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel® Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop CFL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &No_Yes_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &No_Yes_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec b/CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec deleted file mode 100644 index 6bdeac0..0000000 --- a/CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec +++ /dev/null @@ -1,29 +0,0 @@ -## @file -# Component description file for CometLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = CometLakeFspBinPkg - PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 - PACKAGE_VERSION = 1.02 - -[Includes] - Include - -[Guids] - gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }} - -[Ppis] - gEfiReadyToInstallPciEnumerationCompleteProtocolGuid = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }} - gEfiReadyToInstallEventReadyToBootGuid = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }} - gFspReadyToInstallEventEndOfFirmwareGuid = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }} - gEndOfFspS3NotifyGuid = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }} - gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }} diff --git a/CometLakeFspBinPkg/CometLake1/Fsp.bsf b/CometLakeFspBinPkg/CometLake1/Fsp.bsf deleted file mode 100644 index 7df7269..0000000 --- a/CometLakeFspBinPkg/CometLake1/Fsp.bsf +++ /dev/null @@ -1,4862 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "CMLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gPlatformFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize 1 bytes $_DEFAULT_ = 0x0C - $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort 1 bytes $_DEFAULT_ = 0x99 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 10 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGpioData 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xD0000000 - $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xCF000000 - $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x001 - $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MemoryTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableCltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableOltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhPrevention 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 - $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A - $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B - $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RhActProbability 1 bytes $_DEFAULT_ = 0xB - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr 2 bytes $_DEFAULT_ = 0xDE - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x30 - $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping 1 bytes $_DEFAULT_ = 0xAA - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhSolution 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax 1 bytes $_DEFAULT_ = 0x69 - $gPlatformFspPkgTokenSpaceGuid_TsodEventMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodThigMax 1 bytes $_DEFAULT_ = 0x5D - $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_GdxcEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_FivrFaults 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 - $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnBER 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FastBootRmt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x40 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 - Skip 9 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 - $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis 4 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01 - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 4 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 8 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 34 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Reserved2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonSlope1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonOffset1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 8 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity 2 bytes $_DEFAULT_ = 0x00, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x02 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 12 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 3 bytes $_DEFAULT_ = 0x08, 0x08, 0x08 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 3 bytes $_DEFAULT_ = 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux 3 bytes $_DEFAULT_ = 0, 0, 0 - $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F - $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters 10 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x06, 0x08, 0x02, 0x0A - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x08, 0x0C, 0x08, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SlpS0Override 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem 3 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - Skip 8 bytes - $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload 4 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF - $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0F - $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4B - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 16 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux - Selection 0 , " GPIO C8 to C11" - Selection 1 , " GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RhSolution - Selection 0 , "Hardware RHP" - Selection 1 , "2x Refresh" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration - Selection 0 , "IPU Camera" - Selection 1 , "IPU Gen" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit - Selection 0 , "BIT6" - Selection 1 , "BIT7" - Selection 2 , "BIT8" - Selection 3 , "BIT9" - Selection 4 , "BIT10" - Selection 5 , "BIT11" - Selection 6 , "BIT12" - Selection 7 , "BIT13" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType - Selection 0 , "1DPC" - Selection 1 , "2DPC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl - Selection 0 , "Disabled" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" - Selection 4 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , " HALT loop" - Selection 2 , " MWAIT loop" - Selection 3 , " RUN loop" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug - Selection 0 , "No Change" - Selection 1 , "DCI OOB" - Selection 2 , "USB2 DbC" - Selection 3 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode - Selection 0 , "SerialIoUartDisabled" - Selection 1 , "SerialIoUartPci" - Selection 2 , "SerialIoUartHidden" - Selection 3 , "SerialIoUartCom" - Selection 4 , "SerialIoUartSkipInit" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode - Selection 0 , " 2T" - Selection 1 , " 1T" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType - Selection 0 , " VC0" - Selection 1 , " VC1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0Override - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent - Selection 0 , "Disabled" - Selection 1 , "Enabled (DCI OOB+[DbC])" - Selection 2 , "Enabled (DCI OOB)" - Selection 3 , "Enabled (USB3 DbC)" - Selection 4 , "Enabled (XDP/MIPI60)" - Selection 5 , "Enabled (USB2 DbC)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency - Selection 100000000 , "100Hz" - Selection 125000000 , "125Hz" - Selection 167000000 , "167Hz" - Selection 250000000 , "250Hz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode - Selection 0 , " Disable" - Selection 1 , "Target Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BdatTestType - Selection 0 , "Rank Margin Tool" - Selection 1 , "Margin2D" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" - Selection 30 , "30" - Selection 34 , "34" - Selection 40 , "40" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme - Selection 0 , " Single Range Output" - Selection 1 , " ToPA Output" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate - Selection 0 , "Disable" - Selection 1 , "1 CMD" - Selection 2 , "2 CMDS" - Selection 3 , "3 CMDS" - Selection 4 , "4 CMDS" - Selection 5 , "5 CMDS" - Selection 6 , "6 CMDS" - Selection 7 , "7 CMDS" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt - Selection 0 , "Msix" - Selection 1 , "Msi" - Selection 2 , "Legacy" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh - Selection 0 , " Active low" - Selection 1 , " Active high" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize - Selection 0 , "32MB" - Selection 1 , "288MB" - Selection 2 , "544MB" - Selection 3 , "800MB" - Selection 4 , "1024MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow - Selection 0 , " Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Refresh2X - Selection 0 , "Disable" - Selection 1 , "Enabled for WARM or HOT" - Selection 2 , "Enabled HOT only" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CnviMode - Selection 0 , "Disable" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength - Selection 0 , "33 Ohm" - Selection 1 , "40 Ohm" - Selection 2 , "50 Ohm" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode - Selection 0 , " Disabled" - Selection 1 , " Dynamic Configuration" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RefClk - Selection 0 , "133MHz" - Selection 1 , "100MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize - Selection 0 , "Default" - Selection 1 , " 1 Byte" - Selection 2 , " 1 KB" - Selection 3 , " Max value" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnableSgx - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Software Control" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck - Selection 0 , "Disable" - Selection 1 , "L1" - Selection 2 , "L2" - Selection 3 , "Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber - Selection 0 , "UART0" - Selection 1 , "UART1" - Selection 2 , "UART2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1400 , "1400" - Selection 1600 , "1600" - Selection 1800 , "1800" - Selection 1867 , "1867" - Selection 2000 , "2000" - Selection 2133 , "2133" - Selection 2200 , "2200" - Selection 2400 , "2400" - Selection 2600 , "2600" - Selection 2667 , "2667" - Selection 2800 , "2800" - Selection 2933 , "2933" - Selection 3000 , "3000" - Selection 3200 , "3200" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix - Selection 0 , "Positive" - Selection 1 , "Negative" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear - Selection 0 , " Disable ME Unconfig On Rtc Clear" - Selection 1 , " Enable ME Unconfig On Rtc Clear" - Selection 2 , " Cmos is clear" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse - Selection 0 , " PchSfpw4Clk" - Selection 1 , " PchSfpw6Clk" - Selection 2 , " PchSfpw8Clk" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 3 , "512 MB" - Selection 7 , "1024 MB" - Selection 15 , " 2048 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency - Selection 4 , " 96MHz" - Selection 3 , " 48MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode - Selection 0 , "Legacy" - Selection 1 , "Selection" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode - Selection 0 , " Disable" - Selection 1 , " Target Debugger Mode" - Selection 2 , " Host Debugger Mode" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Comet Lake Platform" -EndInfoBlock - -Page "System Agent 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, - Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, - Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, - Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, - Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's" - Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "0: Disable, 1: Enable (Default) timeout check for HECI" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, - Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX, - Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX, - Help "Root port Index number to indicate which PCIe root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, - Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, - Help "0:IPU Camera, 1:IPU Gen Default is 0" - Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, - Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" - Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, - Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1." - "Valid range: 0x00 ~ 0x1FF" - Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." - Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS, - Help "Program Cache Attributes; 0: Program; 1: Disable Program." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, - Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, - Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, - Help "Ring voltage mode; 0: Adaptive; 1: Override." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, - Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, - Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" - "Valid range: 0x0A ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control" - Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, - Help "IsTPMPresence default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS, - Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, - Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms" - Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, - Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " -EndPage - -Page "System Agent 2" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "Enable/disable Device 4" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, - Help "Central Write Buffer feature configurable and disabled by default" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS, - Help "Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, - Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, - Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution." - Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS, - Help "0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS, - Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, - Help "DEPRECATED" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, - Help "Address of Blt buffer" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, - Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, - Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "DEPRECATED" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, - Help "Enable or Disable TXT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS, - Help "@deprecated SkipMpInit has been moved to FspmUpd" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX, - Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, - Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, - Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, - Help "Pointer CPU BIST Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Pointer for CpuMpPpi" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, - Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, - Help "Reserved for CPU Post-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS, - Help "Platform specific common policies that used by several silicon components. CSM status flag." - EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, - Help "The address of the table of SVID SDID to customize each SVID SDID entry." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, - Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, - Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX, - Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX, - Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX, - Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX, - Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy from 0 to 64ms" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0x00 ~ 0x64" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS, - Help "@deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX, - Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX, - Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable, 2: Auto / Silicon default" - Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio, Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, - Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, - Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xF9F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, - Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, - Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, - Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, - Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, - Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS, - Help "@deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS, - Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C3 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0, "Ratio Limit Num Core 0", HEX, - Help "Ratio Limit Num Core0: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1, "Ratio Limit Num Core 1", HEX, - Help "Ratio Limit Num Core1: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2, "Ratio Limit Num Core 2", HEX, - Help "Ratio Limit Num Core2: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3, "Ratio Limit Core 3", HEX, - Help "Ratio Limit Num Core3: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4, "Ratio Limit Num Core 4", HEX, - Help "Ratio Limit Num Core4: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5, "Ratio Limit Num Core 5", HEX, - Help "Ratio Limit Num Core5: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6, "Ratio Limit Num Core 6", HEX, - Help "Ratio Limit Num Core6: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7, "Ratio Limit Num Core 7", HEX, - Help "Ratio Limit Num Core7: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, - Help "Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer, "ITBMT 3.0 Runtime Periodic SMM timer", HEX, - Help "Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, 6 - 32 sec, 7 - 64 sec." - "Valid range: 0x00 ~ 0x07" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" -EndPage - -Page "Memory Reference Code 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, - Help "Indicates RcompResistor settings: CML - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, - Help "Time Measure: 0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, - Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." - Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, - Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." - Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100" - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, - Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, - Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, - Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B." - Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, - Help "This option enables data scrambling in memory." - Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, - Help "100MHz, 133MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34" - "Valid range: 0x00 ~ 0x22" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX, - Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, - Help "Margin Limit Check. Choose level of margin check" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS, - Help "Enables/Disable MRC Safe Config" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, - Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." - Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, - Help "Enables/Disable Early Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, - Help "Enables/Disable SenseAmp Offset Training" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Early ReadMPR Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, - Help "Enables/Disable Read MPR Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, - Help "Enables/Disable Receive Enable Training" - Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, - Help "Enables/Disable Jedec Write Leveling" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Write Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Read Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, - Help "Enables/Disable Dimm ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, - Help "Enables/Disable DIMM RON Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, - Help "Enables/Disable Write Drive Strength/Equalization 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, - Help "Enables/Disable Write Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, - Help "Enables/Disable Read ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, - Help "Enables/Disable Read Equalization Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, - Help "Enables/Disable Read Amplifier Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Read Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, - Help "Enables/Disable Command Voltage Centering" - Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, - Help "Enables/Disable Late Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, - Help "Enables/Disable Round Trip Latency Training" - Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, - Help "Enables/Disable Turn Around Timing Training" - Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, - Help "Enables/Disable Memory Test" - Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, - Help "Enables/Disable DIMM SPD Alias Test" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, - Help "Enables/Disable Receive Enable Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, - Help "Enables/Disable Retrain Margin Check" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, - Help "Enables/Disable Write Drive Strength Up/Dn independently" - Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, - Help "Enables/Disable ECC Support" - Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, - Help "Enables/Disable Memory Remap" - Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, - Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." - Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, - Help "Enables/Disable Enhanced Interleave support" - Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS, - Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed." - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, - Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, - Help "Enables/Disable Extern Therm Status" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Closed Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Open Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS, - Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS, - Help "Enables/Disable RAPL PL Lock" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 2 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 1 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, - Help "Enables/Disable SelfRefresh Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature" - Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS, - Help "Enables/Disable RH Prevention" - Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, - Help "Enables/Disable Exit On Failure (MRC)" - Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS, - Help "Enables/Disable LPDDR Thermal Sensor" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, - Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6" - "Valid range: 0x0000 ~ 0x3FFF" - Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, - Help "Base reference clock value, in Hertz(Default is 125Hz)" - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, - Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX, - Help "Energy Scale Factor, Default is 4" - "Valid range: 0x01 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, - Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, - Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" - "Valid range: 0x00 ~ 0x7D0" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, - Help "Enable/Disable CMD Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, - Help "Enable/Disable CMD Drive Strength and Tx Equalization" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, - Help "Enable/Disable CMD Normalization" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, - Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" - EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX, - Help "RH Activation Probability, Probability value is 1/2^(inputvalue)" - "Valid range: 0x01 ~ 0xF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX, - Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX, - Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX, - Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX, - Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, - Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX, - Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, - Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" - Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, - Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" - Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, - Help "Enable/disable(default) Energy Performance Gain." - Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution, - Help "Type of method used to prevent Row Hammer. Default is Hardware RHP" - Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, - Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." - Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, - Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, " TcritMax", HEX, - Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax" - "Valid range: 0x0 ~ 0x7F" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS, - Help "Disable:Comparator mode.\n Enable:Interrupt mode" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS, - Help "Disable:Active LOW.\nEnable:Active HIGH" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS, - Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS, - Help "Disable:Event output disable.\nEnable:Event output enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS, - Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS, - Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS, - Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX, - Help "Thigh = ThighMax (Default is 93)" - "Valid range: 0x0 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS, - Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit." - Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS, - Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh." - EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, - Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, - Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC MOT enable", &EN_DIS, - Help "GDXC MOT enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS, - Help "Fivr Faults; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS, - Help "Fivr Efficiency Management; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, - Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" - Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, - Help "Enables/Disable LpDdrDqDqsReTraining" - EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, - Help "This option configures Post Code Output Port" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, - Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" - "Valid range: 0 ~ 0x20" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX, - Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation." - "Valid range: 0 ~ 0x20" - Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, - Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs." - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS, - Help "Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. Disable=0, Enable(Default)=1" - Combo $gPlatformFspPkgTokenSpaceGuid_FastBootRmt, "RMT on Fast flow", &EN_DIS, - Help "Enable/Disable RMT on Fast flow. Default: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS, - Help "Reserved FspmConfig CFL" - Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, - Help "Run Base Memory Test on Warm Boot" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX, - Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS, - Help "Enables/Disable the MRC training on warm boot" - Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, - Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, - Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, - Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "deprecated" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, - Help "Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; 0: Legacy; 1: Selection." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, - Help "Array used to specifies the Offset Voltage applied to the each selected Core VF Point. This voltage is specified in millivolts." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, - Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, - Help "Array for the each selected Core VF Point to display the ration." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX, - Help "Number of supported Core Voltage & Frequency Point Offset" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, - Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX, - Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX, - Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX, - Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX, - Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX, - Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86." - "Valid range: 0x00 ~ 0x56" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX, - Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX, - Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX, - Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX, - Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX, - Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX, - Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX, - Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX, - Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX, - Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX, - Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX, - Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, - Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, - Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, - Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, - Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" -EndPage - -Page "PCH 1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, - Help "Select SerialIo Uart Controller mode" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, - Help "Set default Parity." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, - Help "Set default stop bits." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, - Help "Enables UART hardware flow control, CTS and RTS lines." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, "PcdSerialIoUartPinMux - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, - Help "Enable to initialize LPC Uart device in FSP." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity, "SPI0 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity, "SPI1 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity, "SPI2 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable, "SPI0 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable, "SPI1 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable, "SPI2 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, - Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, - Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, - Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, - Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, - Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, - Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, - Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, - Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, - Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS lines." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux, "Serial IO UART Pin Mux", HEX, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, - Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS, - Help "Enable/disable eMMC Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS, - Help "Enable eMMC HS400 Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS, - Help "Enable/disable SD Card Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0x17" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0x17" - Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, - Help "Enable/disable TCO IRQ" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, - Help "To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting" - Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, - Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, - Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, - Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, - Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, - Help "0: Disable, 1: Enable (Default) Azalia controller" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "0: Disable, 1: Enable (Default) ISH Controller" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, - Help "Enable PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, - Help "PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, - Help "Enables override of recommended LTR values for xHCI" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC0 link. Muxed with SNDW4." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask, "PTM for PCIE RP Mask", HEX, - Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask, "DPC for PCIE RP Mask", HEX, - Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask, "DPC Extensions PCIE RP Mask", HEX, - Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, - Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, - Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" - "Valid range: 0x00 ~ 0x009C4000" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Master and Slave BME enabled", &EN_DIS, - Help "PCH eSPI Master and Slave BME enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom, "PCH SATA use RST Legacy OROM", &EN_DIS, - Help "Use PCH SATA RST Legacy OROM when CSM is Enabled" - EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX, - Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, - Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Pointer." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Length." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled, "Enable Ufs Controller", &EN_DIS, - Help "Enable/disable Ufs 2.0 Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, - Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, - Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, - Help "Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, "SdCard power enable polarity", &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, - Help "Choose SD_PWREN# polarity" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, - Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, - Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode", &EN_DIS, - Help "This option enables or disables espi lgmr" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, - Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, - Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, - Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl, "SLP_S0 VM Dynamic Control", &EN_DIS, - Help "SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport, "SLP_S0 VM 0.70V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport, "SLP_S0 VM 0.75V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, - Help "0: built-in device, 1:slot" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, - Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, - Help "Number of ClkReq signal assigned to ClkSrc" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, - Help "Enable/Disable PCIE RP Access Control Services Extended Capability" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, - Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, - Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, - Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &EN_DIS, - Help "Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping CPU and 1 for PCH-H Series. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel, "USB LFPS Filter selection", HEX, - Help "For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS, - Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, - Help "Original LPC only decodes one byte of port 80h." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, - Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, - Help "Enable SMBus ARP support." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, - Help "The number of elements in the RsvdSmbusAddressTable." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, - Help "SMBUS Base Address (IO space)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, - Help "Size of PCIe IMR in megabytes" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, - Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, - Help "0:Disable, 1:Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection, "Root port number for IMR.", HEX, - Help "Root port number for IMR." - "Valid range: 0x00 ~ 0x18" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, - Help "Enable SMBus Alert Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS, - Help "Enables UART hardware flow control, CTS and RTS lines." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, - Help "Set default Parity." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, - Help "Set default stop bits." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem, "ReservedPchPreMem", &EN_DIS, - Help "Reserved for Pch Pre-Mem" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters, "PCH USB3 RX HSIO Tuning parameters", HEX, - Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX, - Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS, - Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once." - Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, - Help "Disable or Enable Smbus dynamic power gating." - Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, - Help "Set 1 to clear WDT status, then disable and lock WDT registers." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, - Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS, - Help "Reserved for Pch Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, - Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" - Combo $gPlatformFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable message check." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, - Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." - Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable KT device." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR, "Teton Glacier Cycle Router", HEX, - Help "Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system " - "Valid range: 0x0 ~ 0x02" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, - Help "Enables Isolated Memory Region for PCIe." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, - Help "Selects PCIE root port number for IMR feature." - "Valid range: 0x0 ~ 23" - Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, "Teton Glacier Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, - Help "Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0Override, "SLP_S0# Override", &gPlatformFspPkgTokenSpaceGuid_SlpS0Override, - Help "Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, "S0ix Override Settings", &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, - Help "Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\nReminder: DCI OOB (aka BSSB) uses CCA probe.\nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for DbC", &EN_DIS, - Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, - Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Device Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, - Help "Enable RAID Alternate ID." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS, - Help "Deprecated" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, - Help "Deprecated" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, - Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, - Help "Thermal Sensor 1 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, - Help "Thermal Sensor 2 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, - Help "Thermal Sensor 3 Target Width." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode, "Enable xHCI Compliance Mode", &EN_DIS, - Help "Compliance Mode can be enabled for testing through this option but this is disabled by default." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, - Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH Sata Rst CPU Attached Storage", &EN_DIS, - Help "CPU Attached Storage" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, - Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, - Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, - Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, - Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients, "Number of Coefficients to be used", HEX, - Help "The number of coefficients to be used for equalization, default value is 3" - "Valid range: 0x0 ~ 0x5" - Combo $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating, "GPIO RCOMP Community Clock Gating", &EN_DIS, - Help "0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock local clock gating, default value is 1" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable SD Card Write Protect Pin", &EN_DIS, - Help "Enable/disable SD Card Write Protect Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, - Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS, - Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem, "ReservedPchPostMem", &EN_DIS, - Help "Reserved for Pch Post-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX, - Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, - Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, - Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, - Help "Force all GPIO pads to be unlocked for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, - Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 5." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, - Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, - Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, - Help "Disable/Enable PCH to CPU energy report feature." - Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, - Help "Allow entrance to the PCH SATA test modes." - Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, - Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS, - Help "Reserved for Pch Post-Mem Test" - Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, - Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls, "Use DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue, "Emmc Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue, "Emmc Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue, "Emmc Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue, "Emmc Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue, "Emmc Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue, "Emmc Rx Strobe Delay control register value", HEX, - Help "Please see Rx Strobe Delay control register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls, "Use tuned DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue, "SdCard Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue, "SdCard Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue, "SdCard Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue, "SdCard Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue, "SdCard Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS, - Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, - Help "Address of LogoPixelHeight" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, - Help "Address of LogoPixelWidth" - "Valid range: 0x0 ~ 0xFFFFFFFF" -EndPage - -Page "PCH 2" - EditNum $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX, - Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, - Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." - Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, - Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &EN_DIS, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): Enable EOP message" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" -EndPage - diff --git a/CometLakeFspBinPkg/CometLake1/Fsp.fd b/CometLakeFspBinPkg/CometLake1/Fsp.fd deleted file mode 100644 index c336e9adfe078f2f55e7ca1362100766a4059a79..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 815104 zcmeFYc|6qL_c%Ud24iccQVB&&5t1#tEE$v~WKTp$N(zHyZBoXwQL?1ao}{vrwUB+^ z$(phxV++~0=69b%uUD_v=k@-4-tX_{@%uf#fBdfI`Ml42&pG#;bI&>V-1~fnK>W4% z4Boh*62^PMpdQ1cC*BNM8@M;n#Q>prH^bi6}+{qJ#C%@!?tr^3UgfPzN{!zykt_I7-kr zG(HMWf(;m#xI>DjbX4zcDxC-0+1k=Vv)RfFrZxmV5kJ8v1+&Kp@Bs(;M z3|fXy1G>imuYgA|K91Z@E{Ck~TumcQ9oSbj$fjZ9%=|RD1Yq&bJK(vnsWr%I@WAiR zs?hGe(H*T&?!l%zuvt_S&&6Yc=N(|#TfV)WEJ?nECU;0S+u9ue#e=zIAy5Ve;Ifme zf%HHJ=F=~M;K>%YCC9?7@fb7dIde!w2if>DXqkb?8$$EsAkk=^m|#_4+nS!{1@JuE zLgj#F&@zh13p$CTFyk&LOR64FPe|dV-U47YL8F~P%V^Jnpk+p4H6T+ClPOvwL(HXP zFj~^>A*9f!KGfD?^aZp99v3i&hBPqbBbXBDLee6NC>GM}sU55c+}D(-80?ES)U?$n zN-Agwdx{170?$Mu+y&<~BxqP*n_Q$tMj|&r*t(9uvW9TXlM%M%pb}GP4ARFz1a|4> z`6)w)fSI3y^f?C@$Q!Lrl)&cqe_es&K#WwJ)KjTsslPMF6<0TKup$;du_Cs^`U0vt2HWg^QegPM;-HYA=z>Bgg9N?wKhV5JxAP~0AN+8gKVd+) z{65}>-yi<7`WmsnQT+4q&)R=R_CJFDi!A>W=HEgx9UO28Rtos?hg#{3!%g%8BNc=C z`VX{YFc@%UU|^u5!ay(#i~xRX1#X1PujhZbuK^$sY^-ebvVn!=R}Yb5>mtMS+U7YuxdQU1h(YyVULrN0yek^zNgWMam! zu(GjpY{32#&VSeTI|u(x{ZG06H8cZQ_J1qLzgr8C{+|>;NBLL0{zmWrul|Du){Gav z{zK>An*ODZ|7J_Ljhi-eZrQr+Z|HwKqW?wtlb65N{y_XUD@^~Q{Bqd8--9G;c5rZjJ7K5! z-Elyj?f^jFu>aEW=?%Xq0cZvW6bg-IWMpDuW`?oXp5Y<>1p3X-^!_M+bR+&~g7cO2 z^53`7SHNFl{6hI3?r=DQLH-h!=nrd%|E2v;dUR1t2**t5fgc8h$Nn#Kv#u^A0t*m$ zIoJQu$-wYHg@2Mj`lx3ze4CDybw`{C4?UG2bebt z9t0v5r1|g3~q;(78KroieuQV zKaK3ye=VpwEqg$9T5yWt`pfT+EGrYV$(fvXGfdnEL43xb1^(Qh%K{^W_uCfOfi*7_ zL?Gb(_yvK#?$2-ST!VYKe*aw{{@?cJYJgTDX!v#i9Zv1H{W&}a0*n>3eur^pTxrM4 zGXLBC`G32g1@z6~?ewo5?{qS(6x&~WVR(FVAR;>*2HtvuoiSOnVS#MYu+l$AUI37P z#eex<@B#Wi?dLndna%$<`}x1f=d{isJnzG>nSjkMX$)ruO;MXTz!}TJMhan)Ojz+$ zfe0&DBnBe%swDs2w`YOcuULNB=Aff1{*#bXz)ad5rrL3?FZXeKtl&Y<4w(=3uwq0 z6Ef#1cebAWm^n2ZbV8q@g`xp8s)sa+t6&BVK~O`5HpT~#BHN;=aex}Bf}QjoN&IYk z+~!1X5aLb@BsNmQU{;)Ut5CWsF_A>Ky{Ws#8me$fS>2m8Z9K9)+x{l29yWm8q$dDG~A!)@L&L4 z{h!fcw$-Wlwa!s>(!wU9GT_LW&QT@IQ6!jU`jp{8y9B+R3b$YW)ecK4@oQA7DjN`h z3jjckVAMeH6jF!{xejCp=rVM4c^F;!7rGneD*hJet^fy3LEvr(;CKxIP32=|&U#>C zfD%ciTwuNlppmPHih?SO`cO)GcrKzeDUUrA;9!Y+p&Aku>4_!f)xyNE9$e~5mF`pE zdLKjqUT7MOrwp|LS4e^tpahr! zEuLDiz+&*l5WZN$qMMl0h2{rBSA({b>s+pnWKYqER7G14@QQpv{4D1AhbP0IpI4K`bYgasoR<;uyf>3#~~+BjP}}F#MxR07C|{ z0|7aKt#NuT+1liQeSXk!*ahjQUF;OX3Q!BhbivG!LYR@BGo%i!&nPxD2v#>?=Gc3f z5fB4*L5+ef^Ibg6MO60rE>t5`703=vhRhL}>10QZ<_IfDbI2d(DGU)7{t1HvV33(Z z3V&hjq!GCweRinbjJoj4l32l^8$c%`r3-;q!>odZ0~6$nLV7Z-9n@j7jxb=eG>}Do z7`94m76bi$%q(~jEdK~1Cv*fIX2lMB4pwI1#prnZ)6I!Lp9W;E$cx=B?m-;pi#|##`_885XSqZjvXNWv6(?FPy_WW z=&}Sh#7~w0S6;F_(8dXHvT8PnM8=M{rRu$g@d}2r^*|Dw^*g^YBEowK^?%R zp%x0Ex2T^nxEKR0xM+mkP=ksDYycj5!8!y8!zAEEYDv1;MIKrLK15bWQ-Wb|GNG5E zjsY-~3uv1K%Vb*_k?$Oyt4p%?qQv1J7GFr@SU zQxC}r12lyW>GtG+OeX;k$EbBcE=zM7v6q@U2X!d3{`?x3}^sS0&V#U&k+ZF4QVE#$t=DK&?)<|Q#Bo%ln5ywo;%tKA^+rS$qF6`9@fR#0; z{Ye8$7Q8s}!fv|{hJ|Ly=kUVd#|s5uNDg>BqG*U66@ZrRCVS%fz0n{D5}MBgdzZIGeE`c2c7$ISWtlvu}ej?G3;0+jTYD$$@ zQZ|4iIiV3y4Wxx$gC%buZD1g6KuR}*Csi4_^l8U%(5E~h)H2AX1wAvGaL6G&ng1e2fC zfb^+k;uxt2GkX0UOiI*rrl=o9eS`weqTdSJ^tJ`Wsab5bhu+=R{6U_douvl*O}%8BFBaI7v~kHDjxV9^K3fj>|MSn)a6SA4W3 z^&KoEyyAa`*a_U`a;cpbeDisR(Gf;Ebqg6QBX4jUX-oUg3ZU7~zNGq6->uZDB~(5(car zk`1`1R{<o?`YKwwp*8yBqmIglK~#;V*j_%0bu|NFbp9a?em*P zjg6>5-(eZpOW=e6(m=zG3*Ne`V;~K7vN}6}gOExLL>}PjN*ZYJ$$~mYNdrShck0yG7zj{qbxGJ^9DU{>G=V!@Eg1!f68TKK+h zWJX5EOrb6_^N?;jkUQ8&;VAFnU|sNom8ksR>w&flCiKrzii~|0x%Q!Kx&Z;e+B~-Ks`eD z6CZtS)=>tEIR=}hjRc>Z;MR9r%=CNkFaSc#ck)z8&yo68D4eVc9%!#EkS>PW3t}t? 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z_+;ej$n}xiBPWf0bZpkxnPZ=Sc+11P9v(c-7!@6r6qOpaD#{l1a@6{$52Bi*K8v~# z)frV4-4eYwnvV&H=@Szcb8pQ3G0((28}pl(uVeD#UStZS+`5SWjJOst-uPGJ z=f?X{%FB`OMJ|4L<-_?CKAzxY@pRA?Sf3-7!dPs4(zx8X&d5hjh-{DUiXIp9tC;4P zZ(=USbjLgs_k7$daY5tn8UO8s3lj?Ck;uT|cNMT!G-wQ3Lx>^N5N6OB^oF(Z>*CkP zzaPIL{-gLU@gK)G#P5u6iT^adHU9JXqw!zGx5a-OFU6mW?})z?-xc2-k6~Pvl{2Ue zx91gZ7-cXRA`MX}i(PMD{&?v|_tD84KRAEN^y}egKYaJb?=P^=3)q(ho|yj|cLfv# zpBCV1^QPAF>>~s2F18f?C)c~#zWIr4B0vO)01+SpM1Tko0U|&IhyW4zKS$ty0ZX&c A+W-In diff --git a/CometLakeFspBinPkg/CometLake1/FspPcds.dsc b/CometLakeFspBinPkg/CometLake1/FspPcds.dsc deleted file mode 100644 index b091516..0000000 --- a/CometLakeFspBinPkg/CometLake1/FspPcds.dsc +++ /dev/null @@ -1,40 +0,0 @@ -## @file -# FSP description for DynamicEx PCDs. -# -# @copyright -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - - ## Specifies the AP target C-state for Mwait during POST phase. - # The default value 0 means C1 state. - # The value is defined as below.

- # @Prompt The specified AP target C-state for Mwait. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 20 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress | 0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength | 0x10000000 - - ## Specifies the base address of the first microcode Patch in the microcode Region. - # @Prompt Microcode Region base address. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - diff --git a/CometLakeFspBinPkg/CometLake1/Include/FirmwareVersionInfoHob.h b/CometLakeFspBinPkg/CometLake1/Include/FirmwareVersionInfoHob.h deleted file mode 100644 index c4aea4b..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/FspInfoHob.h b/CometLakeFspBinPkg/CometLake1/Include/FspInfoHob.h deleted file mode 100644 index aa0c842..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FspInfoHob.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @file - Header file for FSP Information HOB. - - @copyright - Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _FSP_INFO_HOB_H_ -#define _FSP_INFO_HOB_H_ - -extern EFI_GUID gFspInfoGuid; - -#pragma pack (push, 1) - -typedef struct { -UINT8 SiliconInitVersionMajor; -UINT8 SiliconInitVersionMinor; -UINT8 SiliconInitVersionRevision; -UINT8 SiliconInitVersionBuild; -UINT8 FspVersionRevision; -UINT8 FspVersionBuild; -UINT8 TimeStamp [12]; -UINT8 FspVersionMinor; -} FSP_INFO_HOB; - -#pragma pack (pop) - -#endif // _FSP_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/FspUpd.h b/CometLakeFspBinPkg/CometLake1/Include/FspUpd.h deleted file mode 100644 index f97ed67..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FspUpd.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */ - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake1/Include/FspmUpd.h b/CometLakeFspBinPkg/CometLake1/Include/FspmUpd.h deleted file mode 100644 index d63061f..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FspmUpd.h +++ /dev/null @@ -1,3056 +0,0 @@ -/** @file - -Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResistor settings - Indicates RcompResistor settings: CML - 0's means MRC auto configured based on - Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to - provide the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0096 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0097 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0098 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A4 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A6 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A7 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A8 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A9 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00AE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00AF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00B0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00B1 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00B2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00B4 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00B6 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00B7 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00B8 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00B9 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00BA - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00BB - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00BC - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00C0 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00C1 - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00C2 - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00C3 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00C4 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C5 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C6 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C8 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00CA - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00CC - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00CE - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CF - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00D0 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00D1 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00D2 - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00D3 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00D4 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D5 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D6 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D7 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00D8 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00DA - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00DB - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00DC - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00DD - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00DE - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00DF - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00E0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x00E4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x00E8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x00EC - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x00EE - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x00F0 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x00F3 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x00F4 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x00F5 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x00F6 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x00F7 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x00F8 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x00F9 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x00FA - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x00FB - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x00FC - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x00FD - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x00FE - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x00FF - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0100 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0101 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0102 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0105 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x010D - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0115 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0122 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0130 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0134 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0154 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0155 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0156 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0158 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x015C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0160 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01C1 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01C2 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01C3 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01C4 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01C5 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x01C6 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01CA - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01CC - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01CF - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01D0 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01D1 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01D2 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01D3 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01D4 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01DA - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01DB - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[1]; - -/** Offset 0x01DC - Per-core HT Disable - Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, - 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value - of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have - HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1. -**/ - UINT16 PerCoreHtDisable; - -/** Offset 0x01DE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01E0 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01E1 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x01E2 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x01E3 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x01E4 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x01E5 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x01E6 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x01E7 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01E8 - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x01E9 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01EA - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01EC - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01ED - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01EE - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x01EF - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x01F0 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x01F1 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x01F2 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x01F4 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x01F6 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x01F8 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x01F9 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x01FA - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x01FC - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x01FE - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0200 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0201 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0202 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0203 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0204 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0205 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0208 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x020C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0210 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0214 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0218 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0220 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0224 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0228 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x022C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0230 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0238 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0240 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0241 - Intel Speed Optimizer Enable - When enabled this feature automatically overclocks your processor. It changes the - All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AutoEasyOverclock; - -/** Offset 0x0242 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[2]; - -/** Offset 0x0244 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0250 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0251 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x0253 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x0256 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0257 - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0439 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x043A - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x043B - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x043C - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x043E - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0440 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0444 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0448 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0449 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x044A - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x044B - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x044C - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x044D - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x044E -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0450 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0454 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0455 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0456 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0457 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0458 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x045A - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x045B - Enable HD Audio DMIC0 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x045C - Enable HD Audio DMIC1 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x045D - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x045E - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x045F - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0465 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[2]; - -/** Offset 0x0467 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0468 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0469 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x046A - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x046B - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x046C - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x046D - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x046E - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x046F - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0470 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0471 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0472 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0473 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0474 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0475 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0476 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0477 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0478 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0479 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x047A - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x047B - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x047C - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x047D - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x047E - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x047F - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0480 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0481 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0482 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0483 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0484 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0485 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0486 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0487 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0488 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0489 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x048A - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x048B - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x048C - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x048D - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x048E - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x048F - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0490 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0491 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0492 - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x0493 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x0494 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x0495 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x0496 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x0497 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x049A - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x049B - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x049C - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x049D - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x049F - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04A0 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04A1 - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04A2 - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04A5 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x04A6 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04A8 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04AC - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04AD - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04AE - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04B0 - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04B2 - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04B4 - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04B6 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04B7 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04B8 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04B9 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04BA - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04BB -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x04BC - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04BE - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04CA - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04CB - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04CC - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04CD - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04CE - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04CF - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D0 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04D1 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04D2 - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04D3 - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04D8 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04D9 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04DA - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04DB - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04DC - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04DD - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04DE - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04DF - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E0 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04E1 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04E2 - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04E3 - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04E4 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04E5 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04E6 - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04E7 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04E8 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04E9 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04EA - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04EB - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04EC - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04ED - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04EE - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04EF - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F0 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04F1 - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04F2 - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04F3 - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04F4 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04F5 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04F6 - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x04F7 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x04F9 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x04FB - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x04FC - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x04FD - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x04FE - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x04FF - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0500 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x0501 - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x0502 - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x0504 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0505 - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x0506 - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4Mixed2DpcLimit; - -/** Offset 0x0508 - RMT on Fast flow - Enable/Disable RMT on Fast flow. Default: Disabled - $EN_DIS -**/ - UINT8 FastBootRmt; - -/** Offset 0x0509 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl; - -/** Offset 0x050A - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x050B - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x050D - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x050E - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x050F - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x0510 - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control - deprecated -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x0515 - Core VF Point Offset Mode - Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; - 0: Legacy; 1: Selection. - 0:Legacy, 1:Selection -**/ - UINT8 CoreVfPointOffsetMode; - -/** Offset 0x0516 - Core VF Point Offset - Array used to specifies the Offset Voltage applied to the each selected Core VF - Point. This voltage is specified in millivolts. -**/ - UINT16 CoreVfPointOffset[15]; - -/** Offset 0x0534 - Core VF Point Offset Prefix - Sets the CoreVfPointOffset value as positive or negative for corresponding core - VF Point; 0: Positive ; 1: Negative. - 0:Positive, 1:Negative -**/ - UINT8 CoreVfPointOffsetPrefix[15]; - -/** Offset 0x0543 - Core VF Point Ratio - Array for the each selected Core VF Point to display the ration. -**/ - UINT8 CoreVfPointRatio[15]; - -/** Offset 0x0552 - Core VF Point Count - Number of supported Core Voltage & Frequency Point Offset -**/ - UINT8 CoreVfPointCount; - -/** Offset 0x0553 -**/ - UINT8 UnusedUpdSpace8[4]; - -/** Offset 0x0557 -**/ - UINT8 ReservedFspmUpd[1]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0558 -**/ - UINT32 Signature; - -/** Offset 0x055C - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x055D - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x055E - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x055F - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0560 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0561 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0562 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0563 - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x0564 - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x0565 - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x0566 - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x0567 - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0568 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0569 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x056A - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x056B - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x056C - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x056D - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x056E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x056F - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0570 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0571 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x0572 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0573 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0574 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0575 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0589 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x059D - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x05B1 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x05B4 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x05B6 - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x05B8 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x05BA - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x05BB - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x05BC - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x05BD -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x05C0 - Oem T12 Dealy Override - Oem T12 Dealy Override. 0(Default)=Disable 1=Enable - $EN_DIS -**/ - UINT8 OemT12DelayOverride; - -/** Offset 0x05C1 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x05CA - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x05CC - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x05CE - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x05CF - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x05D2 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x05D3 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x05D4 - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x05D5 - ReservedPchPreMemTest - Reserved for Pch Pre-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPreMemTest[16]; - -/** Offset 0x05E5 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05E6 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05E7 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05E8 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05E9 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05EA - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05EB - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05EC - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05ED - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05EE - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05EF - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05F0 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05F1 - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05F2 - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05F3 - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05F4 - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05F5 - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05F6 - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05F7 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05F8 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05F9 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05FA - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05FB - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05FC - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05FD - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05FE - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05FF - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x0600 - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x0601 -**/ - UINT8 ReservedFspmTestUpd[7]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0558 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0608 -**/ - UINT8 UnusedUpdSpace11[6]; - -/** Offset 0x060E -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake1/Include/FspsUpd.h b/CometLakeFspBinPkg/CometLake1/Include/FspsUpd.h deleted file mode 100644 index f1de99d..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FspsUpd.h +++ /dev/null @@ -1,3675 +0,0 @@ -/** @file - -Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0030 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0034 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0038 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0039 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x003A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x003B - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x003C - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x003D - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x003E - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x003F - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0040 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0041 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0042 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0044 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x0046 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0047 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0048 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0049 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x004A - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x004B - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x004F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x0053 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0058 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0060 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0063 - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x0065 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x0068 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0074 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0075 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0076 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0077 - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x0078 - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x0079 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x007A - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x007B - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x007C - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x007D - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0080 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0084 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0088 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0089 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x00C4 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x00C9 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x00CE - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x00D3 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x00DD - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x00E2 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x00E7 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x00EC - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x00ED - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x00EE - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x00F3 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x00F4 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x00FE - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0108 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x0112 - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x011C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0126 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0130 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x013A - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0146 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0147 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0148 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x014A - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x014B - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x014C - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x014E - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x014F - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x0159 -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x015A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0164 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0168 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0169 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x016A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x016B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x016C - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0170 - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0174 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace8[1]; - -/** Offset 0x0176 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x0180 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0188 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0189 - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x018B - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x018D - SPI2 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi2CsPolarity[2]; - -/** Offset 0x018F - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x0191 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x0193 - SPI2 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi2CsEnable[2]; - -/** Offset 0x0195 - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[3]; - -/** Offset 0x0198 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[3]; - -/** Offset 0x019B - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x01A1 - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x01A7 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01AC - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x01B8 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x01BB - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x01BE - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x01CA - Serial IO UART Pin Mux - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 SerialIoUartPinMux[3]; - -/** Offset 0x01CD - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01CE - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x01D1 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x01D2 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x01D3 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x01D4 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x01D5 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x01D6 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x01DE - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x01E6 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x01F6 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x0200 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0201 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0208 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0209 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0211 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0212 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0213 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x0214 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x0215 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0216 -**/ - UINT8 UnusedUpdSpace11[2]; - -/** Offset 0x0218 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x021C - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x021D - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x021E - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x021F - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x022F - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x023F - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x0287 - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x0288 - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x028C - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0290 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x0294 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x0295 - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x0296 - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x0297 - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0298 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0299 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x029A - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x029B - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x029C - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x029D - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x029E - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x02A0 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x02A4 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x02A8 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x02AC - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x02AD -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x02B0 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x02B5 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x02B6 -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x02B8 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x02BC - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x02BD -**/ - UINT8 UnusedUpdSpace14[3]; - -/** Offset 0x02C0 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x02C4 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x02C8 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x02C9 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x02CA - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x02CB - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x02CC - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x02CD - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x02CE - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x02CF - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x02D0 - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x02D1 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x02D2 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x02D3 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x02D4 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x02D5 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x02D6 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x02EE - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x02FE - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x030E - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x0326 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x033E - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x036F - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping - CPU and 1 for PCH-H Series. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x0370 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x037B -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x037C - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0386 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0390 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0391 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0392 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x0393 - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x0394 - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x0396 - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0397 - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x03A2 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x03B1 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x03B4 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x03B5 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x03B6 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03CE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03E6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x0416 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x042E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0446 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x045E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0476 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x048E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x04A6 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04D6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04EE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x051A - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x054A - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0562 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x057A - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x0592 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05AA - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05C2 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x060A - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, - the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x060F - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the - default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0614 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0615 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0616 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0617 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0618 - Teton Glacier Cycle Router - Specify to which cycle router Teton Glacier is connected, it is valid only when - Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x061A - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x061B - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x061C - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic - Configuration. Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x061D - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x061F - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0622 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0623 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0624 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0625 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0626 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x0627 - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x0628 - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x0629 - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x062A - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x062B - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x062C - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x062D - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x062E - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0630 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0631 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0632 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0635 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0636 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0637 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x0638 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0639 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0641 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0649 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0651 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0659 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0661 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0669 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0671 -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x0672 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x0682 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x068A - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x068B - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x068C - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x068D - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x068E - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x068F - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x0692 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x0693 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0694 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0695 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x069F - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06A0 - Set HS400 Tuning Data Valid - Deprecated - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06A1 - Rx Strobe Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06A2 - Tx Data Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06A3 - I/O Driver Strength - Deprecated - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06A4 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06A5 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06A6 - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06A7 - PCH eSPI Link Configuration Lock (SBLCL) - Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves - addresseses from range 0x0 - 0x7FF - $EN_DIS -**/ - UINT8 PchEspiLockLinkConfiguration; - -/** Offset 0x06A8 - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06A9 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06B0 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06B1 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06B2 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x06B3 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x06B4 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x06B7 - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x06B8 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x06B9 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x06BA - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x06BB - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x06BC - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x06BD - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x06BE - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x06BF - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x06C0 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x06C1 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x06C2 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x06C3 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x06C5 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x06C8 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x06C9 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x06CB - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x06CD - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x06CF -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x06D0 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x06D2 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x06D3 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x06E3 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x06ED - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x06EE - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x06F1 -**/ - UINT8 UnusedUpdSpace19[3]; - -/** Offset 0x06F4 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x06F8 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x06F9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x06FB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default - = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x074C - Number of Coefficients to be used - The number of coefficients to be used for equalization, default value is 3 -**/ - UINT8 PcieNumOfCoefficients; - -/** Offset 0x074D - GPIO RCOMP Community Clock Gating - 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock - local clock gating, default value is 1 - $EN_DIS -**/ - UINT8 GpioPmRcompCommunityLocalClockGating; - -/** Offset 0x074E - Enable SD Card Write Protect Pin - Enable/disable SD Card Write Protect Pin. - $EN_DIS -**/ - UINT8 ScsSdCardWpPinEnabled; - -/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x0757 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control - 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x075C - ReservedPchPostMem - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[3]; - -/** Offset 0x075F -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0760 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0780 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0784 -**/ - UINT8 UnusedUpdSpace21[4]; - -/** Offset 0x0788 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0790 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0798 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0799 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x079A -**/ - UINT8 UnusedUpdSpace22[6]; - -/** Offset 0x07A0 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x07A8 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x07B0 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07B1 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07B2 -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x07B4 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07B8 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07BA - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07BB - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07BC -**/ - UINT8 UnusedUpdSpace24[3]; - -/** Offset 0x07BF -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07C0 -**/ - UINT32 Signature; - -/** Offset 0x07C4 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07C5 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07C6 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07C7 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07C8 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07C9 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07CD - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07CE - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07CF - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07D0 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07D1 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07D2 - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07D3 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07DE - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07DF - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07E0 - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07E1 - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07E2 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07E3 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07E4 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07E5 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07E6 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07E7 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07E8 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07E9 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07EA - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07EB - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07ED - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07EE - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07EF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07F0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07F1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07F2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07F3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07F4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07F5 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07F6 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07F7 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07F8 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07F9 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07FA - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07FB - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07FC - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0800 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0802 - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x0803 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0804 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x0805 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x0806 -**/ - UINT8 UnusedUpdSpace25[2]; - -/** Offset 0x0808 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0810 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x0814 - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0816 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable, 2: Auto / Silicon default - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0818 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x081B - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x081C - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x081D - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x081E - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x081F - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0820 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0821 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0822 - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0824 - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0825 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0827 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0828 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0829 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x082A - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x082B - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x082C - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x082D - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x082E - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x082F - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0830 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0831 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0832 - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x0833 - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x086B -**/ - UINT8 UnusedUpdSpace26; - -/** Offset 0x086C - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x087A -**/ - UINT8 UnusedUpdSpace27[2]; - -/** Offset 0x087C - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0880 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0884 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0888 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x088C - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x08A8 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x08AC - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x08B0 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x08B2 - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x08B3 - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x08B4 - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x08B5 - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver - @deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08BA - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08BB - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08BC - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08BF - Ratio Limit Num Core 0 - Ratio Limit Num Core0: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore0; - -/** Offset 0x08C0 - Ratio Limit Num Core 1 - Ratio Limit Num Core1: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore1; - -/** Offset 0x08C1 - Ratio Limit Num Core 2 - Ratio Limit Num Core2: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore2; - -/** Offset 0x08C2 - Ratio Limit Core 3 - Ratio Limit Num Core3: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore3; - -/** Offset 0x08C3 - Ratio Limit Num Core 4 - Ratio Limit Num Core4: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore4; - -/** Offset 0x08C4 - Ratio Limit Num Core 5 - Ratio Limit Num Core5: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore5; - -/** Offset 0x08C5 - Ratio Limit Num Core 6 - Ratio Limit Num Core6: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore6; - -/** Offset 0x08C6 - Ratio Limit Num Core 7 - Ratio Limit Num Core7: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore7; - -/** Offset 0x08C7 - Dual Tau Boost - Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 DualTauBoost; - -/** Offset 0x08C8 - ITBMT 3.0 Runtime Periodic SMM timer - Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic - SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, - 6 - 32 sec, 7 - 64 sec. -**/ - UINT8 ItbmPeriodicSmmTimer; - -/** Offset 0x08C9 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[9]; - -/** Offset 0x08D2 - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08D3 - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): - Enable EOP message - $EN_DIS -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08D4 - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08D5 -**/ - UINT8 UnusedUpdSpace28; - -/** Offset 0x08D6 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08D8 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08DA - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08DB - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x096C - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x0A14 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A75 - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A76 - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A77 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A79 - ReservedPchPostMemTest - Reserved for Pch Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPostMemTest[16]; - -/** Offset 0x0A89 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A8A - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0A8B -**/ - UINT8 UnusedUpdSpace29; - -/** Offset 0x0A8C - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0AA4 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x0AA5 -**/ - UINT8 UnusedUpdSpace30[3]; - -/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x0ABC - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0ABD -**/ - UINT8 UnusedUpdSpace31[3]; - -/** Offset 0x0AC0 - LogoPixelHeight Address - Address of LogoPixelHeight -**/ - UINT32 LogoPixelHeight; - -/** Offset 0x0AC4 - LogoPixelWidth Address - Address of LogoPixelWidth -**/ - UINT32 LogoPixelWidth; - -/** Offset 0x0AC8 -**/ - UINT8 UnusedUpdSpace32[4]; - -/** Offset 0x0ACC -**/ - UINT8 ReservedFspsTestUpd[4]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07C0 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0AD0 -**/ - UINT8 UnusedUpdSpace33[6]; - -/** Offset 0x0AD6 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake1/Include/FsptUpd.h b/CometLakeFspBinPkg/CometLake1/Include/FsptUpd.h deleted file mode 100644 index d01188d..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/FsptUpd.h +++ /dev/null @@ -1,180 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) - 0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 PcdSerialIoUartPinMux; - -/** Offset 0x0059 - PcdLpcUartDebugEnable - Enable to initialize LPC Uart device in FSP. - 0:Disable, 1:Enable -**/ - UINT8 PcdLpcUartDebugEnable; - -/** Offset 0x005A - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x005B - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x005C - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x005D -**/ - UINT8 UnusedUpdSpace1[7]; - -/** Offset 0x0064 -**/ - UINT8 ReservedFsptUpd1[20]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0078 -**/ - UINT8 UnusedUpdSpace2[6]; - -/** Offset 0x007E -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake1/Include/GpioConfig.h b/CometLakeFspBinPkg/CometLake1/Include/GpioConfig.h deleted file mode 100644 index 57f0774..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/GpioConfig.h +++ /dev/null @@ -1,329 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - -@copyright - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 9; - UINT32 RsvdBits : 10; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, - GpioPadModeNative5 = 0xB -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Configuration options for GPIO termination setting -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. - By default GPIO pads will be locked unless GPIO lib is explicitly - informed that certain pad is to be left unlocked. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controlled - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock - an already locked pad upon request for reconfiguration -**/ -typedef enum { - /** - Perform default action - - if pad is an GPO, lock configuration but leave output unlocked - - if pad is an GPI, lock everything - - if pad is in native, lock everything -**/ - GpioLockDefault = 0x0, - GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked - GpioPadConfigLock = 0x1, ///< Lock Pad configuration - GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked - GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked - GpioPadLock = 0x5 ///< Lock both Pad configuration and output control -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h b/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h deleted file mode 100644 index 0404b06..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Sample enum definitions for GPIO table. - - @copyright - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/HobUsageDataHob.h b/CometLakeFspBinPkg/CometLake1/Include/HobUsageDataHob.h deleted file mode 100644 index 8b97afa..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/HobUsageDataHob.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Definitions for Hob Usage data HOB - - @copyright - Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _HOB_USAGE_DATA_HOB_H_ -#define _HOB_USAGE_DATA_HOB_H_ - -extern EFI_GUID gHobUsageDataGuid; - -#pragma pack (push, 1) - -/** - Hob Usage Data Hob - - Revision 1: - - Initial version. -**/ -typedef struct { - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - UINTN FreeMemory; -} HOB_USAGE_DATA_HOB; - -#pragma pack (pop) - -#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/MemInfoHob.h b/CometLakeFspBinPkg/CometLake1/Include/MemInfoHob.h deleted file mode 100644 index 1c94e8e..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/MemInfoHob.h +++ /dev/null @@ -1,263 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; - -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/SmbiosCacheInfoHob.h b/CometLakeFspBinPkg/CometLake1/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index 3623b55..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 - // - // Add for smbios 3.1.0 - // - UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/Include/SmbiosProcessorInfoHob.h b/CometLakeFspBinPkg/CometLake1/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index f28250c..0000000 --- a/CometLakeFspBinPkg/CometLake1/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - - @copyright - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake1/README.md b/CometLakeFspBinPkg/CometLake1/README.md deleted file mode 100644 index b0aafbe..0000000 --- a/CometLakeFspBinPkg/CometLake1/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# CometLakeFspBinPkg/CometLake1 -These FSP binaries are intended to be used with 10th Generation Intel® Core™ U-Series/H-Series processors and chipsets formerly known as Comet Lake with support for LPDDR3 & DDR4 memory. Please consult CometLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use. diff --git a/CometLakeFspBinPkg/CometLake1/SampleCode/Vbt/Vbt.bin b/CometLakeFspBinPkg/CometLake1/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index e801e45246d84e43bc6439b6fdda257a20675aa9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKU2GIp6h5=FzjtP~vr{7573<+Auv=)EEwExOakjgyUAnN_ZfQz1=>of8!$NC+ zv=~g+q){G}?1LIKD19L+FXEH&4c|yilxTuaModgle38hD0U6Kyw2LKa7a}NzZ};4D z?wLE^oclBPo>?={(T};F-RXEwC)y~03a0~pDsM+eDw7*Z#{1(#9qCM>2Y-S`U?Ony z3P6G58pNooMpK6;iluO0glN;aV`T4eskkv&96vZQGK$$m3gi3s6-&jjJrl(O<_4aL zqroY$j>+Lt0e4Ow+FKlJLn2bCHAXkLY}$+%-PlThHM)gNwJjQJ+w!EulAVdnj%+F& z?@wiRVx|w1sa!ml>)g?i-i_J5On0gy)!&(v*nBq!MpRGU+@M_>i@XFxSz=`0L zK||1FKpDIMP5=!60c0Zx864X<2l>`{!5uU_b0B)&v^Ar#4Pt|fd5~qV;Hdc0}L z99jm|=yC9k*=&v7%mF}u1033h(F|?2nB9z&^-z^V%b+{Z4poM3yP04R8Nk0aGhO$) z;5mRBFVj;=8{mL50O03TIPPnN3?GK0yaQh2w?dQiJg7c|oKJ@RBu7ZTbusv!Zr}wClR= z%Tv{1E|7awvM+%av;|#%&@HhZw$q!)d)sGLn0?s=pr4X>m;x4{cie^|&MivQvFrnI zhpbDU_PI6-^}l%~Wb6!&iu?r+gA1N(+_C!qre%zoyu{BMS6vU-u<8%Xha+%jBe0?y zF8az9y!4pt&9AcVZM-|rW2gYvxzpxr4eIXKgM- zsGC39t2f_jg&T={{8o=?pCMSz$Xmc4VE86ePBHc|!>^h0BV)fZ3<%0BiA_s*T2elf*cTFBmXtpv#``hiSDx~-PCp*>E3f$3>wc+8ag`mHxH6@n zMtu2zb?fLPynSL~)07YxofDBCbS%v8GHXa0W7F25 zNb^No{?ZJE2GHWLRt+ADSq#D0G;gI<6ec(ghW15!p*F#ZUQji4w0=GYy3w%3DOac_ zhAHd~$(no%16Og~0mDZdr!Mt|)@p+%sxfdCx5=Qn&(;t__tToX_iU@CovSjqtt?3# zaMd!B`&SN}>4iqMt76ZEF_IPYe5Fuo8Hb}SmDzl#QB%>L3z|)5#mr*GvZt0_gxkxr zqi0tWLzB^W0Ag@e%v?sCb-2yA}quNjsmPDX76- zD`zxf;AuG$?siR@43fp*!Ww#UB?PlsT&{|0qS}iJy^j<_*|XJL4~xH>j<#~}g{{rn zU~_dYc&M{tps$~$-;0O_`7+e!WjRodfi_YjhIChUD7)uyv9xo~q2m9bVs&t_a{a5| z-hQ6)_%rve)EB_902^ZPMi&K{qU?Sb9bg66z`X-M^RyLPpuE_GdjVQh4vx*^!7#1K UnEQCS?|PH{@x9oZ_y?~21+7}z9{>OV diff --git a/CometLakeFspBinPkg/CometLake1/SampleCode/Vbt/Vbt.bsf b/CometLakeFspBinPkg/CometLake1/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index 30ec8b8..0000000 --- a/CometLakeFspBinPkg/CometLake1/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11683 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Coffeelake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from CFL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x01, "Pin-Pair #1" - Selection 0x02, "Pin-Pair #2" - Selection 0x03, "Pin-Pair #3" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Coffeelake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if theres no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel Rapid Memory Power Management (RMPM)\r\n" - "2. Intel Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop CFL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec b/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec deleted file mode 100644 index 1c0b637..0000000 --- a/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec +++ /dev/null @@ -1,29 +0,0 @@ -## @file -# Component description file for CometLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = CometLakeFspBinPkg - PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 - PACKAGE_VERSION = 1.02 - -[Includes] - Include - -[Guids] - gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }} - -[Ppis] - gEfiReadyToInstallPciEnumerationCompleteProtocolGuid = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }} - gEfiReadyToInstallEventReadyToBootGuid = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }} - gFspReadyToInstallEventEndOfFirmwareGuid = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }} - gEndOfFspS3NotifyGuid = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }} - gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }} diff --git a/CometLakeFspBinPkg/CometLake2/Fsp.bsf b/CometLakeFspBinPkg/CometLake2/Fsp.bsf deleted file mode 100644 index b86b588..0000000 --- a/CometLakeFspBinPkg/CometLake2/Fsp.bsf +++ /dev/null @@ -1,4862 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "CMLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gPlatformFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize 1 bytes $_DEFAULT_ = 0x0C - $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort 1 bytes $_DEFAULT_ = 0x99 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 10 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGpioData 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xD0000000 - $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xCF000000 - $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x001 - $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MemoryTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableCltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableOltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhPrevention 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 - $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A - $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B - $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RhActProbability 1 bytes $_DEFAULT_ = 0xB - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr 2 bytes $_DEFAULT_ = 0xDE - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x30 - $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping 1 bytes $_DEFAULT_ = 0xAA - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhSolution 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax 1 bytes $_DEFAULT_ = 0x69 - $gPlatformFspPkgTokenSpaceGuid_TsodEventMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodThigMax 1 bytes $_DEFAULT_ = 0x5D - $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_GdxcEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_FivrFaults 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 - $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnBER 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FastBootRmt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x40 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 - Skip 9 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 - $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis 4 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01 - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 4 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 8 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 34 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Reserved2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonSlope1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonOffset1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 8 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity 2 bytes $_DEFAULT_ = 0x00, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x02 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 12 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 3 bytes $_DEFAULT_ = 0x08, 0x08, 0x08 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 3 bytes $_DEFAULT_ = 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux 3 bytes $_DEFAULT_ = 0, 0, 0 - $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F - $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters 10 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x06, 0x08, 0x02, 0x0A - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x08, 0x0C, 0x08, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SlpS0Override 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem 3 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - Skip 8 bytes - $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload 4 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF - $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0F - $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4B - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 16 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux - Selection 0 , " GPIO C8 to C11" - Selection 1 , " GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RhSolution - Selection 0 , "Hardware RHP" - Selection 1 , "2x Refresh" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration - Selection 0 , "IPU Camera" - Selection 1 , "IPU Gen" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit - Selection 0 , "BIT6" - Selection 1 , "BIT7" - Selection 2 , "BIT8" - Selection 3 , "BIT9" - Selection 4 , "BIT10" - Selection 5 , "BIT11" - Selection 6 , "BIT12" - Selection 7 , "BIT13" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType - Selection 0 , "1DPC" - Selection 1 , "2DPC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl - Selection 0 , "Disabled" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" - Selection 4 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , " HALT loop" - Selection 2 , " MWAIT loop" - Selection 3 , " RUN loop" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug - Selection 0 , "No Change" - Selection 1 , "DCI OOB" - Selection 2 , "USB2 DbC" - Selection 3 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode - Selection 0 , "SerialIoUartDisabled" - Selection 1 , "SerialIoUartPci" - Selection 2 , "SerialIoUartHidden" - Selection 3 , "SerialIoUartCom" - Selection 4 , "SerialIoUartSkipInit" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode - Selection 0 , " 2T" - Selection 1 , " 1T" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType - Selection 0 , " VC0" - Selection 1 , " VC1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0Override - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent - Selection 0 , "Disabled" - Selection 1 , "Enabled (DCI OOB+[DbC])" - Selection 2 , "Enabled (DCI OOB)" - Selection 3 , "Enabled (USB3 DbC)" - Selection 4 , "Enabled (XDP/MIPI60)" - Selection 5 , "Enabled (USB2 DbC)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency - Selection 100000000 , "100Hz" - Selection 125000000 , "125Hz" - Selection 167000000 , "167Hz" - Selection 250000000 , "250Hz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode - Selection 0 , " Disable" - Selection 1 , "Target Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BdatTestType - Selection 0 , "Rank Margin Tool" - Selection 1 , "Margin2D" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" - Selection 30 , "30" - Selection 34 , "34" - Selection 40 , "40" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme - Selection 0 , " Single Range Output" - Selection 1 , " ToPA Output" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate - Selection 0 , "Disable" - Selection 1 , "1 CMD" - Selection 2 , "2 CMDS" - Selection 3 , "3 CMDS" - Selection 4 , "4 CMDS" - Selection 5 , "5 CMDS" - Selection 6 , "6 CMDS" - Selection 7 , "7 CMDS" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt - Selection 0 , "Msix" - Selection 1 , "Msi" - Selection 2 , "Legacy" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh - Selection 0 , " Active low" - Selection 1 , " Active high" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize - Selection 0 , "32MB" - Selection 1 , "288MB" - Selection 2 , "544MB" - Selection 3 , "800MB" - Selection 4 , "1024MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow - Selection 0 , " Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Refresh2X - Selection 0 , "Disable" - Selection 1 , "Enabled for WARM or HOT" - Selection 2 , "Enabled HOT only" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CnviMode - Selection 0 , "Disable" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength - Selection 0 , "33 Ohm" - Selection 1 , "40 Ohm" - Selection 2 , "50 Ohm" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode - Selection 0 , " Disabled" - Selection 1 , " Dynamic Configuration" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RefClk - Selection 0 , "133MHz" - Selection 1 , "100MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize - Selection 0 , "Default" - Selection 1 , " 1 Byte" - Selection 2 , " 1 KB" - Selection 3 , " Max value" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnableSgx - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Software Control" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck - Selection 0 , "Disable" - Selection 1 , "L1" - Selection 2 , "L2" - Selection 3 , "Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber - Selection 0 , "UART0" - Selection 1 , "UART1" - Selection 2 , "UART2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1400 , "1400" - Selection 1600 , "1600" - Selection 1800 , "1800" - Selection 1867 , "1867" - Selection 2000 , "2000" - Selection 2133 , "2133" - Selection 2200 , "2200" - Selection 2400 , "2400" - Selection 2600 , "2600" - Selection 2667 , "2667" - Selection 2800 , "2800" - Selection 2933 , "2933" - Selection 3000 , "3000" - Selection 3200 , "3200" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix - Selection 0 , "Positive" - Selection 1 , "Negative" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear - Selection 0 , " Disable ME Unconfig On Rtc Clear" - Selection 1 , " Enable ME Unconfig On Rtc Clear" - Selection 2 , " Cmos is clear" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse - Selection 0 , " PchSfpw4Clk" - Selection 1 , " PchSfpw6Clk" - Selection 2 , " PchSfpw8Clk" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 3 , "512 MB" - Selection 7 , "1024 MB" - Selection 15 , " 2048 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency - Selection 4 , " 96MHz" - Selection 3 , " 48MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode - Selection 0 , "Legacy" - Selection 1 , "Selection" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode - Selection 0 , " Disable" - Selection 1 , " Target Debugger Mode" - Selection 2 , " Host Debugger Mode" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Comet Lake Platform" -EndInfoBlock - -Page "System Agent 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, - Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, - Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, - Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, - Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's" - Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "0: Disable, 1: Enable (Default) timeout check for HECI" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, - Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX, - Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX, - Help "Root port Index number to indicate which PCIe root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, - Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, - Help "0:IPU Camera, 1:IPU Gen Default is 0" - Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, - Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" - Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, - Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1." - "Valid range: 0x00 ~ 0x1FF" - Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." - Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS, - Help "Program Cache Attributes; 0: Program; 1: Disable Program." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, - Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, - Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, - Help "Ring voltage mode; 0: Adaptive; 1: Override." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, - Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, - Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" - "Valid range: 0x0A ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control" - Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, - Help "IsTPMPresence default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS, - Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, - Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms" - Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, - Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " -EndPage - -Page "System Agent 2" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "Enable/disable Device 4" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, - Help "Central Write Buffer feature configurable and disabled by default" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS, - Help "Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, - Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, - Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution." - Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS, - Help "0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS, - Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, - Help "DEPRECATED" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, - Help "Address of Blt buffer" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, - Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, - Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "DEPRECATED" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, - Help "Enable or Disable TXT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS, - Help "@deprecated SkipMpInit has been moved to FspmUpd" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX, - Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, - Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, - Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, - Help "Pointer CPU BIST Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Pointer for CpuMpPpi" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, - Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, - Help "Reserved for CPU Post-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS, - Help "Platform specific common policies that used by several silicon components. CSM status flag." - EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, - Help "The address of the table of SVID SDID to customize each SVID SDID entry." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, - Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, - Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX, - Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX, - Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX, - Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX, - Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy from 0 to 64ms" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0x00 ~ 0x64" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS, - Help "@deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX, - Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX, - Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable, 2: Auto / Silicon default" - Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio, Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, - Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, - Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xF9F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, - Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, - Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, - Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, - Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, - Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS, - Help "@deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS, - Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C3 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0, "Ratio Limit Num Core 0", HEX, - Help "Ratio Limit Num Core0: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1, "Ratio Limit Num Core 1", HEX, - Help "Ratio Limit Num Core1: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2, "Ratio Limit Num Core 2", HEX, - Help "Ratio Limit Num Core2: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3, "Ratio Limit Core 3", HEX, - Help "Ratio Limit Num Core3: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4, "Ratio Limit Num Core 4", HEX, - Help "Ratio Limit Num Core4: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5, "Ratio Limit Num Core 5", HEX, - Help "Ratio Limit Num Core5: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6, "Ratio Limit Num Core 6", HEX, - Help "Ratio Limit Num Core6: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7, "Ratio Limit Num Core 7", HEX, - Help "Ratio Limit Num Core7: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, - Help "Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer, "ITBMT 3.0 Runtime Periodic SMM timer", HEX, - Help "Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, 6 - 32 sec, 7 - 64 sec." - "Valid range: 0x00 ~ 0x07" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" -EndPage - -Page "Memory Reference Code 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, - Help "Indicates RcompResistor settings: CML - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, - Help "Time Measure: 0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, - Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." - Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, - Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." - Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100" - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, - Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, - Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, - Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B." - Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, - Help "This option enables data scrambling in memory." - Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, - Help "100MHz, 133MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34" - "Valid range: 0x00 ~ 0x22" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX, - Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, - Help "Margin Limit Check. Choose level of margin check" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS, - Help "Enables/Disable MRC Safe Config" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, - Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." - Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, - Help "Enables/Disable Early Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, - Help "Enables/Disable SenseAmp Offset Training" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Early ReadMPR Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, - Help "Enables/Disable Read MPR Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, - Help "Enables/Disable Receive Enable Training" - Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, - Help "Enables/Disable Jedec Write Leveling" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Write Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Read Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, - Help "Enables/Disable Dimm ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, - Help "Enables/Disable DIMM RON Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, - Help "Enables/Disable Write Drive Strength/Equalization 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, - Help "Enables/Disable Write Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, - Help "Enables/Disable Read ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, - Help "Enables/Disable Read Equalization Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, - Help "Enables/Disable Read Amplifier Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Read Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, - Help "Enables/Disable Command Voltage Centering" - Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, - Help "Enables/Disable Late Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, - Help "Enables/Disable Round Trip Latency Training" - Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, - Help "Enables/Disable Turn Around Timing Training" - Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, - Help "Enables/Disable Memory Test" - Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, - Help "Enables/Disable DIMM SPD Alias Test" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, - Help "Enables/Disable Receive Enable Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, - Help "Enables/Disable Retrain Margin Check" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, - Help "Enables/Disable Write Drive Strength Up/Dn independently" - Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, - Help "Enables/Disable ECC Support" - Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, - Help "Enables/Disable Memory Remap" - Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, - Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." - Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, - Help "Enables/Disable Enhanced Interleave support" - Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS, - Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed." - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, - Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, - Help "Enables/Disable Extern Therm Status" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Closed Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Open Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS, - Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS, - Help "Enables/Disable RAPL PL Lock" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 2 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 1 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, - Help "Enables/Disable SelfRefresh Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature" - Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS, - Help "Enables/Disable RH Prevention" - Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, - Help "Enables/Disable Exit On Failure (MRC)" - Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS, - Help "Enables/Disable LPDDR Thermal Sensor" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, - Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6" - "Valid range: 0x0000 ~ 0x3FFF" - Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, - Help "Base reference clock value, in Hertz(Default is 125Hz)" - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, - Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX, - Help "Energy Scale Factor, Default is 4" - "Valid range: 0x01 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, - Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, - Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" - "Valid range: 0x00 ~ 0x7D0" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, - Help "Enable/Disable CMD Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, - Help "Enable/Disable CMD Drive Strength and Tx Equalization" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, - Help "Enable/Disable CMD Normalization" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, - Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" - EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX, - Help "RH Activation Probability, Probability value is 1/2^(inputvalue)" - "Valid range: 0x01 ~ 0xF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX, - Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX, - Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX, - Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX, - Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, - Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX, - Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, - Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" - Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, - Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" - Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, - Help "Enable/disable(default) Energy Performance Gain." - Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution, - Help "Type of method used to prevent Row Hammer. Default is Hardware RHP" - Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, - Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." - Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, - Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, " TcritMax", HEX, - Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax" - "Valid range: 0x0 ~ 0x7F" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS, - Help "Disable:Comparator mode.\n Enable:Interrupt mode" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS, - Help "Disable:Active LOW.\nEnable:Active HIGH" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS, - Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS, - Help "Disable:Event output disable.\nEnable:Event output enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS, - Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS, - Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS, - Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX, - Help "Thigh = ThighMax (Default is 93)" - "Valid range: 0x0 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS, - Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit." - Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS, - Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh." - EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, - Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, - Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC MOT enable", &EN_DIS, - Help "GDXC MOT enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS, - Help "Fivr Faults; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS, - Help "Fivr Efficiency Management; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, - Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" - Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, - Help "Enables/Disable LpDdrDqDqsReTraining" - EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, - Help "This option configures Post Code Output Port" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, - Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" - "Valid range: 0 ~ 0x20" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX, - Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation." - "Valid range: 0 ~ 0x20" - Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, - Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs." - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS, - Help "Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. Disable=0, Enable(Default)=1" - Combo $gPlatformFspPkgTokenSpaceGuid_FastBootRmt, "RMT on Fast flow", &EN_DIS, - Help "Enable/Disable RMT on Fast flow. Default: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS, - Help "Reserved FspmConfig CFL" - Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, - Help "Run Base Memory Test on Warm Boot" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX, - Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS, - Help "Enables/Disable the MRC training on warm boot" - Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, - Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, - Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, - Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "deprecated" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, - Help "Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; 0: Legacy; 1: Selection." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, - Help "Array used to specifies the Offset Voltage applied to the each selected Core VF Point. This voltage is specified in millivolts." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, - Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, - Help "Array for the each selected Core VF Point to display the ration." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX, - Help "Number of supported Core Voltage & Frequency Point Offset" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, - Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX, - Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX, - Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX, - Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX, - Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX, - Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86." - "Valid range: 0x00 ~ 0x56" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX, - Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX, - Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX, - Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX, - Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX, - Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX, - Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX, - Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX, - Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX, - Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX, - Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX, - Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, - Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, - Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, - Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, - Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" -EndPage - -Page "PCH 1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, - Help "Select SerialIo Uart Controller mode" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, - Help "Set default Parity." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, - Help "Set default stop bits." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, - Help "Enables UART hardware flow control, CTS and RTS lines." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, "PcdSerialIoUartPinMux - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, - Help "Enable to initialize LPC Uart device in FSP." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity, "SPI0 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity, "SPI1 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity, "SPI2 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable, "SPI0 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable, "SPI1 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable, "SPI2 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, - Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, - Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, - Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, - Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, - Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, - Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, - Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, - Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, - Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS lines." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux, "Serial IO UART Pin Mux", HEX, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, - Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS, - Help "Enable/disable eMMC Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS, - Help "Enable eMMC HS400 Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS, - Help "Enable/disable SD Card Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0x17" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0x17" - Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, - Help "Enable/disable TCO IRQ" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, - Help "To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting" - Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, - Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, - Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, - Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, - Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, - Help "0: Disable, 1: Enable (Default) Azalia controller" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "0: Disable, 1: Enable (Default) ISH Controller" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, - Help "Enable PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, - Help "PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, - Help "Enables override of recommended LTR values for xHCI" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC0 link. Muxed with SNDW4." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask, "PTM for PCIE RP Mask", HEX, - Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask, "DPC for PCIE RP Mask", HEX, - Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask, "DPC Extensions PCIE RP Mask", HEX, - Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, - Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, - Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" - "Valid range: 0x00 ~ 0x009C4000" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Master and Slave BME enabled", &EN_DIS, - Help "PCH eSPI Master and Slave BME enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom, "PCH SATA use RST Legacy OROM", &EN_DIS, - Help "Use PCH SATA RST Legacy OROM when CSM is Enabled" - EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX, - Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, - Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Pointer." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Length." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled, "Enable Ufs Controller", &EN_DIS, - Help "Enable/disable Ufs 2.0 Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, - Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, - Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, - Help "Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, "SdCard power enable polarity", &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, - Help "Choose SD_PWREN# polarity" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, - Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, - Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode", &EN_DIS, - Help "This option enables or disables espi lgmr" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, - Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, - Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, - Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl, "SLP_S0 VM Dynamic Control", &EN_DIS, - Help "SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport, "SLP_S0 VM 0.70V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport, "SLP_S0 VM 0.75V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, - Help "0: built-in device, 1:slot" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, - Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, - Help "Number of ClkReq signal assigned to ClkSrc" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, - Help "Enable/Disable PCIE RP Access Control Services Extended Capability" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, - Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, - Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, - Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &EN_DIS, - Help "Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping CPU and 1 for PCH-H Series. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel, "USB LFPS Filter selection", HEX, - Help "For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS, - Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, - Help "Original LPC only decodes one byte of port 80h." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, - Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, - Help "Enable SMBus ARP support." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, - Help "The number of elements in the RsvdSmbusAddressTable." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, - Help "SMBUS Base Address (IO space)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, - Help "Size of PCIe IMR in megabytes" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, - Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, - Help "0:Disable, 1:Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection, "Root port number for IMR.", HEX, - Help "Root port number for IMR." - "Valid range: 0x00 ~ 0x18" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, - Help "Enable SMBus Alert Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS, - Help "Enables UART hardware flow control, CTS and RTS lines." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, - Help "Set default Parity." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, - Help "Set default stop bits." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem, "ReservedPchPreMem", &EN_DIS, - Help "Reserved for Pch Pre-Mem" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters, "PCH USB3 RX HSIO Tuning parameters", HEX, - Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX, - Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS, - Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once." - Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, - Help "Disable or Enable Smbus dynamic power gating." - Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, - Help "Set 1 to clear WDT status, then disable and lock WDT registers." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, - Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS, - Help "Reserved for Pch Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, - Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" - Combo $gPlatformFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable message check." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, - Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." - Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable KT device." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR, "Teton Glacier Cycle Router", HEX, - Help "Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system " - "Valid range: 0x0 ~ 0x02" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, - Help "Enables Isolated Memory Region for PCIe." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, - Help "Selects PCIE root port number for IMR feature." - "Valid range: 0x0 ~ 23" - Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, "Teton Glacier Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, - Help "Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0Override, "SLP_S0# Override", &gPlatformFspPkgTokenSpaceGuid_SlpS0Override, - Help "Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, "S0ix Override Settings", &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, - Help "Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\nReminder: DCI OOB (aka BSSB) uses CCA probe.\nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for DbC", &EN_DIS, - Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, - Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Device Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, - Help "Enable RAID Alternate ID." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS, - Help "Deprecated" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, - Help "Deprecated" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, - Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, - Help "Thermal Sensor 1 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, - Help "Thermal Sensor 2 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, - Help "Thermal Sensor 3 Target Width." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode, "Enable xHCI Compliance Mode", &EN_DIS, - Help "Compliance Mode can be enabled for testing through this option but this is disabled by default." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, - Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH Sata Rst CPU Attached Storage", &EN_DIS, - Help "CPU Attached Storage" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, - Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, - Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, - Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, - Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients, "Number of Coefficients to be used", HEX, - Help "The number of coefficients to be used for equalization, default value is 3" - "Valid range: 0x0 ~ 0x5" - Combo $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating, "GPIO RCOMP Community Clock Gating", &EN_DIS, - Help "0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock local clock gating, default value is 1" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable SD Card Write Protect Pin", &EN_DIS, - Help "Enable/disable SD Card Write Protect Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, - Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS, - Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem, "ReservedPchPostMem", &EN_DIS, - Help "Reserved for Pch Post-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX, - Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, - Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, - Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, - Help "Force all GPIO pads to be unlocked for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, - Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 5." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, - Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, - Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, - Help "Disable/Enable PCH to CPU energy report feature." - Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, - Help "Allow entrance to the PCH SATA test modes." - Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, - Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS, - Help "Reserved for Pch Post-Mem Test" - Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, - Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls, "Use DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue, "Emmc Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue, "Emmc Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue, "Emmc Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue, "Emmc Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue, "Emmc Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue, "Emmc Rx Strobe Delay control register value", HEX, - Help "Please see Rx Strobe Delay control register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls, "Use tuned DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue, "SdCard Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue, "SdCard Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue, "SdCard Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue, "SdCard Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue, "SdCard Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS, - Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, - Help "Address of LogoPixelHeight" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, - Help "Address of LogoPixelWidth" - "Valid range: 0x0 ~ 0xFFFFFFFF" -EndPage - -Page "PCH 2" - EditNum $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX, - Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, - Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." - Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, - Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &EN_DIS, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): Enable EOP message" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" -EndPage - diff --git a/CometLakeFspBinPkg/CometLake2/Fsp.fd b/CometLakeFspBinPkg/CometLake2/Fsp.fd deleted file mode 100644 index a306180b4d537e439b718ac6a77ed333c144b43a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 815104 zcmeFYc|6qL_c%Ud24iccQVB&&5t1#tEE$v~WKTp$N(zHyZBoXwQL?1ao}{vrwUB+^ z$(phxV++~0=69b%uUD_v=k@-4-tX_{@%uf#fBdfI`Ml42&pG#;bI&>V-1~fnK>W4% z4Boh*62^PMpdQ1Op5HkiH&h!>{o&Ktmx=5>bo@LHH5`JJ%#}qqc*sRs!f&T z&?}7c;E^^YSvbltiZF~{I!PMCV3F*26KVw@K`zB2dGTOCy9B^c3C!7AF*Aoe@i@p2 z&kmX3IVqZ3X$n6*&w5yMw&XXuWFD@!^D~SX>tj`;+=QEb750!kk#OU z-JA;CDMhYMHEpiq}fwDSP{6dDN!-l7j39% zt51|v&=B?%3-$$`iA1;y&TB}}u)sFCNQ;a_Zh)|L9f4&H;g}~QY|B9^pQpr+(XO1hbZs5jUucKKuvFRp* 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zd;}DLQGof$KNl7vjZLe?Xj^+n=h`k(nXk;V7kM>#3}2O#T3?-y^I<_n<*CYXJOm0S zPMsLX*TMzgDIb0~{$CvI`LRjp7d{j|7Csd&3pa#ak+&m-$k&ms#upm<8eeKW+H}6@ zo2I8$3u07k7rVtb#6#jSu^^ri$HmLyZSi;U&FDn*+bER+QngekJuR(}_DgR`?@HfG z@#go~0IDH)!x1tZ{xbYWc#ZIta79=FE5{cZMn$maTqJ0E2!lYb_lzK zJ;Ja+BQ24iqj#gLrG3)4^n>)PbWhsfe6;z4=J{)uuDRZFyG50u#1s6l0_KW*6<@_kJpKIRfPflp|1%Ksf^C2$UmGjzBpA#TV7lA(kW*zkF diff --git a/CometLakeFspBinPkg/CometLake2/FspPcds.dsc b/CometLakeFspBinPkg/CometLake2/FspPcds.dsc deleted file mode 100644 index 42c29d2..0000000 --- a/CometLakeFspBinPkg/CometLake2/FspPcds.dsc +++ /dev/null @@ -1,40 +0,0 @@ -## @file -# FSP description for DynamicEx PCDs. -# -# @copyright -# Copyright (c) 2020, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - - ## Specifies the AP target C-state for Mwait during POST phase. - # The default value 0 means C1 state. - # The value is defined as below.

- # @Prompt The specified AP target C-state for Mwait. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 20 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress | 0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength | 0x10000000 - - ## Specifies the base address of the first microcode Patch in the microcode Region. - # @Prompt Microcode Region base address. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - diff --git a/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h deleted file mode 100644 index 4d72102..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h deleted file mode 100644 index 34283b8..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @file - Header file for FSP Information HOB. - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _FSP_INFO_HOB_H_ -#define _FSP_INFO_HOB_H_ - -extern EFI_GUID gFspInfoGuid; - -#pragma pack (push, 1) - -typedef struct { -UINT8 SiliconInitVersionMajor; -UINT8 SiliconInitVersionMinor; -UINT8 SiliconInitVersionRevision; -UINT8 SiliconInitVersionBuild; -UINT8 FspVersionRevision; -UINT8 FspVersionBuild; -UINT8 TimeStamp [12]; -UINT8 FspVersionMinor; -} FSP_INFO_HOB; - -#pragma pack (pop) - -#endif // _FSP_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h deleted file mode 100644 index 395a7a1..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */ - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h deleted file mode 100644 index cb58672..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h +++ /dev/null @@ -1,3056 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResistor settings - Indicates RcompResistor settings: CML - 0's means MRC auto configured based on - Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to - provide the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0096 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0097 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0098 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A4 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A6 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A7 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A8 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A9 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00AE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00AF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00B0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00B1 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00B2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00B4 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00B6 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00B7 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00B8 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00B9 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00BA - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00BB - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00BC - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00C0 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00C1 - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00C2 - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00C3 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00C4 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C5 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C6 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C8 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00CA - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00CC - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00CE - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CF - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00D0 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00D1 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00D2 - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00D3 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00D4 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D5 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D6 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D7 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00D8 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00DA - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00DB - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00DC - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00DD - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00DE - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00DF - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00E0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x00E4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x00E8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x00EC - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x00EE - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x00F0 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x00F3 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x00F4 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x00F5 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x00F6 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x00F7 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x00F8 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x00F9 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x00FA - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x00FB - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x00FC - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x00FD - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x00FE - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x00FF - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0100 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0101 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0102 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0105 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x010D - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0115 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0122 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0130 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0134 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0154 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0155 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0156 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0158 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x015C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0160 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01C1 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01C2 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01C3 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01C4 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01C5 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x01C6 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01CA - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01CC - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01CF - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01D0 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01D1 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01D2 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01D3 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01D4 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01DA - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01DB - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[1]; - -/** Offset 0x01DC - Per-core HT Disable - Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, - 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value - of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have - HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1. -**/ - UINT16 PerCoreHtDisable; - -/** Offset 0x01DE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01E0 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01E1 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x01E2 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x01E3 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x01E4 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x01E5 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x01E6 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x01E7 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01E8 - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x01E9 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01EA - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01EC - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01ED - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01EE - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x01EF - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x01F0 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x01F1 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x01F2 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x01F4 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x01F6 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x01F8 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x01F9 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x01FA - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x01FC - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x01FE - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0200 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0201 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0202 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0203 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0204 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0205 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0208 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x020C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0210 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0214 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0218 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0220 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0224 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0228 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x022C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0230 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0238 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0240 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0241 - Intel Speed Optimizer Enable - When enabled this feature automatically overclocks your processor. It changes the - All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AutoEasyOverclock; - -/** Offset 0x0242 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[2]; - -/** Offset 0x0244 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0250 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0251 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x0253 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x0256 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0257 - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0439 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x043A - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x043B - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x043C - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x043E - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0440 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0444 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0448 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0449 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x044A - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x044B - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x044C - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x044D - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x044E -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0450 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0454 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0455 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0456 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0457 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0458 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x045A - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x045B - Enable HD Audio DMIC0 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x045C - Enable HD Audio DMIC1 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x045D - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x045E - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x045F - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0465 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[2]; - -/** Offset 0x0467 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0468 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0469 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x046A - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x046B - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x046C - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x046D - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x046E - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x046F - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0470 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0471 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0472 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0473 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0474 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0475 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0476 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0477 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0478 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0479 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x047A - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x047B - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x047C - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x047D - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x047E - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x047F - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0480 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0481 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0482 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0483 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0484 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0485 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0486 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0487 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0488 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0489 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x048A - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x048B - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x048C - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x048D - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x048E - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x048F - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0490 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0491 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0492 - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x0493 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x0494 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x0495 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x0496 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x0497 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x049A - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x049B - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x049C - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x049D - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x049F - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04A0 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04A1 - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04A2 - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04A5 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x04A6 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04A8 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04AC - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04AD - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04AE - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04B0 - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04B2 - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04B4 - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04B6 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04B7 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04B8 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04B9 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04BA - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04BB -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x04BC - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04BE - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04CA - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04CB - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04CC - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04CD - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04CE - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04CF - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D0 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04D1 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04D2 - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04D3 - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04D8 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04D9 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04DA - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04DB - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04DC - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04DD - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04DE - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04DF - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E0 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04E1 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04E2 - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04E3 - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04E4 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04E5 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04E6 - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04E7 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04E8 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04E9 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04EA - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04EB - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04EC - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04ED - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04EE - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04EF - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F0 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04F1 - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04F2 - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04F3 - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04F4 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04F5 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04F6 - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x04F7 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x04F9 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x04FB - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x04FC - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x04FD - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x04FE - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x04FF - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0500 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x0501 - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x0502 - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x0504 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0505 - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x0506 - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4Mixed2DpcLimit; - -/** Offset 0x0508 - RMT on Fast flow - Enable/Disable RMT on Fast flow. Default: Disabled - $EN_DIS -**/ - UINT8 FastBootRmt; - -/** Offset 0x0509 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl; - -/** Offset 0x050A - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x050B - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x050D - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x050E - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x050F - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x0510 - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control - deprecated -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x0515 - Core VF Point Offset Mode - Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; - 0: Legacy; 1: Selection. - 0:Legacy, 1:Selection -**/ - UINT8 CoreVfPointOffsetMode; - -/** Offset 0x0516 - Core VF Point Offset - Array used to specifies the Offset Voltage applied to the each selected Core VF - Point. This voltage is specified in millivolts. -**/ - UINT16 CoreVfPointOffset[15]; - -/** Offset 0x0534 - Core VF Point Offset Prefix - Sets the CoreVfPointOffset value as positive or negative for corresponding core - VF Point; 0: Positive ; 1: Negative. - 0:Positive, 1:Negative -**/ - UINT8 CoreVfPointOffsetPrefix[15]; - -/** Offset 0x0543 - Core VF Point Ratio - Array for the each selected Core VF Point to display the ration. -**/ - UINT8 CoreVfPointRatio[15]; - -/** Offset 0x0552 - Core VF Point Count - Number of supported Core Voltage & Frequency Point Offset -**/ - UINT8 CoreVfPointCount; - -/** Offset 0x0553 -**/ - UINT8 UnusedUpdSpace8[4]; - -/** Offset 0x0557 -**/ - UINT8 ReservedFspmUpd[1]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0558 -**/ - UINT32 Signature; - -/** Offset 0x055C - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x055D - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x055E - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x055F - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0560 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0561 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0562 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0563 - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x0564 - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x0565 - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x0566 - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x0567 - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0568 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0569 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x056A - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x056B - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x056C - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x056D - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x056E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x056F - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0570 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0571 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x0572 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0573 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0574 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0575 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0589 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x059D - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x05B1 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x05B4 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x05B6 - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x05B8 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x05BA - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x05BB - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x05BC - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x05BD -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x05C0 - Oem T12 Dealy Override - Oem T12 Dealy Override. 0(Default)=Disable 1=Enable - $EN_DIS -**/ - UINT8 OemT12DelayOverride; - -/** Offset 0x05C1 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x05CA - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x05CC - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x05CE - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x05CF - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x05D2 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x05D3 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x05D4 - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x05D5 - ReservedPchPreMemTest - Reserved for Pch Pre-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPreMemTest[16]; - -/** Offset 0x05E5 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05E6 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05E7 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05E8 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05E9 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05EA - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05EB - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05EC - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05ED - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05EE - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05EF - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05F0 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05F1 - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05F2 - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05F3 - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05F4 - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05F5 - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05F6 - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05F7 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05F8 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05F9 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05FA - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05FB - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05FC - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05FD - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05FE - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05FF - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x0600 - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x0601 -**/ - UINT8 ReservedFspmTestUpd[7]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0558 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0608 -**/ - UINT8 UnusedUpdSpace11[6]; - -/** Offset 0x060E -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h deleted file mode 100644 index ddfcb0c..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h +++ /dev/null @@ -1,3675 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0030 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0034 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0038 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0039 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x003A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x003B - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x003C - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x003D - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x003E - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x003F - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0040 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0041 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0042 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0044 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x0046 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0047 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0048 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0049 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x004A - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x004B - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x004F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x0053 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0058 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0060 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0063 - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x0065 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x0068 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0074 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0075 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0076 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0077 - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x0078 - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x0079 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x007A - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x007B - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x007C - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x007D - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0080 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0084 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0088 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0089 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x00C4 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x00C9 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x00CE - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x00D3 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x00DD - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x00E2 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x00E7 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x00EC - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x00ED - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x00EE - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x00F3 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x00F4 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x00FE - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0108 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x0112 - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x011C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0126 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0130 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x013A - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0146 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0147 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0148 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x014A - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x014B - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x014C - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x014E - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x014F - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x0159 -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x015A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0164 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0168 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0169 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x016A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x016B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x016C - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0170 - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0174 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace8[1]; - -/** Offset 0x0176 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x0180 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0188 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0189 - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x018B - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x018D - SPI2 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi2CsPolarity[2]; - -/** Offset 0x018F - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x0191 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x0193 - SPI2 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi2CsEnable[2]; - -/** Offset 0x0195 - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[3]; - -/** Offset 0x0198 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[3]; - -/** Offset 0x019B - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x01A1 - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x01A7 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01AC - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x01B8 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x01BB - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x01BE - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x01CA - Serial IO UART Pin Mux - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 SerialIoUartPinMux[3]; - -/** Offset 0x01CD - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01CE - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x01D1 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x01D2 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x01D3 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x01D4 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x01D5 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x01D6 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x01DE - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x01E6 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x01F6 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x0200 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0201 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0208 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0209 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0211 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0212 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0213 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x0214 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x0215 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0216 -**/ - UINT8 UnusedUpdSpace11[2]; - -/** Offset 0x0218 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x021C - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x021D - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x021E - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x021F - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x022F - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x023F - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x0287 - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x0288 - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x028C - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0290 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x0294 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x0295 - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x0296 - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x0297 - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0298 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0299 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x029A - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x029B - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x029C - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x029D - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x029E - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x02A0 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x02A4 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x02A8 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x02AC - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x02AD -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x02B0 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x02B5 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x02B6 -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x02B8 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x02BC - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x02BD -**/ - UINT8 UnusedUpdSpace14[3]; - -/** Offset 0x02C0 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x02C4 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x02C8 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x02C9 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x02CA - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x02CB - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x02CC - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x02CD - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x02CE - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x02CF - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x02D0 - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x02D1 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x02D2 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x02D3 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x02D4 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x02D5 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x02D6 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x02EE - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x02FE - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x030E - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x0326 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x033E - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x036F - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping - CPU and 1 for PCH-H Series. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x0370 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x037B -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x037C - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0386 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0390 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0391 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0392 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x0393 - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x0394 - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x0396 - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0397 - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x03A2 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x03B1 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x03B4 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x03B5 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x03B6 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03CE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03E6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x0416 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x042E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0446 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x045E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0476 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x048E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x04A6 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04D6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04EE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x051A - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x054A - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0562 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x057A - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x0592 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05AA - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05C2 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x060A - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, - the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x060F - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the - default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0614 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0615 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0616 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0617 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0618 - Teton Glacier Cycle Router - Specify to which cycle router Teton Glacier is connected, it is valid only when - Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x061A - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x061B - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x061C - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic - Configuration. Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x061D - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x061F - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0622 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0623 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0624 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0625 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0626 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x0627 - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x0628 - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x0629 - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x062A - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x062B - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x062C - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x062D - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x062E - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0630 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0631 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0632 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0635 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0636 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0637 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x0638 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0639 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0641 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0649 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0651 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0659 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0661 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0669 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0671 -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x0672 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x0682 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x068A - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x068B - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x068C - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x068D - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x068E - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x068F - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x0692 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x0693 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0694 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0695 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x069F - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06A0 - Set HS400 Tuning Data Valid - Deprecated - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06A1 - Rx Strobe Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06A2 - Tx Data Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06A3 - I/O Driver Strength - Deprecated - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06A4 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06A5 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06A6 - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06A7 - PCH eSPI Link Configuration Lock (SBLCL) - Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves - addresseses from range 0x0 - 0x7FF - $EN_DIS -**/ - UINT8 PchEspiLockLinkConfiguration; - -/** Offset 0x06A8 - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06A9 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06B0 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06B1 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06B2 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x06B3 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x06B4 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x06B7 - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x06B8 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x06B9 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x06BA - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x06BB - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x06BC - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x06BD - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x06BE - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x06BF - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x06C0 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x06C1 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x06C2 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x06C3 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x06C5 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x06C8 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x06C9 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x06CB - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x06CD - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x06CF -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x06D0 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x06D2 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x06D3 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x06E3 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x06ED - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x06EE - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x06F1 -**/ - UINT8 UnusedUpdSpace19[3]; - -/** Offset 0x06F4 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x06F8 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x06F9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x06FB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default - = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x074C - Number of Coefficients to be used - The number of coefficients to be used for equalization, default value is 3 -**/ - UINT8 PcieNumOfCoefficients; - -/** Offset 0x074D - GPIO RCOMP Community Clock Gating - 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock - local clock gating, default value is 1 - $EN_DIS -**/ - UINT8 GpioPmRcompCommunityLocalClockGating; - -/** Offset 0x074E - Enable SD Card Write Protect Pin - Enable/disable SD Card Write Protect Pin. - $EN_DIS -**/ - UINT8 ScsSdCardWpPinEnabled; - -/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x0757 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control - 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x075C - ReservedPchPostMem - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[3]; - -/** Offset 0x075F -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0760 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0780 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0784 -**/ - UINT8 UnusedUpdSpace21[4]; - -/** Offset 0x0788 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0790 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0798 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0799 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x079A -**/ - UINT8 UnusedUpdSpace22[6]; - -/** Offset 0x07A0 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x07A8 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x07B0 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07B1 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07B2 -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x07B4 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07B8 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07BA - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07BB - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07BC -**/ - UINT8 UnusedUpdSpace24[3]; - -/** Offset 0x07BF -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07C0 -**/ - UINT32 Signature; - -/** Offset 0x07C4 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07C5 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07C6 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07C7 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07C8 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07C9 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07CD - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07CE - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07CF - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07D0 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07D1 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07D2 - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07D3 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07DE - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07DF - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07E0 - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07E1 - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07E2 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07E3 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07E4 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07E5 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07E6 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07E7 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07E8 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07E9 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07EA - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07EB - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07ED - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07EE - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07EF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07F0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07F1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07F2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07F3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07F4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07F5 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07F6 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07F7 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07F8 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07F9 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07FA - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07FB - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07FC - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0800 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0802 - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x0803 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0804 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x0805 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x0806 -**/ - UINT8 UnusedUpdSpace25[2]; - -/** Offset 0x0808 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0810 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x0814 - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0816 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable, 2: Auto / Silicon default - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0818 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x081B - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x081C - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x081D - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x081E - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x081F - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0820 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0821 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0822 - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0824 - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0825 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0827 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0828 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0829 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x082A - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x082B - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x082C - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x082D - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x082E - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x082F - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0830 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0831 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0832 - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x0833 - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x086B -**/ - UINT8 UnusedUpdSpace26; - -/** Offset 0x086C - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x087A -**/ - UINT8 UnusedUpdSpace27[2]; - -/** Offset 0x087C - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0880 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0884 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0888 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x088C - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x08A8 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x08AC - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x08B0 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x08B2 - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x08B3 - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x08B4 - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x08B5 - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver - @deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08BA - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08BB - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08BC - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08BF - Ratio Limit Num Core 0 - Ratio Limit Num Core0: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore0; - -/** Offset 0x08C0 - Ratio Limit Num Core 1 - Ratio Limit Num Core1: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore1; - -/** Offset 0x08C1 - Ratio Limit Num Core 2 - Ratio Limit Num Core2: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore2; - -/** Offset 0x08C2 - Ratio Limit Core 3 - Ratio Limit Num Core3: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore3; - -/** Offset 0x08C3 - Ratio Limit Num Core 4 - Ratio Limit Num Core4: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore4; - -/** Offset 0x08C4 - Ratio Limit Num Core 5 - Ratio Limit Num Core5: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore5; - -/** Offset 0x08C5 - Ratio Limit Num Core 6 - Ratio Limit Num Core6: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore6; - -/** Offset 0x08C6 - Ratio Limit Num Core 7 - Ratio Limit Num Core7: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore7; - -/** Offset 0x08C7 - Dual Tau Boost - Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 DualTauBoost; - -/** Offset 0x08C8 - ITBMT 3.0 Runtime Periodic SMM timer - Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic - SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, - 6 - 32 sec, 7 - 64 sec. -**/ - UINT8 ItbmPeriodicSmmTimer; - -/** Offset 0x08C9 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[9]; - -/** Offset 0x08D2 - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08D3 - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): - Enable EOP message - $EN_DIS -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08D4 - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08D5 -**/ - UINT8 UnusedUpdSpace28; - -/** Offset 0x08D6 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08D8 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08DA - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08DB - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x096C - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x0A14 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A75 - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A76 - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A77 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A79 - ReservedPchPostMemTest - Reserved for Pch Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPostMemTest[16]; - -/** Offset 0x0A89 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A8A - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0A8B -**/ - UINT8 UnusedUpdSpace29; - -/** Offset 0x0A8C - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0AA4 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x0AA5 -**/ - UINT8 UnusedUpdSpace30[3]; - -/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x0ABC - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0ABD -**/ - UINT8 UnusedUpdSpace31[3]; - -/** Offset 0x0AC0 - LogoPixelHeight Address - Address of LogoPixelHeight -**/ - UINT32 LogoPixelHeight; - -/** Offset 0x0AC4 - LogoPixelWidth Address - Address of LogoPixelWidth -**/ - UINT32 LogoPixelWidth; - -/** Offset 0x0AC8 -**/ - UINT8 UnusedUpdSpace32[4]; - -/** Offset 0x0ACC -**/ - UINT8 ReservedFspsTestUpd[4]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07C0 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0AD0 -**/ - UINT8 UnusedUpdSpace33[6]; - -/** Offset 0x0AD6 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h deleted file mode 100644 index 9617105..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h +++ /dev/null @@ -1,180 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) - 0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 PcdSerialIoUartPinMux; - -/** Offset 0x0059 - PcdLpcUartDebugEnable - Enable to initialize LPC Uart device in FSP. - 0:Disable, 1:Enable -**/ - UINT8 PcdLpcUartDebugEnable; - -/** Offset 0x005A - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x005B - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x005C - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x005D -**/ - UINT8 UnusedUpdSpace1[7]; - -/** Offset 0x0064 -**/ - UINT8 ReservedFsptUpd1[20]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0078 -**/ - UINT8 UnusedUpdSpace2[6]; - -/** Offset 0x007E -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h b/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h deleted file mode 100644 index eed3cb2..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h +++ /dev/null @@ -1,329 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - -@copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 9; - UINT32 RsvdBits : 10; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, - GpioPadModeNative5 = 0xB -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Configuration options for GPIO termination setting -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. - By default GPIO pads will be locked unless GPIO lib is explicitly - informed that certain pad is to be left unlocked. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controlled - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock - an already locked pad upon request for reconfiguration -**/ -typedef enum { - /** - Perform default action - - if pad is an GPO, lock configuration but leave output unlocked - - if pad is an GPI, lock everything - - if pad is in native, lock everything -**/ - GpioLockDefault = 0x0, - GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked - GpioPadConfigLock = 0x1, ///< Lock Pad configuration - GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked - GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked - GpioPadLock = 0x5 ///< Lock both Pad configuration and output control -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h b/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h deleted file mode 100644 index 9cfc7c7..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Sample enum definitions for GPIO table. - - @copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h b/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h deleted file mode 100644 index 2712130..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Definitions for Hob Usage data HOB - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _HOB_USAGE_DATA_HOB_H_ -#define _HOB_USAGE_DATA_HOB_H_ - -extern EFI_GUID gHobUsageDataGuid; - -#pragma pack (push, 1) - -/** - Hob Usage Data Hob - - Revision 1: - - Initial version. -**/ -typedef struct { - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - UINTN FreeMemory; -} HOB_USAGE_DATA_HOB; - -#pragma pack (pop) - -#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h deleted file mode 100644 index 1c94e8e..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h +++ /dev/null @@ -1,263 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; - -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index 87913d9..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 - // - // Add for smbios 3.1.0 - // - UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index 1fa6795..0000000 --- a/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLake2/README.md b/CometLakeFspBinPkg/CometLake2/README.md deleted file mode 100644 index 4e3e935..0000000 --- a/CometLakeFspBinPkg/CometLake2/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# CometLakeFspBinPkg/CometLake2 -These FSP binaries are intended to be used with 10th Generation Intel® Core™ U-Series processors and chipsets formerly known as Comet Lake with support for LPDDR4 & DDR4 memory. Please consult CometLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use. diff --git a/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bin b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index e801e45246d84e43bc6439b6fdda257a20675aa9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKU2GIp6h5=FzjtP~vr{7573<+Auv=)EEwExOakjgyUAnN_ZfQz1=>of8!$NC+ zv=~g+q){G}?1LIKD19L+FXEH&4c|yilxTuaModgle38hD0U6Kyw2LKa7a}NzZ};4D z?wLE^oclBPo>?={(T};F-RXEwC)y~03a0~pDsM+eDw7*Z#{1(#9qCM>2Y-S`U?Ony z3P6G58pNooMpK6;iluO0glN;aV`T4eskkv&96vZQGK$$m3gi3s6-&jjJrl(O<_4aL zqroY$j>+Lt0e4Ow+FKlJLn2bCHAXkLY}$+%-PlThHM)gNwJjQJ+w!EulAVdnj%+F& z?@wiRVx|w1sa!ml>)g?i-i_J5On0gy)!&(v*nBq!MpRGU+@M_>i@XFxSz=`0L zK||1FKpDIMP5=!60c0Zx864X<2l>`{!5uU_b0B)&v^Ar#4Pt|fd5~qV;Hdc0}L z99jm|=yC9k*=&v7%mF}u1033h(F|?2nB9z&^-z^V%b+{Z4poM3yP04R8Nk0aGhO$) z;5mRBFVj;=8{mL50O03TIPPnN3?GK0yaQh2w?dQiJg7c|oKJ@RBu7ZTbusv!Zr}wClR= z%Tv{1E|7awvM+%av;|#%&@HhZw$q!)d)sGLn0?s=pr4X>m;x4{cie^|&MivQvFrnI zhpbDU_PI6-^}l%~Wb6!&iu?r+gA1N(+_C!qre%zoyu{BMS6vU-u<8%Xha+%jBe0?y zF8az9y!4pt&9AcVZM-|rW2gYvxzpxr4eIXKgM- zsGC39t2f_jg&T={{8o=?pCMSz$Xmc4VE86ePBHc|!>^h0BV)fZ3<%0BiA_s*T2elf*cTFBmXtpv#``hiSDx~-PCp*>E3f$3>wc+8ag`mHxH6@n zMtu2zb?fLPynSL~)07YxofDBCbS%v8GHXa0W7F25 zNb^No{?ZJE2GHWLRt+ADSq#D0G;gI<6ec(ghW15!p*F#ZUQji4w0=GYy3w%3DOac_ zhAHd~$(no%16Og~0mDZdr!Mt|)@p+%sxfdCx5=Qn&(;t__tToX_iU@CovSjqtt?3# zaMd!B`&SN}>4iqMt76ZEF_IPYe5Fuo8Hb}SmDzl#QB%>L3z|)5#mr*GvZt0_gxkxr zqi0tWLzB^W0Ag@e%v?sCb-2yA}quNjsmPDX76- zD`zxf;AuG$?siR@43fp*!Ww#UB?PlsT&{|0qS}iJy^j<_*|XJL4~xH>j<#~}g{{rn zU~_dYc&M{tps$~$-;0O_`7+e!WjRodfi_YjhIChUD7)uyv9xo~q2m9bVs&t_a{a5| z-hQ6)_%rve)EB_902^ZPMi&K{qU?Sb9bg66z`X-M^RyLPpuE_GdjVQh4vx*^!7#1K UnEQCS?|PH{@x9oZ_y?~21+7}z9{>OV diff --git a/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index 30ec8b8..0000000 --- a/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11683 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Coffeelake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from CFL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x01, "Pin-Pair #1" - Selection 0x02, "Pin-Pair #2" - Selection 0x03, "Pin-Pair #3" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Coffeelake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if theres no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel Rapid Memory Power Management (RMPM)\r\n" - "2. Intel Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop CFL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/CometLakeFspBinPkg/CometLakeS/CometLakeFspBinPkg.dec b/CometLakeFspBinPkg/CometLakeS/CometLakeFspBinPkg.dec deleted file mode 100644 index 1c0b637..0000000 --- a/CometLakeFspBinPkg/CometLakeS/CometLakeFspBinPkg.dec +++ /dev/null @@ -1,29 +0,0 @@ -## @file -# Component description file for CometLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = CometLakeFspBinPkg - PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 - PACKAGE_VERSION = 1.02 - -[Includes] - Include - -[Guids] - gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }} - -[Ppis] - gEfiReadyToInstallPciEnumerationCompleteProtocolGuid = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }} - gEfiReadyToInstallEventReadyToBootGuid = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }} - gFspReadyToInstallEventEndOfFirmwareGuid = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }} - gEndOfFspS3NotifyGuid = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }} - gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }} diff --git a/CometLakeFspBinPkg/CometLakeS/Fsp.bsf b/CometLakeFspBinPkg/CometLakeS/Fsp.bsf deleted file mode 100644 index b86b588..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Fsp.bsf +++ /dev/null @@ -1,4862 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "CMLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gPlatformFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize 1 bytes $_DEFAULT_ = 0x0C - $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort 1 bytes $_DEFAULT_ = 0x99 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 10 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGpioData 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xD0000000 - $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xCF000000 - $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x001 - $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MemoryTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableCltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableOltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhPrevention 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 - $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A - $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B - $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RhActProbability 1 bytes $_DEFAULT_ = 0xB - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr 2 bytes $_DEFAULT_ = 0xDE - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x30 - $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping 1 bytes $_DEFAULT_ = 0xAA - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhSolution 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax 1 bytes $_DEFAULT_ = 0x69 - $gPlatformFspPkgTokenSpaceGuid_TsodEventMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodThigMax 1 bytes $_DEFAULT_ = 0x5D - $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_GdxcEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_FivrFaults 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 - $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnBER 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FastBootRmt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x40 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 - Skip 9 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 - $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis 4 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01 - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 4 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 8 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 34 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Reserved2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonSlope1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonOffset1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 8 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity 2 bytes $_DEFAULT_ = 0x00, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x02 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 12 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 3 bytes $_DEFAULT_ = 0x08, 0x08, 0x08 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 3 bytes $_DEFAULT_ = 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux 3 bytes $_DEFAULT_ = 0, 0, 0 - $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF - $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F - $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters 10 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x06, 0x08, 0x02, 0x0A - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x08, 0x0C, 0x08, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SlpS0Override 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C - $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem 3 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - Skip 8 bytes - $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload 4 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF - $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0F - $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4B - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 16 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux - Selection 0 , " GPIO C8 to C11" - Selection 1 , " GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RhSolution - Selection 0 , "Hardware RHP" - Selection 1 , "2x Refresh" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration - Selection 0 , "IPU Camera" - Selection 1 , "IPU Gen" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit - Selection 0 , "BIT6" - Selection 1 , "BIT7" - Selection 2 , "BIT8" - Selection 3 , "BIT9" - Selection 4 , "BIT10" - Selection 5 , "BIT11" - Selection 6 , "BIT12" - Selection 7 , "BIT13" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType - Selection 0 , "1DPC" - Selection 1 , "2DPC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl - Selection 0 , "Disabled" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" - Selection 4 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , " HALT loop" - Selection 2 , " MWAIT loop" - Selection 3 , " RUN loop" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug - Selection 0 , "No Change" - Selection 1 , "DCI OOB" - Selection 2 , "USB2 DbC" - Selection 3 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode - Selection 0 , "SerialIoUartDisabled" - Selection 1 , "SerialIoUartPci" - Selection 2 , "SerialIoUartHidden" - Selection 3 , "SerialIoUartCom" - Selection 4 , "SerialIoUartSkipInit" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode - Selection 0 , " 2T" - Selection 1 , " 1T" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType - Selection 0 , " VC0" - Selection 1 , " VC1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0Override - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent - Selection 0 , "Disabled" - Selection 1 , "Enabled (DCI OOB+[DbC])" - Selection 2 , "Enabled (DCI OOB)" - Selection 3 , "Enabled (USB3 DbC)" - Selection 4 , "Enabled (XDP/MIPI60)" - Selection 5 , "Enabled (USB2 DbC)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency - Selection 100000000 , "100Hz" - Selection 125000000 , "125Hz" - Selection 167000000 , "167Hz" - Selection 250000000 , "250Hz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode - Selection 0 , " Disable" - Selection 1 , "Target Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BdatTestType - Selection 0 , "Rank Margin Tool" - Selection 1 , "Margin2D" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" - Selection 30 , "30" - Selection 34 , "34" - Selection 40 , "40" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme - Selection 0 , " Single Range Output" - Selection 1 , " ToPA Output" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate - Selection 0 , "Disable" - Selection 1 , "1 CMD" - Selection 2 , "2 CMDS" - Selection 3 , "3 CMDS" - Selection 4 , "4 CMDS" - Selection 5 , "5 CMDS" - Selection 6 , "6 CMDS" - Selection 7 , "7 CMDS" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt - Selection 0 , "Msix" - Selection 1 , "Msi" - Selection 2 , "Legacy" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh - Selection 0 , " Active low" - Selection 1 , " Active high" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize - Selection 0 , "32MB" - Selection 1 , "288MB" - Selection 2 , "544MB" - Selection 3 , "800MB" - Selection 4 , "1024MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow - Selection 0 , " Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency - Selection 0 , " 6MHz" - Selection 1 , " 12MHz" - Selection 2 , " 24MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Refresh2X - Selection 0 , "Disable" - Selection 1 , "Enabled for WARM or HOT" - Selection 2 , "Enabled HOT only" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CnviMode - Selection 0 , "Disable" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength - Selection 0 , "33 Ohm" - Selection 1 , "40 Ohm" - Selection 2 , "50 Ohm" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode - Selection 0 , " Disabled" - Selection 1 , " Dynamic Configuration" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RefClk - Selection 0 , "133MHz" - Selection 1 , "100MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize - Selection 0 , "Default" - Selection 1 , " 1 Byte" - Selection 2 , " 1 KB" - Selection 3 , " Max value" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnableSgx - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Software Control" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW - Selection 0 , "x1" - Selection 1 , "x2" - Selection 2 , "x4" - Selection 3 , "x8" - Selection 4 , "x16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck - Selection 0 , "Disable" - Selection 1 , "L1" - Selection 2 , "L2" - Selection 3 , "Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber - Selection 0 , "UART0" - Selection 1 , "UART1" - Selection 2 , "UART2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1400 , "1400" - Selection 1600 , "1600" - Selection 1800 , "1800" - Selection 1867 , "1867" - Selection 2000 , "2000" - Selection 2133 , "2133" - Selection 2200 , "2200" - Selection 2400 , "2400" - Selection 2600 , "2600" - Selection 2667 , "2667" - Selection 2800 , "2800" - Selection 2933 , "2933" - Selection 3000 , "3000" - Selection 3200 , "3200" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix - Selection 0 , "Positive" - Selection 1 , "Negative" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear - Selection 0 , " Disable ME Unconfig On Rtc Clear" - Selection 1 , " Enable ME Unconfig On Rtc Clear" - Selection 2 , " Cmos is clear" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse - Selection 0 , " PchSfpw4Clk" - Selection 1 , " PchSfpw6Clk" - Selection 2 , " PchSfpw8Clk" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 3 , "512 MB" - Selection 7 , "1024 MB" - Selection 15 , " 2048 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency - Selection 4 , " 96MHz" - Selection 3 , " 48MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode - Selection 0 , "Legacy" - Selection 1 , "Selection" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode - Selection 0 , " Disable" - Selection 1 , " Target Debugger Mode" - Selection 2 , " Host Debugger Mode" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Comet Lake Platform" -EndInfoBlock - -Page "System Agent 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, - Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, - Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, - Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, - Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's" - Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "0: Disable, 1: Enable (Default) timeout check for HECI" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, - Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX, - Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX, - Help "Root port Index number to indicate which PCIe root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, - Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, - Help "0:IPU Camera, 1:IPU Gen Default is 0" - Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, - Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" - Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, - Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1." - "Valid range: 0x00 ~ 0x1FF" - Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." - Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS, - Help "Program Cache Attributes; 0: Program; 1: Disable Program." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, - Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, - Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, - Help "Ring voltage mode; 0: Adaptive; 1: Override." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, - Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, - Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" - "Valid range: 0x0A ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control" - Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, - Help "IsTPMPresence default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS, - Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, - Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms" - Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, - Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " -EndPage - -Page "System Agent 2" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "Enable/disable Device 4" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, - Help "Central Write Buffer feature configurable and disabled by default" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS, - Help "Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, - Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, - Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution." - Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS, - Help "0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS, - Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, - Help "DEPRECATED" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, - Help "Address of Blt buffer" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, - Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, - Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "DEPRECATED" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, - Help "Enable or Disable TXT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS, - Help "@deprecated SkipMpInit has been moved to FspmUpd" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX, - Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, - Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, - Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, - Help "Pointer CPU BIST Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Pointer for CpuMpPpi" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, - Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, - Help "Reserved for CPU Post-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS, - Help "Platform specific common policies that used by several silicon components. CSM status flag." - EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, - Help "The address of the table of SVID SDID to customize each SVID SDID entry." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, - Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, - Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX, - Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX, - Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX, - Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX, - Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy from 0 to 64ms" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0x00 ~ 0x64" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS, - Help "@deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX, - Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX, - Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable, 2: Auto / Silicon default" - Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio, Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, - Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, - Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xF9F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, - Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, - Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, - Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, - Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, - Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS, - Help "@deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS, - Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C3 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0, "Ratio Limit Num Core 0", HEX, - Help "Ratio Limit Num Core0: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1, "Ratio Limit Num Core 1", HEX, - Help "Ratio Limit Num Core1: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2, "Ratio Limit Num Core 2", HEX, - Help "Ratio Limit Num Core2: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3, "Ratio Limit Core 3", HEX, - Help "Ratio Limit Num Core3: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4, "Ratio Limit Num Core 4", HEX, - Help "Ratio Limit Num Core4: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5, "Ratio Limit Num Core 5", HEX, - Help "Ratio Limit Num Core5: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6, "Ratio Limit Num Core 6", HEX, - Help "Ratio Limit Num Core6: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7, "Ratio Limit Num Core 7", HEX, - Help "Ratio Limit Num Core7: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, - Help "Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer, "ITBMT 3.0 Runtime Periodic SMM timer", HEX, - Help "Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, 6 - 32 sec, 7 - 64 sec." - "Valid range: 0x00 ~ 0x07" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" -EndPage - -Page "Memory Reference Code 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, - Help "Indicates RcompResistor settings: CML - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, - Help "Time Measure: 0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, - Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." - Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, - Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." - Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100" - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, - Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, - Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, - Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B." - Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, - Help "This option enables data scrambling in memory." - Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, - Help "100MHz, 133MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34" - "Valid range: 0x00 ~ 0x22" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX, - Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, - Help "Margin Limit Check. Choose level of margin check" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS, - Help "Enables/Disable MRC Safe Config" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, - Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." - Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, - Help "Enables/Disable Early Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, - Help "Enables/Disable SenseAmp Offset Training" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Early ReadMPR Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, - Help "Enables/Disable Read MPR Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, - Help "Enables/Disable Receive Enable Training" - Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, - Help "Enables/Disable Jedec Write Leveling" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Write Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Read Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, - Help "Enables/Disable Dimm ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, - Help "Enables/Disable DIMM RON Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, - Help "Enables/Disable Write Drive Strength/Equalization 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, - Help "Enables/Disable Write Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, - Help "Enables/Disable Read ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, - Help "Enables/Disable Read Equalization Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, - Help "Enables/Disable Read Amplifier Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Read Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, - Help "Enables/Disable Command Voltage Centering" - Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, - Help "Enables/Disable Late Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, - Help "Enables/Disable Round Trip Latency Training" - Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, - Help "Enables/Disable Turn Around Timing Training" - Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, - Help "Enables/Disable Memory Test" - Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, - Help "Enables/Disable DIMM SPD Alias Test" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, - Help "Enables/Disable Receive Enable Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, - Help "Enables/Disable Retrain Margin Check" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, - Help "Enables/Disable Write Drive Strength Up/Dn independently" - Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, - Help "Enables/Disable ECC Support" - Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, - Help "Enables/Disable Memory Remap" - Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, - Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." - Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, - Help "Enables/Disable Enhanced Interleave support" - Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS, - Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed." - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, - Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, - Help "Enables/Disable Extern Therm Status" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Closed Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Open Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS, - Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS, - Help "Enables/Disable RAPL PL Lock" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 2 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 1 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, - Help "Enables/Disable SelfRefresh Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature" - Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS, - Help "Enables/Disable RH Prevention" - Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, - Help "Enables/Disable Exit On Failure (MRC)" - Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS, - Help "Enables/Disable LPDDR Thermal Sensor" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, - Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6" - "Valid range: 0x0000 ~ 0x3FFF" - Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, - Help "Base reference clock value, in Hertz(Default is 125Hz)" - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, - Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX, - Help "Energy Scale Factor, Default is 4" - "Valid range: 0x01 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, - Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, - Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" - "Valid range: 0x00 ~ 0x7D0" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, - Help "Enable/Disable CMD Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, - Help "Enable/Disable CMD Drive Strength and Tx Equalization" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, - Help "Enable/Disable CMD Normalization" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, - Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" - EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX, - Help "RH Activation Probability, Probability value is 1/2^(inputvalue)" - "Valid range: 0x01 ~ 0xF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX, - Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX, - Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX, - Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX, - Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, - Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX, - Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, - Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" - Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, - Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" - Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, - Help "Enable/disable(default) Energy Performance Gain." - Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution, - Help "Type of method used to prevent Row Hammer. Default is Hardware RHP" - Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, - Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." - Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, - Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, " TcritMax", HEX, - Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax" - "Valid range: 0x0 ~ 0x7F" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS, - Help "Disable:Comparator mode.\n Enable:Interrupt mode" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS, - Help "Disable:Active LOW.\nEnable:Active HIGH" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS, - Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS, - Help "Disable:Event output disable.\nEnable:Event output enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS, - Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS, - Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS, - Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX, - Help "Thigh = ThighMax (Default is 93)" - "Valid range: 0x0 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS, - Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit." - Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS, - Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh." - EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, - Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, - Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC MOT enable", &EN_DIS, - Help "GDXC MOT enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS, - Help "Fivr Faults; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS, - Help "Fivr Efficiency Management; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, - Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" - Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, - Help "Enables/Disable LpDdrDqDqsReTraining" - EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, - Help "This option configures Post Code Output Port" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, - Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" - "Valid range: 0 ~ 0x20" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX, - Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation." - "Valid range: 0 ~ 0x20" - Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, - Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs." - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS, - Help "Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. Disable=0, Enable(Default)=1" - Combo $gPlatformFspPkgTokenSpaceGuid_FastBootRmt, "RMT on Fast flow", &EN_DIS, - Help "Enable/Disable RMT on Fast flow. Default: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS, - Help "Reserved FspmConfig CFL" - Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, - Help "Run Base Memory Test on Warm Boot" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX, - Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS, - Help "Enables/Disable the MRC training on warm boot" - Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, - Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, - Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, - Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "deprecated" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, - Help "Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; 0: Legacy; 1: Selection." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, - Help "Array used to specifies the Offset Voltage applied to the each selected Core VF Point. This voltage is specified in millivolts." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, - Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, - Help "Array for the each selected Core VF Point to display the ration." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX, - Help "Number of supported Core Voltage & Frequency Point Offset" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, - Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX, - Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX, - Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX, - Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX, - Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX, - Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86." - "Valid range: 0x00 ~ 0x56" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX, - Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX, - Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX, - Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX, - Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX, - Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX, - Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX, - Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX, - Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX, - Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX, - Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX, - Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, - Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, - Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, - Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, - Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" -EndPage - -Page "PCH 1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, - Help "Select SerialIo Uart Controller mode" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, - Help "Set default Parity." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, - Help "Set default stop bits." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, - Help "Enables UART hardware flow control, CTS and RTS lines." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, "PcdSerialIoUartPinMux - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, - Help "Enable to initialize LPC Uart device in FSP." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity, "SPI0 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity, "SPI1 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity, "SPI2 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable, "SPI0 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable, "SPI1 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable, "SPI2 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, - Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, - Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, - Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, - Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, - Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, - Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, - Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, - Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, - Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS lines." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux, "Serial IO UART Pin Mux", HEX, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, - Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS, - Help "Enable/disable eMMC Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS, - Help "Enable eMMC HS400 Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS, - Help "Enable/disable SD Card Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0x17" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0x17" - Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, - Help "Enable/disable TCO IRQ" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, - Help "Enable/disable SMBus controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, - Help "To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting" - Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, - Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, - Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, - Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, - Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, - Help "0: Disable, 1: Enable (Default) Azalia controller" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "0: Disable, 1: Enable (Default) ISH Controller" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, - Help "Enable PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, - Help "PCH PCIe Gen 3 Set CTLE Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, - Help "Enables override of recommended LTR values for xHCI" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC0 link. Muxed with SNDW4." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask, "PTM for PCIE RP Mask", HEX, - Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask, "DPC for PCIE RP Mask", HEX, - Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask, "DPC Extensions PCIE RP Mask", HEX, - Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, - Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, - Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" - "Valid range: 0x00 ~ 0x009C4000" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Master and Slave BME enabled", &EN_DIS, - Help "PCH eSPI Master and Slave BME enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom, "PCH SATA use RST Legacy OROM", &EN_DIS, - Help "Use PCH SATA RST Legacy OROM when CSM is Enabled" - EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX, - Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, - Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Pointer." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, - Help "ChipsetInit Binary Length." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled, "Enable Ufs Controller", &EN_DIS, - Help "Enable/disable Ufs 2.0 Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, - Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, - Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, - Help "Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, "SdCard power enable polarity", &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, - Help "Choose SD_PWREN# polarity" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, - Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, - Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode", &EN_DIS, - Help "This option enables or disables espi lgmr" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, - Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, - Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, - Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl, "SLP_S0 VM Dynamic Control", &EN_DIS, - Help "SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport, "SLP_S0 VM 0.70V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport, "SLP_S0 VM 0.75V Support", &EN_DIS, - Help "SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, - Help "0: built-in device, 1:slot" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, - Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, - Help "Number of ClkReq signal assigned to ClkSrc" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, - Help "Enable/Disable PCIE RP Access Control Services Extended Capability" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, - Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, - Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, - Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &EN_DIS, - Help "Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping CPU and 1 for PCH-H Series. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, - Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel, "USB LFPS Filter selection", HEX, - Help "For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS, - Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, - Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, - Help "Original LPC only decodes one byte of port 80h." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, - Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, - Help "Enable SMBus ARP support." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, - Help "The number of elements in the RsvdSmbusAddressTable." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, - Help "SMBUS Base Address (IO space)." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, - Help "Size of PCIe IMR in megabytes" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, - Help "Array of addresses reserved for non-ARP-capable SMBus devices." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, - Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." - "Valid range: 0x00 ~ 0x00FFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, - Help "0:Disable, 1:Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection, "Root port number for IMR.", HEX, - Help "Root port number for IMR." - "Valid range: 0x00 ~ 0x18" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, - Help "Enable SMBus Alert Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS, - Help "Enables UART hardware flow control, CTS and RTS lines." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, - Help "Set default Parity." - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, - Help "Set default stop bits." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS, - Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS, - Help "Enable/disable HD Audio SSP2/I2S link." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS, - Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS, - Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem, "ReservedPchPreMem", &EN_DIS, - Help "Reserved for Pch Pre-Mem" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters, "PCH USB3 RX HSIO Tuning parameters", HEX, - Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX, - Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS, - Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once." - Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, - Help "Disable or Enable Smbus dynamic power gating." - Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, - Help "Set 1 to clear WDT status, then disable and lock WDT registers." - Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, - Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS, - Help "Reserved for Pch Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, - Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" - Combo $gPlatformFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable message check." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, - Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." - Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, - Help "Test, 0: disable, 1: enable, Enable or Disable KT device." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR, "Teton Glacier Cycle Router", HEX, - Help "Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system " - "Valid range: 0x0 ~ 0x02" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, - Help "Enables Isolated Memory Region for PCIe." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, - Help "Selects PCIE root port number for IMR feature." - "Valid range: 0x0 ~ 23" - Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, "Teton Glacier Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, - Help "Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0Override, "SLP_S0# Override", &gPlatformFspPkgTokenSpaceGuid_SlpS0Override, - Help "Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, "S0ix Override Settings", &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, - Help "Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\nReminder: DCI OOB (aka BSSB) uses CCA probe.\nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for DbC", &EN_DIS, - Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, - Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Device Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, - Help "Enable RAID Alternate ID." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS, - Help "Deprecated." - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS, - Help "Deprecated" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX, - Help "Deprecated" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, - Help "Deprecated" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, - Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, - Help "DMT thermal sensor suggested representative values." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, - Help "Thermal Sensor 1 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, - Help "Thermal Sensor 2 Target Width." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, - Help "Thermal Sensor 3 Target Width." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode, "Enable xHCI Compliance Mode", &EN_DIS, - Help "Compliance Mode can be enabled for testing through this option but this is disabled by default." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, - Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH Sata Rst CPU Attached Storage", &EN_DIS, - Help "CPU Attached Storage" - Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, - Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, - Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, - Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, - Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, - Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, - Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients, "Number of Coefficients to be used", HEX, - Help "The number of coefficients to be used for equalization, default value is 3" - "Valid range: 0x0 ~ 0x5" - Combo $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating, "GPIO RCOMP Community Clock Gating", &EN_DIS, - Help "0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock local clock gating, default value is 1" - Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable SD Card Write Protect Pin", &EN_DIS, - Help "Enable/disable SD Card Write Protect Pin." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, - Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS, - Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem, "ReservedPchPostMem", &EN_DIS, - Help "Reserved for Pch Post-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX, - Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, - Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, - Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, - Help "Force all GPIO pads to be unlocked for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, - Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, - Help "Latency Tolerance Reporting, Max Non-Snoop Latency." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, - Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, - Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, - Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 5." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX, - Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, - Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, - Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, - Help "Disable/Enable PCH to CPU energy report feature." - Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, - Help "Allow entrance to the PCH SATA test modes." - Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, - Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS, - Help "Reserved for Pch Post-Mem Test" - Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, - Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls, "Use DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue, "Emmc Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue, "Emmc Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue, "Emmc Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue, "Emmc Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue, "Emmc Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue, "Emmc Rx Strobe Delay control register value", HEX, - Help "Please see Rx Strobe Delay control register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls, "Use tuned DLL values from policy", &EN_DIS, - Help "Set if FSP should use HS400 DLL values from policy" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue, "SdCard Tx CMD Delay control register value", HEX, - Help "Please see Tx CMD Delay Control register definition for help" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue, "SdCard Tx DATA Delay control 1 register value", HEX, - Help "Please see Tx DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue, "SdCard Tx DATA Delay control 2 register value", HEX, - Help "Please see Tx DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue, "SdCard Rx CMD + DATA Delay control 1 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 1 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue, "SdCard Rx CMD + DATA Delay control 2 register value", HEX, - Help "Please see Rx CMD + DATA Delay control 2 register definition for help" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS, - Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, - Help "Address of LogoPixelHeight" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, - Help "Address of LogoPixelWidth" - "Valid range: 0x0 ~ 0xFFFFFFFF" -EndPage - -Page "PCH 2" - EditNum $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX, - Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, - Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." - Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, - Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &EN_DIS, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): Enable EOP message" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" -EndPage - diff --git a/CometLakeFspBinPkg/CometLakeS/Fsp.fd b/CometLakeFspBinPkg/CometLakeS/Fsp.fd deleted file mode 100644 index 4e60931760492cc66e0d00846f91e7a8062c99a0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 815104 zcmeFYc|6qL_c%Ud24iccQVB&&5t1#tEE$v~WKTp$N(zHyZBoXwQL?1ao}{vrwUB+^ z$(phxV++~0=69b%uUD_v=k@-4-tX_{@%uf#fBdfI`Ml42&pG#;bI&>V-1~fnK>W4% z4Boh*62^PMpdQ1d0WJNM8@M;n#Q>prH^bi6}+{qJ#C%@!?tr^3UgfPzN{!zykt_I7-kr zG(HMdZ0^uy~VCQKE8qa|rj2pCm2e&_p8Uj%%?(TTb?bO;B@L2qy7ry^q)DQ@b z9C(c3t>BUa_YSjz%jnM%`oCIG3`wPEB~AQ_Cvy(qC}@=HB+V0#H>9Qm6_83Xqy>a0 z6Im0_Ygb}NT0nWSQn_I&itr^9sHgTVfTJ>jM^Yg#geakc8p2|q9>V~QQ5#%D)uu{v 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All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - - ## Specifies the AP target C-state for Mwait during POST phase. - # The default value 0 means C1 state. - # The value is defined as below.

- # @Prompt The specified AP target C-state for Mwait. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 20 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress | 0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength | 0x10000000 - - ## Specifies the base address of the first microcode Patch in the microcode Region. - # @Prompt Microcode Region base address. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FirmwareVersionInfoHob.h b/CometLakeFspBinPkg/CometLakeS/Include/FirmwareVersionInfoHob.h deleted file mode 100644 index 4d72102..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FspInfoHob.h b/CometLakeFspBinPkg/CometLakeS/Include/FspInfoHob.h deleted file mode 100644 index 34283b8..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FspInfoHob.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @file - Header file for FSP Information HOB. - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _FSP_INFO_HOB_H_ -#define _FSP_INFO_HOB_H_ - -extern EFI_GUID gFspInfoGuid; - -#pragma pack (push, 1) - -typedef struct { -UINT8 SiliconInitVersionMajor; -UINT8 SiliconInitVersionMinor; -UINT8 SiliconInitVersionRevision; -UINT8 SiliconInitVersionBuild; -UINT8 FspVersionRevision; -UINT8 FspVersionBuild; -UINT8 TimeStamp [12]; -UINT8 FspVersionMinor; -} FSP_INFO_HOB; - -#pragma pack (pop) - -#endif // _FSP_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FspUpd.h b/CometLakeFspBinPkg/CometLakeS/Include/FspUpd.h deleted file mode 100644 index 395a7a1..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FspUpd.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */ - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FspmUpd.h b/CometLakeFspBinPkg/CometLakeS/Include/FspmUpd.h deleted file mode 100644 index cb58672..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FspmUpd.h +++ /dev/null @@ -1,3056 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResistor settings - Indicates RcompResistor settings: CML - 0's means MRC auto configured based on - Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to - provide the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0096 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0097 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0098 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A4 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A6 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A7 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A8 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A9 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00AE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00AF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00B0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00B1 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00B2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00B4 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00B6 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00B7 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00B8 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00B9 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00BA - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00BB - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00BC - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00C0 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00C1 - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00C2 - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00C3 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00C4 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C5 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C6 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C8 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00CA - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00CC - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00CE - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CF - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00D0 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00D1 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00D2 - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00D3 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00D4 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D5 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D6 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D7 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00D8 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00DA - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00DB - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00DC - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00DD - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00DE - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00DF - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00E0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x00E4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x00E8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x00EC - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x00EE - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x00F0 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x00F3 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x00F4 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x00F5 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x00F6 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x00F7 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x00F8 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x00F9 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x00FA - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x00FB - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x00FC - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x00FD - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x00FE - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x00FF - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0100 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0101 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0102 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0105 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x010D - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0115 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0122 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0130 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0134 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0154 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0155 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0156 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0158 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x015C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0160 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01C1 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01C2 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01C3 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01C4 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01C5 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x01C6 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01CA - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01CC - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01CF - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01D0 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01D1 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01D2 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01D3 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01D4 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01DA - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01DB - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[1]; - -/** Offset 0x01DC - Per-core HT Disable - Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, - 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value - of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have - HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1. -**/ - UINT16 PerCoreHtDisable; - -/** Offset 0x01DE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01E0 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01E1 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x01E2 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x01E3 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x01E4 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x01E5 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x01E6 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x01E7 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01E8 - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x01E9 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01EA - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01EC - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01ED - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01EE - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x01EF - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x01F0 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x01F1 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x01F2 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x01F4 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x01F6 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x01F8 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x01F9 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x01FA - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x01FC - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x01FE - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0200 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0201 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0202 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0203 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0204 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0205 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0208 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x020C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0210 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0214 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0218 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0220 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0224 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0228 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x022C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0230 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0238 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0240 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0241 - Intel Speed Optimizer Enable - When enabled this feature automatically overclocks your processor. It changes the - All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AutoEasyOverclock; - -/** Offset 0x0242 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[2]; - -/** Offset 0x0244 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0250 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0251 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x0253 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x0256 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0257 - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0439 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x043A - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x043B - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x043C - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x043E - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0440 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0444 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0448 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0449 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x044A - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x044B - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x044C - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x044D - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x044E -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0450 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0454 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0455 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0456 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0457 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0458 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x045A - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x045B - Enable HD Audio DMIC0 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x045C - Enable HD Audio DMIC1 Link - Deprecated. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x045D - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x045E - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x045F - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0465 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[2]; - -/** Offset 0x0467 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0468 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0469 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x046A - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x046B - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x046C - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x046D - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x046E - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x046F - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0470 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0471 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0472 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0473 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0474 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0475 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0476 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0477 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0478 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0479 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x047A - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x047B - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x047C - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x047D - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x047E - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x047F - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0480 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0481 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0482 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0483 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0484 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0485 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0486 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0487 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0488 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0489 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x048A - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x048B - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x048C - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x048D - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x048E - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x048F - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0490 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0491 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0492 - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x0493 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x0494 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x0495 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x0496 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x0497 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x049A - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x049B - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x049C - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x049D - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x049F - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04A0 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04A1 - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04A2 - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04A5 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x04A6 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04A8 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04AC - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04AD - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04AE - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04B0 - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04B2 - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04B4 - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04B6 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04B7 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04B8 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04B9 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04BA - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04BB -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x04BC - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04BE - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04CA - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04CB - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04CC - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04CD - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04CE - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04CF - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D0 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04D1 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04D2 - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04D3 - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04D8 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04D9 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04DA - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04DB - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04DC - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04DD - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04DE - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04DF - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E0 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04E1 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04E2 - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04E3 - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04E4 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04E5 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04E6 - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04E7 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04E8 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04E9 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04EA - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04EB - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04EC - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04ED - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04EE - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04EF - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F0 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04F1 - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04F2 - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04F3 - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04F4 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04F5 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04F6 - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x04F7 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x04F9 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x04FB - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x04FC - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x04FD - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x04FE - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x04FF - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0500 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x0501 - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x0502 - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x0504 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0505 - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x0506 - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4Mixed2DpcLimit; - -/** Offset 0x0508 - RMT on Fast flow - Enable/Disable RMT on Fast flow. Default: Disabled - $EN_DIS -**/ - UINT8 FastBootRmt; - -/** Offset 0x0509 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl; - -/** Offset 0x050A - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x050B - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x050D - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x050E - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x050F - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x0510 - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control - deprecated -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x0515 - Core VF Point Offset Mode - Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; - 0: Legacy; 1: Selection. - 0:Legacy, 1:Selection -**/ - UINT8 CoreVfPointOffsetMode; - -/** Offset 0x0516 - Core VF Point Offset - Array used to specifies the Offset Voltage applied to the each selected Core VF - Point. This voltage is specified in millivolts. -**/ - UINT16 CoreVfPointOffset[15]; - -/** Offset 0x0534 - Core VF Point Offset Prefix - Sets the CoreVfPointOffset value as positive or negative for corresponding core - VF Point; 0: Positive ; 1: Negative. - 0:Positive, 1:Negative -**/ - UINT8 CoreVfPointOffsetPrefix[15]; - -/** Offset 0x0543 - Core VF Point Ratio - Array for the each selected Core VF Point to display the ration. -**/ - UINT8 CoreVfPointRatio[15]; - -/** Offset 0x0552 - Core VF Point Count - Number of supported Core Voltage & Frequency Point Offset -**/ - UINT8 CoreVfPointCount; - -/** Offset 0x0553 -**/ - UINT8 UnusedUpdSpace8[4]; - -/** Offset 0x0557 -**/ - UINT8 ReservedFspmUpd[1]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0558 -**/ - UINT32 Signature; - -/** Offset 0x055C - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x055D - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x055E - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x055F - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0560 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0561 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0562 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0563 - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x0564 - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x0565 - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x0566 - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x0567 - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0568 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0569 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x056A - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x056B - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x056C - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x056D - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x056E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x056F - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0570 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0571 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x0572 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0573 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0574 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0575 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0589 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x059D - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x05B1 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x05B4 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x05B6 - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x05B8 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x05BA - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x05BB - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x05BC - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x05BD -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x05C0 - Oem T12 Dealy Override - Oem T12 Dealy Override. 0(Default)=Disable 1=Enable - $EN_DIS -**/ - UINT8 OemT12DelayOverride; - -/** Offset 0x05C1 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x05CA - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x05CC - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x05CE - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x05CF - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x05D2 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x05D3 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x05D4 - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x05D5 - ReservedPchPreMemTest - Reserved for Pch Pre-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPreMemTest[16]; - -/** Offset 0x05E5 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05E6 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05E7 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05E8 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05E9 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05EA - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05EB - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05EC - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05ED - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05EE - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05EF - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05F0 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05F1 - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05F2 - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05F3 - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05F4 - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05F5 - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05F6 - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05F7 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05F8 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05F9 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05FA - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05FB - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05FC - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05FD - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05FE - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05FF - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x0600 - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x0601 -**/ - UINT8 ReservedFspmTestUpd[7]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0558 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0608 -**/ - UINT8 UnusedUpdSpace11[6]; - -/** Offset 0x060E -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h b/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h deleted file mode 100644 index ddfcb0c..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h +++ /dev/null @@ -1,3675 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0030 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0034 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0038 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0039 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x003A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x003B - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x003C - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x003D - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x003E - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x003F - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0040 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0041 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0042 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0044 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x0046 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0047 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0048 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0049 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x004A - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x004B - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x004F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x0053 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0058 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0060 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0063 - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x0065 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x0068 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0074 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0075 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0076 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0077 - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x0078 - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x0079 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x007A - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x007B - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x007C - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x007D - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0080 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0084 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0088 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0089 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x00C4 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x00C9 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x00CE - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x00D3 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x00DD - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x00E2 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x00E7 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x00EC - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x00ED - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x00EE - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x00F3 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x00F4 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x00FE - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0108 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x0112 - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x011C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0126 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0130 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x013A - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0146 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0147 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0148 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x014A - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x014B - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x014C - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x014E - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x014F - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x0159 -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x015A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0164 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0168 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0169 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x016A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x016B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x016C - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0170 - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0174 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace8[1]; - -/** Offset 0x0176 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x0180 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0188 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0189 - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x018B - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x018D - SPI2 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi2CsPolarity[2]; - -/** Offset 0x018F - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x0191 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x0193 - SPI2 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi2CsEnable[2]; - -/** Offset 0x0195 - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[3]; - -/** Offset 0x0198 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[3]; - -/** Offset 0x019B - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x01A1 - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x01A7 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01AC - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x01B8 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x01BB - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x01BE - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x01CA - Serial IO UART Pin Mux - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 SerialIoUartPinMux[3]; - -/** Offset 0x01CD - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01CE - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x01D1 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x01D2 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x01D3 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x01D4 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x01D5 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x01D6 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x01DE - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x01E6 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x01F6 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x0200 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0201 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0208 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0209 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0211 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0212 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0213 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x0214 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x0215 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0216 -**/ - UINT8 UnusedUpdSpace11[2]; - -/** Offset 0x0218 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x021C - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x021D - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x021E - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x021F - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x022F - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x023F - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x0287 - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x0288 - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x028C - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x0290 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x0294 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x0295 - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x0296 - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x0297 - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0298 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0299 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x029A - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x029B - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x029C - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x029D - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x029E - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x02A0 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x02A4 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x02A8 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x02AC - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x02AD -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x02B0 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x02B5 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x02B6 -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x02B8 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x02BC - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x02BD -**/ - UINT8 UnusedUpdSpace14[3]; - -/** Offset 0x02C0 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x02C4 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x02C8 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x02C9 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x02CA - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x02CB - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x02CC - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x02CD - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x02CE - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x02CF - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x02D0 - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x02D1 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x02D2 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x02D3 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x02D4 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x02D5 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x02D6 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x02EE - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x02FE - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x030E - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x0326 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x033E - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x036F - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping - CPU and 1 for PCH-H Series. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x0370 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x037B -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x037C - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0386 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0390 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0391 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0392 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x0393 - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x0394 - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x0396 - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0397 - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x03A2 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x03B1 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x03B4 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x03B5 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x03B6 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03CE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03E6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x0416 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x042E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0446 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x045E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0476 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x048E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x04A6 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04D6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04EE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x051A - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x054A - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0562 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x057A - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x0592 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05AA - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05C2 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x060A - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, - the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x060F - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the - default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0614 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0615 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0616 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0617 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0618 - Teton Glacier Cycle Router - Specify to which cycle router Teton Glacier is connected, it is valid only when - Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x061A - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x061B - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x061C - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic - Configuration. Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x061D - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x061F - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0622 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0623 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0624 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0625 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0626 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x0627 - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x0628 - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x0629 - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x062A - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x062B - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x062C - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x062D - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x062E - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0630 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0631 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0632 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0635 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0636 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0637 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x0638 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0639 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0641 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0649 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x0651 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x0659 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x0661 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0669 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x0671 -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x0672 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x0682 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x068A - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x068B - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x068C - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x068D - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x068E - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x068F - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x0692 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x0693 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0694 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0695 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x069F - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06A0 - Set HS400 Tuning Data Valid - Deprecated - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06A1 - Rx Strobe Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06A2 - Tx Data Delay Control - Deprecated -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06A3 - I/O Driver Strength - Deprecated - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06A4 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06A5 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06A6 - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06A7 - PCH eSPI Link Configuration Lock (SBLCL) - Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves - addresseses from range 0x0 - 0x7FF - $EN_DIS -**/ - UINT8 PchEspiLockLinkConfiguration; - -/** Offset 0x06A8 - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06A9 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06B0 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06B1 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06B2 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x06B3 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x06B4 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x06B7 - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x06B8 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x06B9 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x06BA - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x06BB - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x06BC - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x06BD - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x06BE - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x06BF - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x06C0 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x06C1 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x06C2 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x06C3 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x06C5 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x06C8 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x06C9 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x06CB - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x06CD - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x06CF -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x06D0 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x06D2 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x06D3 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x06E3 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x06ED - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x06EE - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x06F1 -**/ - UINT8 UnusedUpdSpace19[3]; - -/** Offset 0x06F4 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x06F8 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x06F9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x06FB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTranEnable[10]; - -/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default - = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate3UniqTran[10]; - -/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTranEnable[10]; - -/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate2UniqTran[10]; - -/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTranEnable[10]; - -/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate1UniqTran[10]; - -/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each - value in array can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTranEnable[10]; - -/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], - Default = 4Ch. One byte for each port. -**/ - UINT8 Usb3HsioTxRate0UniqTran[10]; - -/** Offset 0x074C - Number of Coefficients to be used - The number of coefficients to be used for equalization, default value is 3 -**/ - UINT8 PcieNumOfCoefficients; - -/** Offset 0x074D - GPIO RCOMP Community Clock Gating - 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock - local clock gating, default value is 1 - $EN_DIS -**/ - UINT8 GpioPmRcompCommunityLocalClockGating; - -/** Offset 0x074E - Enable SD Card Write Protect Pin - Enable/disable SD Card Write Protect Pin. - $EN_DIS -**/ - UINT8 ScsSdCardWpPinEnabled; - -/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x0757 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control - 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x075C - ReservedPchPostMem - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[3]; - -/** Offset 0x075F -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0760 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0780 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0784 -**/ - UINT8 UnusedUpdSpace21[4]; - -/** Offset 0x0788 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0790 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0798 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0799 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x079A -**/ - UINT8 UnusedUpdSpace22[6]; - -/** Offset 0x07A0 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x07A8 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x07B0 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07B1 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07B2 -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x07B4 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07B8 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07BA - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07BB - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07BC -**/ - UINT8 UnusedUpdSpace24[3]; - -/** Offset 0x07BF -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07C0 -**/ - UINT32 Signature; - -/** Offset 0x07C4 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07C5 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07C6 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07C7 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07C8 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07C9 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07CD - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07CE - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07CF - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07D0 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07D1 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07D2 - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07D3 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07DE - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07DF - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07E0 - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07E1 - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07E2 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07E3 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07E4 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07E5 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07E6 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07E7 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07E8 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07E9 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07EA - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07EB - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07ED - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07EE - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07EF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07F0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07F1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07F2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07F3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07F4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07F5 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07F6 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07F7 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07F8 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07F9 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07FA - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07FB - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07FC - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0800 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0802 - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x0803 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0804 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x0805 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x0806 -**/ - UINT8 UnusedUpdSpace25[2]; - -/** Offset 0x0808 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0810 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x0814 - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0816 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable, 2: Auto / Silicon default - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0818 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x081B - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x081C - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x081D - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x081E - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x081F - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0820 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0821 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0822 - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0824 - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0825 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0827 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0828 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0829 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x082A - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x082B - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x082C - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x082D - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x082E - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x082F - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0830 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0831 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0832 - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x0833 - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x086B -**/ - UINT8 UnusedUpdSpace26; - -/** Offset 0x086C - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x087A -**/ - UINT8 UnusedUpdSpace27[2]; - -/** Offset 0x087C - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0880 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x0884 - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0888 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x088C - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x08A8 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x08AC - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x08B0 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x08B2 - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x08B3 - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x08B4 - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x08B5 - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver - @deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08BA - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08BB - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08BC - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08BF - Ratio Limit Num Core 0 - Ratio Limit Num Core0: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore0; - -/** Offset 0x08C0 - Ratio Limit Num Core 1 - Ratio Limit Num Core1: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore1; - -/** Offset 0x08C1 - Ratio Limit Num Core 2 - Ratio Limit Num Core2: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore2; - -/** Offset 0x08C2 - Ratio Limit Core 3 - Ratio Limit Num Core3: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore3; - -/** Offset 0x08C3 - Ratio Limit Num Core 4 - Ratio Limit Num Core4: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore4; - -/** Offset 0x08C4 - Ratio Limit Num Core 5 - Ratio Limit Num Core5: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore5; - -/** Offset 0x08C5 - Ratio Limit Num Core 6 - Ratio Limit Num Core6: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore6; - -/** Offset 0x08C6 - Ratio Limit Num Core 7 - Ratio Limit Num Core7: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore7; - -/** Offset 0x08C7 - Dual Tau Boost - Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 DualTauBoost; - -/** Offset 0x08C8 - ITBMT 3.0 Runtime Periodic SMM timer - Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic - SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, - 6 - 32 sec, 7 - 64 sec. -**/ - UINT8 ItbmPeriodicSmmTimer; - -/** Offset 0x08C9 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[9]; - -/** Offset 0x08D2 - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08D3 - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): - Enable EOP message - $EN_DIS -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08D4 - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08D5 -**/ - UINT8 UnusedUpdSpace28; - -/** Offset 0x08D6 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08D8 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08DA - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08DB - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x096C - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x0A14 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A75 - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A76 - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A77 - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A79 - ReservedPchPostMemTest - Reserved for Pch Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPostMemTest[16]; - -/** Offset 0x0A89 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A8A - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0A8B -**/ - UINT8 UnusedUpdSpace29; - -/** Offset 0x0A8C - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0AA4 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x0AA5 -**/ - UINT8 UnusedUpdSpace30[3]; - -/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x0ABC - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0ABD -**/ - UINT8 UnusedUpdSpace31[3]; - -/** Offset 0x0AC0 - LogoPixelHeight Address - Address of LogoPixelHeight -**/ - UINT32 LogoPixelHeight; - -/** Offset 0x0AC4 - LogoPixelWidth Address - Address of LogoPixelWidth -**/ - UINT32 LogoPixelWidth; - -/** Offset 0x0AC8 -**/ - UINT8 UnusedUpdSpace32[4]; - -/** Offset 0x0ACC -**/ - UINT8 ReservedFspsTestUpd[4]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07C0 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0AD0 -**/ - UINT8 UnusedUpdSpace33[6]; - -/** Offset 0x0AD6 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeS/Include/FsptUpd.h b/CometLakeFspBinPkg/CometLakeS/Include/FsptUpd.h deleted file mode 100644 index 9617105..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/FsptUpd.h +++ /dev/null @@ -1,180 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) - 0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 PcdSerialIoUartPinMux; - -/** Offset 0x0059 - PcdLpcUartDebugEnable - Enable to initialize LPC Uart device in FSP. - 0:Disable, 1:Enable -**/ - UINT8 PcdLpcUartDebugEnable; - -/** Offset 0x005A - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x005B - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x005C - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x005D -**/ - UINT8 UnusedUpdSpace1[7]; - -/** Offset 0x0064 -**/ - UINT8 ReservedFsptUpd1[20]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0078 -**/ - UINT8 UnusedUpdSpace2[6]; - -/** Offset 0x007E -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeS/Include/GpioConfig.h b/CometLakeFspBinPkg/CometLakeS/Include/GpioConfig.h deleted file mode 100644 index eed3cb2..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/GpioConfig.h +++ /dev/null @@ -1,329 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - -@copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 9; - UINT32 RsvdBits : 10; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, - GpioPadModeNative5 = 0xB -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Configuration options for GPIO termination setting -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. - By default GPIO pads will be locked unless GPIO lib is explicitly - informed that certain pad is to be left unlocked. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controlled - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock - an already locked pad upon request for reconfiguration -**/ -typedef enum { - /** - Perform default action - - if pad is an GPO, lock configuration but leave output unlocked - - if pad is an GPI, lock everything - - if pad is in native, lock everything -**/ - GpioLockDefault = 0x0, - GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked - GpioPadConfigLock = 0x1, ///< Lock Pad configuration - GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked - GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked - GpioPadLock = 0x5 ///< Lock both Pad configuration and output control -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/GpioSampleDef.h b/CometLakeFspBinPkg/CometLakeS/Include/GpioSampleDef.h deleted file mode 100644 index 9cfc7c7..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/GpioSampleDef.h +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Sample enum definitions for GPIO table. - - @copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/HobUsageDataHob.h b/CometLakeFspBinPkg/CometLakeS/Include/HobUsageDataHob.h deleted file mode 100644 index 2712130..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/HobUsageDataHob.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Definitions for Hob Usage data HOB - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _HOB_USAGE_DATA_HOB_H_ -#define _HOB_USAGE_DATA_HOB_H_ - -extern EFI_GUID gHobUsageDataGuid; - -#pragma pack (push, 1) - -/** - Hob Usage Data Hob - - Revision 1: - - Initial version. -**/ -typedef struct { - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - UINTN FreeMemory; -} HOB_USAGE_DATA_HOB; - -#pragma pack (pop) - -#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/MemInfoHob.h b/CometLakeFspBinPkg/CometLakeS/Include/MemInfoHob.h deleted file mode 100644 index 1c94e8e..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/MemInfoHob.h +++ /dev/null @@ -1,263 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; - -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/SmbiosCacheInfoHob.h b/CometLakeFspBinPkg/CometLakeS/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index 87913d9..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 - // - // Add for smbios 3.1.0 - // - UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/Include/SmbiosProcessorInfoHob.h b/CometLakeFspBinPkg/CometLakeS/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index 1fa6795..0000000 --- a/CometLakeFspBinPkg/CometLakeS/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeS/README.md b/CometLakeFspBinPkg/CometLakeS/README.md deleted file mode 100644 index 03e8d69..0000000 --- a/CometLakeFspBinPkg/CometLakeS/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# CometLakeFspBinPkg/CometLakeS -These FSP binaries are intended to be used with 10th Generation Intel® Core™ desktop processors and chipsets formerly known as Comet Lake with a 14nm Platform Controller Hub (PCH). Please consult CometLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use. diff --git a/CometLakeFspBinPkg/CometLakeS/SampleCode/Vbt/Vbt.bin b/CometLakeFspBinPkg/CometLakeS/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index e801e45246d84e43bc6439b6fdda257a20675aa9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKU2GIp6h5=FzjtP~vr{7573<+Auv=)EEwExOakjgyUAnN_ZfQz1=>of8!$NC+ zv=~g+q){G}?1LIKD19L+FXEH&4c|yilxTuaModgle38hD0U6Kyw2LKa7a}NzZ};4D z?wLE^oclBPo>?={(T};F-RXEwC)y~03a0~pDsM+eDw7*Z#{1(#9qCM>2Y-S`U?Ony z3P6G58pNooMpK6;iluO0glN;aV`T4eskkv&96vZQGK$$m3gi3s6-&jjJrl(O<_4aL zqroY$j>+Lt0e4Ow+FKlJLn2bCHAXkLY}$+%-PlThHM)gNwJjQJ+w!EulAVdnj%+F& z?@wiRVx|w1sa!ml>)g?i-i_J5On0gy)!&(v*nBq!MpRGU+@M_>i@XFxSz=`0L zK||1FKpDIMP5=!60c0Zx864X<2l>`{!5uU_b0B)&v^Ar#4Pt|fd5~qV;Hdc0}L z99jm|=yC9k*=&v7%mF}u1033h(F|?2nB9z&^-z^V%b+{Z4poM3yP04R8Nk0aGhO$) z;5mRBFVj;=8{mL50O03TIPPnN3?GK0yaQh2w?dQiJg7c|oKJ@RBu7ZTbusv!Zr}wClR= z%Tv{1E|7awvM+%av;|#%&@HhZw$q!)d)sGLn0?s=pr4X>m;x4{cie^|&MivQvFrnI zhpbDU_PI6-^}l%~Wb6!&iu?r+gA1N(+_C!qre%zoyu{BMS6vU-u<8%Xha+%jBe0?y zF8az9y!4pt&9AcVZM-|rW2gYvxzpxr4eIXKgM- zsGC39t2f_jg&T={{8o=?pCMSz$Xmc4VE86ePBHc|!>^h0BV)fZ3<%0BiA_s*T2elf*cTFBmXtpv#``hiSDx~-PCp*>E3f$3>wc+8ag`mHxH6@n zMtu2zb?fLPynSL~)07YxofDBCbS%v8GHXa0W7F25 zNb^No{?ZJE2GHWLRt+ADSq#D0G;gI<6ec(ghW15!p*F#ZUQji4w0=GYy3w%3DOac_ zhAHd~$(no%16Og~0mDZdr!Mt|)@p+%sxfdCx5=Qn&(;t__tToX_iU@CovSjqtt?3# zaMd!B`&SN}>4iqMt76ZEF_IPYe5Fuo8Hb}SmDzl#QB%>L3z|)5#mr*GvZt0_gxkxr zqi0tWLzB^W0Ag@e%v?sCb-2yA}quNjsmPDX76- zD`zxf;AuG$?siR@43fp*!Ww#UB?PlsT&{|0qS}iJy^j<_*|XJL4~xH>j<#~}g{{rn zU~_dYc&M{tps$~$-;0O_`7+e!WjRodfi_YjhIChUD7)uyv9xo~q2m9bVs&t_a{a5| z-hQ6)_%rve)EB_902^ZPMi&K{qU?Sb9bg66z`X-M^RyLPpuE_GdjVQh4vx*^!7#1K UnEQCS?|PH{@x9oZ_y?~21+7}z9{>OV diff --git a/CometLakeFspBinPkg/CometLakeS/SampleCode/Vbt/Vbt.bsf b/CometLakeFspBinPkg/CometLakeS/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index 30ec8b8..0000000 --- a/CometLakeFspBinPkg/CometLakeS/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11683 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Coffeelake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from CFL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for CFL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x01, "Pin-Pair #1" - Selection 0x02, "Pin-Pair #2" - Selection 0x03, "Pin-Pair #3" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Coffeelake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if theres no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel Rapid Memory Power Management (RMPM)\r\n" - "2. Intel Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop CFL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Coffeelake, based on the selection respective table will be used.\r\n" - "Tables for Coffeelake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel Automatic Display Brightness is to be enabled. " - "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - "Below is recommended Pin-Pair to Port mapping based on PCH used:" - - "\r\n--------------------------------------------------------------\r\n" - "| Pin Pair Values | CNL-PCH Port Mapping | \r\n" - "--------------------------------------------------------------\r\n" - "| N/A | Not Used | \r\n" - "| Pin-Pair #1 | DDI-B DDC | \r\n" - "| Pin-Pair #2 | DDI-C DDC | \r\n" - "| Pin-Pair #3 | DDI-D DDC | \r\n" - "--------------------------------------------------------------\r\n" - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/CometLakeFspBinPkg/CometLakeV/CometLakeFspBinPkg.dec b/CometLakeFspBinPkg/CometLakeV/CometLakeFspBinPkg.dec deleted file mode 100644 index 1c0b637..0000000 --- a/CometLakeFspBinPkg/CometLakeV/CometLakeFspBinPkg.dec +++ /dev/null @@ -1,29 +0,0 @@ -## @file -# Component description file for CometLake Fsp Bin package. -# -# @copyright -# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = CometLakeFspBinPkg - PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 - PACKAGE_VERSION = 1.02 - -[Includes] - Include - -[Guids] - gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }} - -[Ppis] - gEfiReadyToInstallPciEnumerationCompleteProtocolGuid = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }} - gEfiReadyToInstallEventReadyToBootGuid = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }} - gFspReadyToInstallEventEndOfFirmwareGuid = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }} - gEndOfFspS3NotifyGuid = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }} - gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }} diff --git a/CometLakeFspBinPkg/CometLakeV/Fsp.bsf b/CometLakeFspBinPkg/CometLakeV/Fsp.bsf deleted file mode 100644 index 6d67f7b..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Fsp.bsf +++ /dev/null @@ -1,4341 +0,0 @@ -/** @file - - Boot Setting File for Platform Configuration. - - Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - - - -GlobalDataDef - SKUID = 0, "DEFAULT" -EndGlobalData - - -StructDef - - Find "CMLUPD_T" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xE0000000 - $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_M" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x00 - Skip 55 bytes - $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x100 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1 12 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0 8 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5 - $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1 8 bytes $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4 - $gPlatformFspPkgTokenSpaceGuid_RcompResistor 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_IedSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 - $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize 1 bytes $_DEFAULT_ = 0x0C - $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OddRatioMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn2 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DllBwEn3 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort 1 bytes $_DEFAULT_ = 0x99 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 4 - $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFED1A000 - $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFED1B000 - $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFED1C000 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 - $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 - $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Peg0Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking 10 bytes $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PegDataPtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGpioData 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xD0000000 - $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xCF000000 - $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_EnableSgx 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHpetEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHpetBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHpetBase 4 bytes $_DEFAULT_ = 0xFED00000 - $gPlatformFspPkgTokenSpaceGuid_PchHpetBusNumber 1 bytes $_DEFAULT_ = 0xF0 - $gPlatformFspPkgTokenSpaceGuid_PchHpetDeviceNumber 1 bytes $_DEFAULT_ = 0x1F - $gPlatformFspPkgTokenSpaceGuid_PchHpetFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchAcpiBase 2 bytes $_DEFAULT_ = 0x1800 - $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 - $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemReg0Size 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemReg1Size 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF - $gSiPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x12 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 - $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem 16 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 - $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x001 - $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MemoryTrace 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableCltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableOltm 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhPrevention 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 - $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A - $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B - $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RhActProbability 1 bytes $_DEFAULT_ = 0xB - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr 2 bytes $_DEFAULT_ = 0xDE - $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0x06 - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xD4 - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1 1 bytes $_DEFAULT_ = 0xDD - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x30 - $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping 1 bytes $_DEFAULT_ = 0xAA - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RhSolution 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax 1 bytes $_DEFAULT_ = 0x69 - $gPlatformFspPkgTokenSpaceGuid_TsodEventMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TsodThigMax 1 bytes $_DEFAULT_ = 0x5D - $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_GdxcEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_FivrFaults 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 - $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnBER 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FastBootRmt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x40 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 - Skip 5 bytes - $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 - $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime 2 bytes $_DEFAULT_ = 3000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime 2 bytes $_DEFAULT_ = 10000 - $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget 2 bytes $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x1 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 - $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchDciEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ChipsetInitMessage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BypassPhySyncReset 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 - - Find "CMLUPD_S" - $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01 - Skip 23 bytes - $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis 4 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01 - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue 4 bytes $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B - $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber 8 bytes $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0x3 - $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated 1 bytes $_DEFAULT_ = 0x0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE - $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE - $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 34 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_ImonOffset 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysOffset 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Reserved2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_IslVrCmd 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonSlope1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_CpuMpHob 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_ImonOffset1 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 8 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkSrcNumber 24 bytes $_DEFAULT_ = 0x02, 0x1f, 0x1f, 0x1f, 0x03, 0x01, 0x1f, 0x1f, 0x05, 0x04, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f - $gPlatformFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchCio2Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity 2 bytes $_DEFAULT_ = 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity 2 bytes $_DEFAULT_ = 0x00, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x02 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 12 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 3 bytes $_DEFAULT_ = 0x08, 0x08, 0x08 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 3 bytes $_DEFAULT_ = 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 3 bytes $_DEFAULT_ = 0x01, 0x01, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SsicPortEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B - $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 - Skip 3 bytes - $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset 16 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp 16 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DelayUsbPdoProgramming 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqSupport 24 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqNumber 24 bytes $_DEFAULT_ = 0x02, 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x05, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClkReqSupport 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClkReqNumber 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortATermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDTermOvrEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortATrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDTrimEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleCapValue 1 bytes $_DEFAULT_ = 0x0E - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleResValue 1 bytes $_DEFAULT_ = 0x0D - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortAClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCClkTrimValue 1 bytes $_DEFAULT_ = 0x09 - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDClkTrimValue 1 bytes $_DEFAULT_ = 0x0A - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortADataTrimValue 2 bytes $_DEFAULT_ = 0xBBBB - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBDataTrimValue 2 bytes $_DEFAULT_ = 0xBBBB - $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDDataTrimValue 2 bytes $_DEFAULT_ = 0xCCCC - $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferVoltage 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicBdfValid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicBusNumber 1 bytes $_DEFAULT_ = 0xF0 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicDeviceNumber 1 bytes $_DEFAULT_ = 0x1F - $gPlatformFspPkgTokenSpaceGuid_PchIoApicFunctionNumber 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLanK1OffEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanClkReqSupported 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLanClkReqNumber 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownSpiEiss 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDeviceResetPadActiveHigh 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 24 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 - $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PcieRpDeviceResetPad 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm 24 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 - $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 24 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm 5 bytes $_DEFAULT_ = 0x06, 0x04, 0x08, 0x02, 0x0A - $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp 5 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieAllowNoLtrIccPllShutdown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPort61hEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02 - $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaidAlternateId 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 - $gPlatformFspPkgTokenSpaceGuid_SerialIoGpio 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cVoltage 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSirqMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchThermalDeviceEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_PchDisableComplianceMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 - $gPlatformFspPkgTokenSpaceGuid_Early8254ClockGatingEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HybridStorageMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem 8 bytes $_DEFAULT_ = 0x00 - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF - Skip 4 bytes - $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF - Skip 6 bytes - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF - $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 - $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 - Skip 8 bytes - $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 - $gPlatformFspPkgTokenSpaceGuid_DmiExtSync 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_DmiIot 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload 4 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF - $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 11 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0F - $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x1C - $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 - $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase 8 bytes $_DEFAULT_ = 0x0000000000000000 - $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 - $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - Skip 1 bytes - $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl 2 bytes $_DEFAULT_ = 0x4B - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0x76 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0x94 - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0xFA - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0x14C - $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0x3F2 - Skip 2 bytes - $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x1B58 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x3A98 - $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x5208 - $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x9C40 - $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0xC350 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer 1 bytes $_DEFAULT_ = 0x04 - $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 9 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm 1 bytes $_DEFAULT_ = 0xFF - $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x1 - $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer 2 bytes $_DEFAULT_ = 0x258 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchSbiUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 48 bytes $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 24 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 - $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 48 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp 24 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 - $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp 24 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 - $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_PchXhciOcEnable 1 bytes $_DEFAULT_ = 0x01 - $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem 16 bytes $_DEFAULT_ = 0x00 - $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x0 - $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 - $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 - -EndStruct - - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux - Selection 0 , " GPIO C8 to C11" - Selection 1 , " GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase - Selection 0 , "0x3F8" - Selection 1 , "0x2F8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1600 , "1600" - Selection 1867 , "1867" - Selection 2133 , "2133" - Selection 2400 , "2400" - Selection 2667 , "2667" - Selection 2933 , "2933" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RhSolution - Selection 0 , "Hardware RHP" - Selection 1 , "2x Refresh" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TsegSize - Selection 0x0400000 , "4MB" - Selection 0x01000000 , "16MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidAlternateId - Selection 0 , "Client" - Selection 1 , "Alternate" - Selection 2 , "Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SmramMask - Selection 0 , " Neither" - Selection 1 , "AB-SEG" - Selection 2 , "H-SEG" - Selection 3 , " Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration - Selection 0 , "IPU Camera" - Selection 1 , "IPU Gen" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit - Selection 0 , "BIT6" - Selection 1 , "BIT7" - Selection 2 , "BIT8" - Selection 3 , "BIT9" - Selection 4 , "BIT10" - Selection 5 , "BIT11" - Selection 6 , "BIT12" - Selection 7 , "BIT13" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType - Selection 0 , "1DPC" - Selection 1 , "2DPC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ratio - Selection 0 , "Auto" - Selection 4 , "4" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 9 , "9" - Selection 10 , "10" - Selection 11 , "11" - Selection 12 , "12" - Selection 13 , "13" - Selection 14 , "14" - Selection 15 , "15" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl - Selection 0 , "Disabled" - Selection 1 , "L0s" - Selection 2 , "L1" - Selection 3 , "L0sL1" - Selection 4 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets - Selection 0 , "P7 P3 P5" - Selection 1 , "P0 to P9" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom - Selection 0 , "Before" - Selection 1 , "After" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber - Selection 0 , "SerialIoUart0" - Selection 1 , "SerialIoUart1" - Selection 2 , "SerialIoUart2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable - Selection 0 , "Disable phase2" - Selection 1 , "Enable phase2" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_VddVoltage - Selection 0 , "Default" - Selection 1200 , "1.20 Volts" - Selection 1250 , "1.25 Volts" - Selection 1300 , "1.30 Volts" - Selection 1350 , "1.35 Volts" - Selection 1400 , "1.40 Volts" - Selection 1450 , "1.45 Volts" - Selection 1500 , "1.50 Volts" - Selection 1550 , "1.55 Volts" - Selection 1600 , "1.60 Volts" - Selection 1650 , "1.65 Volts" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner - Selection 1 , " HALT loop" - Selection 2 , " MWAIT loop" - Selection 3 , " RUN loop" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SaGv - Selection 0 , "Disabled" - Selection 1 , "FixedLow" - Selection 2 , "FixedHigh" - Selection 3 , "Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax - Selection 0xFF , " Auto(Default)" - Selection 2 , " 100 Mhz" - Selection 3 , " 150 Mhz" - Selection 4 , " 200 Mhz" - Selection 5 , " 250 Mhz" - Selection 6 , " 300 Mhz" - Selection 7 , " 350 Mhz" - Selection 8 , " 400 Mhz" - Selection 9 , " 450 Mhz" - Selection 0xA , " 500 Mhz" - Selection 0xB , " 550 Mhz" - Selection 0xC , " 600 Mhz" - Selection 0xD , " 650 Mhz" - Selection 0xE , " 700 Mhz" - Selection 0xF , " 750 Mhz" - Selection 0x10 , " 800 Mhz" - Selection 0x11 , " 850 Mhz" - Selection 0x12 , "900 Mhz" - Selection 0x13 , " 950 Mhz" - Selection 0x14 , " 1000 Mhz" - Selection 0x15 , " 1050 Mhz" - Selection 0x16 , " 1100 Mhz" - Selection 0x17 , " 1150 Mhz" - Selection 0x18 , " 1200 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount - Selection 0 , "All" - Selection 1 , "1" - Selection 2 , "2" - Selection 3 , "3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode - Selection 0 , "SerialIoUartDisabled" - Selection 1 , "SerialIoUartPci" - Selection 2 , "SerialIoUartHidden" - Selection 3 , "SerialIoUartCom" - Selection 4 , "SerialIoUartSkipInit" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IedSize - Selection 0 , " Disable" - Selection 0x400000 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected - Selection 0 , "Default profile" - Selection 1 , "Custom profile" - Selection 2 , "XMP profile 1" - Selection 3 , "XMP profile 2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis - Selection 0 , " -6dB" - Selection 1 , " -3.5dB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport - Selection 0 , " Disable" - Selection 1 , " Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent - Selection 0 , "Disabled" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc - Selection 0x00 , "0 MB" - Selection 0x01 , "32 MB" - Selection 0x02 , "64 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency - Selection 100000000 , "100Hz" - Selection 125000000 , "125Hz" - Selection 167000000 , "167Hz" - Selection 250000000 , "250Hz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay - Selection 0 , "iGFX" - Selection 1 , "PEG" - Selection 2 , "PCIe Graphics on PCH" - Selection 3 , "AUTO" - Selection 4 , "Switchable Graphics" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable - Selection 0 , "Disable" - Selection 1 , "Enable and Initialize" - Selection 2 , "Enable without Initializing" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DmiAspm - Selection 0 , "Disable" - Selection 2 , "L1" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BootFrequency - Selection 0 , "0" - Selection 1 , "1" - Selection 2 , "2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth - Selection 0 , "Auto" - Selection 1 , "x1" - Selection 2 , "x2" - Selection 3 , "x4" - Selection 4 , "x8" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes - Selection 0 , "No power saving" - Selection 1 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode - Selection 0 , " Disable" - Selection 1 , "Target Debugger Mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay - Selection 0 , " No Delay" - Selection 0xFFFF , " Auto Calulate T12 Delay" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode - Selection 0 , " EDRAM SW disable" - Selection 1 , " EDRAM SW Enable" - Selection 2 , " EDRAM HW mode" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_BdatTestType - Selection 0 , "Rank Margin Tool" - Selection 1 , "Margin2D" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataMode - Selection 0 , "AHCI" - Selection 1 , "RAID" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_tWR - Selection 0 , "Auto" - Selection 5 , "5" - Selection 6 , "6" - Selection 7 , "7" - Selection 8 , "8" - Selection 10 , "10" - Selection 12 , "12" - Selection 14 , "14" - Selection 16 , "16" - Selection 18 , "18" - Selection 20 , "20" - Selection 24 , "24" - Selection 30 , "30" - Selection 34 , "34" - Selection 40 , "40" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme - Selection 0 , " Single Range Output" - Selection 1 , " ToPA Output" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen - Selection 0x100 , "256 Bytes" - Selection 0x200 , "512 Bytes" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate - Selection 0 , "Disable" - Selection 1 , "1 CMD" - Selection 2 , "2 CMDS" - Selection 3 , "3 CMDS" - Selection 4 , "4 CMDS" - Selection 5 , "5 CMDS" - Selection 6 , "6 CMDS" - Selection 7 , "7 CMDS" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0 - Selection 0 , "Enable both DIMMs" - Selection 1 , "Disable DIMM0" - Selection 2 , "Disable DIMM1" - Selection 3 , "Disable both DIMMs" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig - Selection 0 , "VREF_CA goes to both CH_A and CH_B" - Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B" - Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot - Selection 0 , "Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize - Selection 0 , "32MB" - Selection 1 , "288MB" - Selection 2 , "544MB" - Selection 3 , "800MB" - Selection 4 , "1024MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking - Selection 0 , "Normal Operation" - Selection 1 , "Disable SSC" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency - Selection 0 , "800 MHz" - Selection 1 , " 1 GHz" - Selection 2 , " 400 MHz" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable - Selection 0 , " False" - Selection 1 , " True" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming - Selection 0 , " Disabled" - Selection 1 , " Enabled" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size - Selection 0 , "0" - Selection 1 , "1MB" - Selection 2 , "8MB" - Selection 3 , "64MB" - Selection 4 , "128MB" - Selection 5 , "256MB" - Selection 6 , "512MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow - Selection 0 , " Disable" - Selection 1 , "Enable" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable - Selection 0 , "Disabled" - Selection 1 , "Enabled" - Selection 2 , "No Change" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit - Selection 0x0 , "0xFF" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Refresh2X - Selection 0 , "Disable" - Selection 1 , "Enabled for WARM or HOT" - Selection 2 , "Enabled HOT only" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "AUTO" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed - Selection 0 , "Auto" - Selection 1 , "Gen1" - Selection 2 , "Gen2" - Selection 3 , "Gen3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership - Selection 0 , "HD-A Link" - Selection 1 , "Shared HD-A Link and I2S Port" - Selection 3 , "I2S Ports" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits - Selection 0 , " DefaultStopBits" - Selection 1 , " OneStopBit" - Selection 2 , " OneFiveStopBits" - Selection 3 , " TwoStopBits" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear - Selection 0 , " Disable ME Unconfig On Rtc Clear" - Selection 1 , " Enable ME Unconfig On Rtc Clear" - Selection 2 , " Cmos is clear" - Selection 3 , " Reserved" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_RefClk - Selection 0 , "133MHz" - Selection 1 , "100MHz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize - Selection 0 , "Default" - Selection 1 , " 1 Byte" - Selection 2 , " 1 KB" - Selection 3 , " Max value" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable - Selection 0 , "Disable" - Selection 1 , "Enable" - Selection 2 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CdClock - Selection 0 , " 337.5 Mhz" - Selection 1 , " 450 Mhz" - Selection 2 , " 540 Mhz" - Selection 3 , " 675 Mhz" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GttSize - Selection 1 , "2MB" - Selection 2 , "4MB" - Selection 3 , "8MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_EnableSgx - Selection 0 , " Disable" - Selection 1 , " Enable" - Selection 2 , " Software Control" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck - Selection 0 , "Disable" - Selection 1 , "L1" - Selection 2 , "L2" - Selection 3 , "Both" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode - Selection 0 , " Adaptive" - Selection 1 , " Override" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method - Selection 0 , "Auto" - Selection 1 , "HwEq" - Selection 2 , "SwEq" - Selection 3 , "StaticEq" - Selection 4 , "BypassPhase3" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber - Selection 0 , "UART0" - Selection 1 , "UART1" - Selection 2 , "UART2" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit - Selection 1067 , "1067" - Selection 1333 , "1333" - Selection 1400 , "1400" - Selection 1600 , "1600" - Selection 1800 , "1800" - Selection 1867 , "1867" - Selection 2000 , "2000" - Selection 2133 , "2133" - Selection 2200 , "2200" - Selection 2400 , "2400" - Selection 2600 , "2600" - Selection 2667 , "2667" - Selection 2800 , "2800" - Selection 2933 , "2933" - Selection 3000 , "3000" - Selection 3200 , "3200" - Selection 0 , "Auto" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix - Selection 0 , "Positive" - Selection 1 , "Negative" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel - Selection 0 , "Disable" - Selection 1 , "Error Only" - Selection 2 , "Error and Warnings" - Selection 3 , "Load Error Warnings and Info" - Selection 4 , "Load Error Warnings and Info & Event" - Selection 5 , "Load Error Warnings Info and Verbose" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt - Selection 0 , "Msix" - Selection 1 , "Msi" - Selection 2 , "Legacy" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_ApertureSize - Selection 0 , "128 MB" - Selection 1 , "256 MB" - Selection 3 , "512 MB" - Selection 7 , "1024 MB" - Selection 15 , " 2048 MB" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_HybridStorageMode - Selection 0 , " Disabled" - Selection 1 , " Dynamic Configuration" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate - Selection 3 , "9600" - Selection 4 , "19200" - Selection 6 , "56700" - Selection 7 , "115200" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr - Selection 0 , " Fast/2" - Selection 1 , " Fast/4" - Selection 2 , " Fast/8" - Selection 3 , " Fast/16" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_UserBd - Selection 0 , "Mobile/Mobile Halo" - Selection 1 , "Desktop/DT Halo" - Selection 5 , "ULT/ULX/Mobile Halo" - Selection 7 , "UP Server" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity - Selection 0 , " DefaultParity" - Selection 1 , " NoParity" - Selection 2 , " EvenParity" - Selection 3 , " OddParity" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode - Selection 0 , "Legacy" - Selection 1 , "Selection" -EndList - -List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode - Selection 0 , " Disable" - Selection 1 , " Target Debugger Mode" - Selection 2 , " Host Debugger Mode" -EndList - -BeginInfoBlock - PPVer "0.1" - Description "Comet Lake Platform" -EndInfoBlock - -Page "System Agent 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, - Help "Base address to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, - Help "Region Length to be programmed for Pci Express" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, - Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, - Help "Size of memory preallocated for internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, - Help "Enable/disable internal graphics." - Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, - Help "Select the Aperture Size." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, - Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, - Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, - Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, - Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS, - Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's" - Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS, - Help "Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, - Help "0: Disable, 1: Enable (Default) timeout check for HECI" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, - Help "BAR address of HECI1" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, - Help "BAR address of HECI2" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, - Help "BAR address of HECI3" - "Valid range: 0x00 ~ 0xFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX, - Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX, - Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, - Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable, - Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, - Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, - Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width" - Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, - Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" - Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, - Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, - Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, - Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, - Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" - Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, - Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX, - Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX, - Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX, - Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX, - Help "0(Default): Disable, 1: Enable" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, - Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" - Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, - Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, - Help "1=2MB, 2=4MB, 3=8MB, Default is 3" - EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, - Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, - Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX, - Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX, - Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX, - Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX, - Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, - Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" - Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, - Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, - Help "0(Default)=Minimal/Auto, 60=Maximum" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, - Help "0(Default)=Minimal, 1000=Maximum" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX, - Help "Root port Index number to indicate which PCIe root port has dGPU" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, - Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, - Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" - Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, - Help "0:IPU Camera, 1:IPU Gen Default is 0" - Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, - Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" - Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, - Help "0(Default): Adaptive, 1: Override" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 1000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, - Help "0(Default)=Minimal, 2000=Maximum" - "Valid range: 0 ~ 2000" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX, - Help "0(Default)=Minimal, 60=Maximum" - "Valid range: 0 ~ 60" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Production" - EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, - Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1." - "Valid range: 0x00 ~ 0x1FF" - Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, - Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, - Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, - Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." - Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, - Help "Over clocking support; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, - Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, - Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, - Help "Core voltage mode; 0: Adaptive; 1: Override." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS, - Help "Program Cache Attributes; 0: Program; 1: Disable Program." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, - Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, - Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, - Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, - Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode." - Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, - Help "Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: 2 ;3: 3 " - Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, - Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, - Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, - Help "Enable or Disable VMX; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, - Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." - "Valid range: 0x00 ~ 0x1F" - Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, - Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, - Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, - Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, - Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, - Help "Ring voltage mode; 0: Adaptive; 1: Override." - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, - Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, - Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, - Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" - "Valid range: 0x00 ~ 0x3E8" - EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, - Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" - "Valid range: 0x0A ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx, - Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control" - Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, - Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, - Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, - Help "IsTPMPresence default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS, - Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, - Help "Reserved for Security Pre-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, - Help "Core PLL voltage offset. 0: No offset. Range 0-63" - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, - Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms" - Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, - Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " -EndPage - -Page "System Agent 2" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, - Help "Points to PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, - Help "Size of PEI Display Logo Image" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, - Help "Points to VBT" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, - Help "Enable/disable Device 4" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, - Help "Memory Base of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, - Help "Size of Microcode Updates" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, - Help "Enable/Disable Turbo mode. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, - Help "Central Write Buffer feature configurable and disabled by default" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, - Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS, - Help "Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." - Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, - Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, - Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx." - Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." - Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS, - Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution." - Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, - Help "Enable: SA CRID, Disable (Default): SA CRID" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm, - Help "0=Disable, 2(Default)=L1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX, - Help "0: -6dB, 1(Default): -3.5dB" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX, - Help "Slot power limit value per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX, - Help "Slot power limit scale per root port" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX, - Help "Physical Slot Number per root port" - "Valid range: 0 ~ 8191" - Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, - Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" - Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, - Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, - Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit" - Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, - Help "0=Disable/Clear, 1=Enable/Set" - EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX, - Help "Base addresses for VT-d MMIO access per VT-d engine" - "Valid range: 0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS, - Help "0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS, - Help "0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS, - Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent" - Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, - Help "DEPRECATED" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, - Help "Address of Blt buffer" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, - Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX, - Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]" - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, - Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, - Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, - Help "DEPRECATED" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, - Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" - "Valid range: 0x00 ~ 0xC8" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, - Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, - Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, - Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, - Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, - Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX, - Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, - Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, - Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, - Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, - Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, - Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS, - Help "VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved." - Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, - Help "Enable or Disable TXT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS, - Help "@deprecated SkipMpInit has been moved to FspmUpd" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-)." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX, - Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, - Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, - Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100)." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS, - Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" - Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, - Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, - Help "Pointer CPU BIST Data" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX, - Help "Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, - Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, - Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, - Help "Pointer for CpuMpPpi" - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX, - Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, - Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" - EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX, - Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, - Help "Reserved for CPU Post-Mem Production" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, - Help "Enable/disable HD Audio DSP feature." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership, "Select HDAudio IoBuffer Ownership", &gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferOwnership, - Help "Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkSrcNumber, "Configure CLKSRC Number", HEX, - Help "Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable, "Force Disable clock ", HEX, - Help "Disables clock even if link is inactive default value is 0" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchCio2Enable, "Enable CIO2 Controller", &EN_DIS, - Help "Enable/disable SKYCAM CIO2 Controller." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity, "SPI0 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity, "SPI1 Chip Select Polarity", HEX, - Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable, "SPI0 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable, "SPI1 Chip Select Enable", HEX, - Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, - Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, - Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, - Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, - Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, - Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, - Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, - Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, - Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, - Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" - "Valid range: 0x0 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, - Help "Enables UART hardware flow control, CTS and RTS lines." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, - Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, - Help "Enable/disable ISH Controller." - Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, - Help "Enable/disable to show SPI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS, - Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post." - Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, - Help "Enable/disable SATA Aggressive Link Power Management." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, - Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, - Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, - Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, - Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, - Help "Enable/disable to xDCI controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SsicPortEnable, "Enable XHCI SSIC Enable", &EN_DIS, - Help "Enable/disable XHCI SSIC port." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, - Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, - Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, - Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, - Help "GPIO IRQ Select. The valid value is 14 or 15." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, - Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, - Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", HEX, - Help "Enable/disable TCO IRQ" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, - Help "Number of Entries in Verb Table." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, - Help "Pointer to Array of pointers to Verb Table." - "Valid range: 0x0 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA controller." - Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, - Help "Select SATA controller working mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX, - Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX, - Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX, - Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, - Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, - Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." - "Valid range: 0x00 ~ 0x01010101010101010101" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, - Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, - Help "Enables override of recommended LTR values for xHCI" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, - Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN controller." - Combo $gPlatformFspPkgTokenSpaceGuid_DelayUsbPdoProgramming, "Delay USB PDO Programming", &EN_DIS, - Help "Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: disable, 1: enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX, - Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly." - "Valid range: 0x0 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqSupport, "Enable PCIE RP CLKREQ Support", HEX, - Help "Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqNumber, "Configure CLKREQ Number", HEX, - Help "Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClkReqSupport, "Enable CPU PCIE RP CLKREQ Support", HEX, - Help "Enable/disable CPU PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClkReqNumber, "Configure CPU PCIE CLKREQ Number", HEX, - Help "Configure CPU Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-3. One byte for each port, byte0 for port1, byte1 for port2, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortATermOvrEnable, "Enable SkyCam PortA Termination override", &EN_DIS, - Help "Enable/disable PortA Termination override." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBTermOvrEnable, "Enable SkyCam PortB Termination override", &EN_DIS, - Help "Enable/disable PortB Termination override." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCTermOvrEnable, "Enable SkyCam PortC Termination override", &EN_DIS, - Help "Enable/disable PortC Termination override." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDTermOvrEnable, "Enable SkyCam PortD Termination override", &EN_DIS, - Help "Enable/disable PortD Termination override." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortATrimEnable, "Enable SkyCam PortA Clk Trim", &EN_DIS, - Help "Enable/disable PortA Clk Trim." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBTrimEnable, "Enable SkyCam PortB Clk Trim", &EN_DIS, - Help "Enable/disable PortB Clk Trim." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCTrimEnable, "Enable SkyCam PortC Clk Trim", &EN_DIS, - Help "Enable/disable PortC Clk Trim." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDTrimEnable, "Enable SkyCam PortD Clk Trim", &EN_DIS, - Help "Enable/disable PortD Clk Trim." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleEnable, "Enable SkyCam PortA Ctle", &EN_DIS, - Help "Enable/disable PortA Ctle." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleEnable, "Enable SkyCam PortB Ctle", &EN_DIS, - Help "Enable/disable PortB Ctle." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleEnable, "Enable SkyCam PortCD Ctle", &EN_DIS, - Help "Enable/disable PortCD Ctle." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleCapValue, "Enable SkyCam PortA Ctle Cap Value", HEX, - Help "Enable/disable PortA Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleCapValue, "Enable SkyCam PortB Ctle Cap Value", HEX, - Help "Enable/disable PortB Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleCapValue, "Enable SkyCam PortCD Ctle Cap Value", HEX, - Help "Enable/disable PortCD Ctle Cap Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortACtleResValue, "Enable SkyCam PortA Ctle Res Value", HEX, - Help "Enable/disable PortA Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBCtleResValue, "Enable SkyCam PortB Ctle Res Value", HEX, - Help "Enable/disable PortB Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDCtleResValue, "Enable SkyCam PortCD Ctle Res Value", HEX, - Help "Enable/disable PortCD Ctle Res Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortAClkTrimValue, "Enable SkyCam PortA Clk Trim Value", HEX, - Help "Enable/disable PortA Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBClkTrimValue, "Enable SkyCam PortB Clk Trim Value", HEX, - Help "Enable/disable PortB Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCClkTrimValue, "Enable SkyCam PortC Clk Trim Value", HEX, - Help "Enable/disable PortC Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortDClkTrimValue, "Enable SkyCam PortD Clk Trim Value", HEX, - Help "Enable/disable PortD Clk Trim Value." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortADataTrimValue, "Enable SkyCam Port A Data Trim Value", HEX, - Help "Enable/disable Port A Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortBDataTrimValue, "Enable SkyCam Port B Data Trim Value", HEX, - Help "Enable/disable Port B Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchSkyCamPortCDDataTrimValue, "Enable SkyCam C/D Data Trim Value", HEX, - Help "Enable/disable C/D Data Trim Value." - "Valid range: 0x0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, - Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" - Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, - Help "Enable/Disable SLP_S0 with GBE Support" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, - Help "Enable DMI Power Optimizer on PCH side." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, - Help "Write or erase is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, - Help "Read is blocked by hardware." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, - Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, - Help "Enable Azalia wake-on-ring." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaIoBufferVoltage, "IO Buffer Voltage", HEX, - Help "I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", HEX, - Help "Virtual Channel Type Select: 0: VC0, 1: VC1." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", HEX, - Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", HEX, - Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", HEX, - Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, - Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." - Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, - Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicBdfValid, "Enable PCH Io Apic", &EN_DIS, - Help "Set to 1 if BDF value is valid." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicBusNumber, "PCH Io Apic Bus Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicDeviceNumber, "PCH Io Apic Device Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicFunctionNumber, "PCH Io Apic Function Number", HEX, - Help "Bus/Device/Function used as Requestor / Completer ID. Default is 0x00." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, - Help "This member determines IOAPIC ID. Default is 0x02." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, - Help "0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanK1OffEnable, "Enable PCH Lan use CLKREQ for GbE power management", &EN_DIS, - Help "0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLanClkReqSupported, "Indicate whether dedicated CLKREQ# is supported", &EN_DIS, - Help "0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchLanClkReqNumber, "CLKREQ# used by GbE", HEX, - Help "Valid if ClkReqSupported is TRUE." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, - Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownSpiEiss, "Enable LOCKDOWN SPI Eiss", &EN_DIS, - Help "Enable InSMM.STS (EISS) in SPI." - Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, - Help "This member describes whether or not the CRID feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, - Help "todo" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, - Help "Indicate whether the root port is hot plug available." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, - Help "Indicate whether the root port power manager SCI is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX, - Help "Indicate whether the extended synch is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, - Help "Indicate whether the Transmitter Half Swing is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, - Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, - Help "Indicate whether the Advanced Error Reporting is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, - Help "Indicate whether the Unsupported Request Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, - Help "Indicate whether the Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, - Help "Indicate whether the No Fatal Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, - Help "Indicate whether the Correctable Error Report is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, - Help "Indicate whether the System Error on Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, - Help "Indicate whether the System Error on Non Fatal Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, - Help "Indicate whether the System Error on Correctable Error is enabled." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, - Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDeviceResetPadActiveHigh, "PCIE RP Device Reset Pad Active High", HEX, - Help "Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, - Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, - Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; 4: Fixed Coeficients." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, - Help "Indicates the slot number for the root port. Default is the value as root port index." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, - Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDeviceResetPad, "PCIE RP Device Reset Pad", HEX, - Help "The PCH pin assigned to device PERST# signal if available, zero otherwise. See also DeviceResetPadActiveHigh." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, - Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, - Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, - Help "Latency Tolerance Reporting Mechanism." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, - Help "0: Disable; 1: Enable." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, - Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, - Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, - Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C-1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX, - Help "PCH_PCIE_EQ_PARAM. Coefficient C+1." - "Valid range: 0x00 ~ 0xFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS, - Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, - Help "This member describes whether Peer Memory Writes are enabled on the platform." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieAllowNoLtrIccPllShutdown, "PCIE Allow No Ltr Icc PLL Shutdown", &EN_DIS, - Help "Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, - Help "Compliance Test Mode shall be enabled when using Compliance Load Board." - Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, - Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, - Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmEnable, "PCH Pm Slp S0 Voltage Margining Enable", &EN_DIS, - Help "Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, - Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, - Help "Determine if enable PCIe to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, - Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, - Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, - Help "Determine if enable LAN to wake from deep Sx." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, - Help "Deep Sx Policy." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, - Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, - Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, - Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, - Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS, - Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, - Help "Enable SLP_X Stretching After SUS Well Power Up." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, - Help "Enable/Disable SLP_LAN# Low on DC Power." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, - Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, - Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, - Help "Power button native mode disable." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS, - Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, - Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." - Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, - Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, - Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchPort61hEnable, "PCH Port 61h Config Enable/Disable", &EN_DIS, - Help "Used for the emulation feature for Port61h read. The port is trapped and the SMI handler will toggle bit4 according to the handler's internal state." - Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, - Help "SATA Power Optimizer on PCH side." - Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, - Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, - Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, - Help "Enable SATA Port HotPlug." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, - Help "Enable SATA Port Interlock Sw." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, - Help "Enable SATA Port External." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, - Help "Enable the COMRESET initialization Sequence to the device." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, - Help "0: HDD; 1: SSD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, - Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, - Help "DITO multiplier. Default is 15." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, - Help "DEVSLP Idle Timeout (DITO), Default is 625." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, - Help "Support zero power ODD." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidAlternateId, "PCH Sata Rst Raid Alternate Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidAlternateId, - Help "Enable RAID Alternate ID." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS, - Help "RAID0." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS, - Help "RAID1." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS, - Help "RAID10." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS, - Help "RAID5." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS, - Help "Intel Rapid Recovery Technology." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS, - Help "OROM UI and BANNER." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX, - Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS, - Help "Indicates that the HDD password unlock in the OS is enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS, - Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS, - Help "Allow only IRRT drives to span internal and external ports." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS, - Help "RST Smart Storage caching Bit." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, - Help "Enable Intel RST for PCIe Storage remapping." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, - Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." - "Valid range: 0x00 ~ 0xFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, - Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" - "Valid range: 0x00 ~ 0xFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoGpio, "Enable Pch Serial IO GPIO", &EN_DIS, - Help "Determines if enable Serial IO GPIO." - EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cVoltage, "IO voltage for I2C controllers", HEX, - Help "Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS, - Help "Determines if enable Serial IRQ." - Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS, - Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", HEX, - Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchThermalDeviceEnable, "Enable Thermal Device", HEX, - Help "Enable Thermal Device, 0: Disabled, 1: Enabled in PCI mode, 2: Enabled in ACPI mode." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, - Help "Custimized T0Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, - Help "Custimized T1Level value." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, - Help "Custimized T2Level value." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS, - Help "This locks down SMI Enable on Alert Thermal Sensor Trip." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, - Help "Enable the thermal throttle function." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, - Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." - Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, - Help "Thermal Throttle Lock." - Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, - Help "Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, - Help "Enable/Disable PCH Cross Throttling" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, - Help "DMI Thermal Sensor Autonomous Width Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, - Help "DMT thermal sensor suggested representative values." - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", HEX, - Help "Thermal Sensor 0 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", HEX, - Help "Thermal Sensor 1 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", HEX, - Help "Thermal Sensor 2 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", HEX, - Help "Thermal Sensor 3 Target Width." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, - Help "Port 0 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, - Help "Port 0 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, - Help "Port 0 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, - Help "Port 0 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, - Help "Port 1 T1 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, - Help "Port 1 T2 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, - Help "Port 1 T3 Multipler." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, - Help "Port 1 Tdispatch." - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, - Help "Port 0 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 0 Alternate Fast Init Tdispatch." - EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, - Help "Port 1 Tinactive." - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, - Help "Port 1 Alternate Fast Init Tdispatch." - Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, - Help "Sata Thermal Throttling Suggested Setting." - Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, - Help "Enable Memory Thermal Throttling." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, - Help "Enable Memory Thermal Throttling." - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, - Help "Decides the temperature." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PchDisableComplianceMode, "Disable XHCI Compliance Mode", &EN_DIS, - Help "This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 2.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, - Help "Describe the specific over current pin number of USB 3.0 Port N." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Early8254ClockGatingEnable, "Enable 8254 Static Clock Gating in early POST time", &EN_DIS, - Help "Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this." - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS, - Help "Optane Memory" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH SATA RST CPU attached storage", &EN_DIS, - Help "RST CPU attached storage" - EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX, - Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, - Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." - Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, - Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating, "GPIO RCOMP Community Clock Gating", &EN_DIS, - Help "0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock local clock gating, default value is 1" - Combo $gPlatformFspPkgTokenSpaceGuid_HybridStorageMode, "Hybrid Storage Mode", &gPlatformFspPkgTokenSpaceGuid_HybridStorageMode, - Help "Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" - EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, - Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem, "ReservedPchPostMem", &EN_DIS, - Help "Reserved for Pch Post-Mem" - EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, - Help "BgpdtHash values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, - Help "BiosGuardAttr default values" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, - Help "BiosGuardModulePtr default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, - Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, - Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, - Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX, - Help "SgxEpoch0 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX, - Help "SgxEpoch1 default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX, - Help "SgxSinitNvsData default values" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS, - Help "Platform specific common policies that used by several silicon components. CSM status flag." - EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, - Help "The address of the table of SVID SDID to customize each SVID SDID entry." - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, - Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr." - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS, - Help "Enable: Device 7 enabled, Disable (Default): Device 7 disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, - Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS, - Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS, - Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX, - Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, - Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" - Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, - Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" - Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, - Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp" - Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS, - Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, - Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, - Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" - Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, - Help "Reserved for SA Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX, - Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX, - Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX, - Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX, - Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, - Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, - Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, - Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, - Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, - Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, - Help "Package PL3 time window range for this policy from 0 to 64ms" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, - Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" - "Valid range: 0x00 ~ 0x64" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, - Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, - Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, - Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, - Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, - Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, - Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" - "Valid range: 0x00 ~ 0x28" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, - Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, - Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, - Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" - "Valid range: 0x00 ~ 0x2" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, - Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, - Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, - Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, - Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, - Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, - Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, - Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, - Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS, - Help "@deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS, - Help "Lock or Unlock debug interface features; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, - Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, - Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, - Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX, - Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX, - Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS, - Help "Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, - Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, - Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, - Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable, 2: Auto / Silicon default" - Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, - Help "Enable or Disable T states; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, - Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, - Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, - Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, - Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS, - Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, - Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, - Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, - Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, - Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, - Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, - Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, - Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, - Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." - EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, - Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, - Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, - Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, - Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, - Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, - Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, - Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" - "Valid range: 0x00 ~ 0x5" - EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, - Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change." - "Valid range: 0x00 ~ 0x7" - Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, - Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, - Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, - Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, - Help "Max P-State Ratio, Valid Range 0 to 0x7F" - "Valid range: 0x00 ~ 0x7F" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, - Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, - Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, - Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" - "Valid range: 0x00 ~ 0x400" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, - Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, - Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, - Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, - Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xF9F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, - Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, - Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, - Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, - Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, - Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, - Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, - Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, - Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, - Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" - "Valid range: 0x00 ~ 0x3E7F83" - Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, - Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." - Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, - Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." - Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, - Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, - Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, - Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, - Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, - Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS, - Help "@deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS, - Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX, - Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" - "Valid range: 0x00 ~ 0x53" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS, - Help "Enable or Disable C3 Cstate Demotion. Disable; 1: Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS, - Help "Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0, "Ratio Limit Num Core 0", HEX, - Help "Ratio Limit Num Core0: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1, "Ratio Limit Num Core 1", HEX, - Help "Ratio Limit Num Core1: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2, "Ratio Limit Num Core 2", HEX, - Help "Ratio Limit Num Core2: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3, "Ratio Limit Core 3", HEX, - Help "Ratio Limit Num Core3: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4, "Ratio Limit Num Core 4", HEX, - Help "Ratio Limit Num Core4: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5, "Ratio Limit Num Core 5", HEX, - Help "Ratio Limit Num Core5: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6, "Ratio Limit Num Core 6", HEX, - Help "Ratio Limit Num Core6: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7, "Ratio Limit Num Core 7", HEX, - Help "Ratio Limit Num Core7: This register defines the active core ranges for each frequency point" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, - Help "Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: Disable; 1: Enable" - EditNum $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer, "ITBMT 3.0 Runtime Periodic SMM timer", HEX, - Help "Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, 6 - 32 sec, 7 - 64 sec." - "Valid range: 0x00 ~ 0x07" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, - Help "Reserved for CPU Post-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX, - Help "SgxSinitDataFromTpm default values" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" -EndPage - -Page "Memory Reference Code 1" - EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, - Help "The minimum platform memory size required to pass control into DXE" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX, - Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" - "Valid range: 0x00 ~ 0xFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, - Help "Length of SPD Data" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX, - Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX, - Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, - Help "Indicates RcompResistor settings: CML - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, - Help "RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, - Help "Indicates DqPinsInterleaved setting: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, - Help "CA Vref routing: board-dependent" - Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, - Help "The SMM Regions AB-SEG and/or H-SEG reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, - Help "Time Measure: 0(Default)=Disable, 1=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, - Help "Enables/Disable the MRC fast path thru the MRC" - Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, - Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." - Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, - Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." - Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize, - Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied" - Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, - Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" - EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, - Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" - "Valid range: 0 ~ 0xC00" - Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, - Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX, - Help "Size of IOT and MOT is in 8 MB chunks" - "Valid range: 0x00 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, - Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" - Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, - Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, - Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100" - Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, - Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." - Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, - Help "Enable/disable Rank Margin Tool." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, - Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A." - Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, - Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B." - Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, - Help "This option enables data scrambling in memory." - Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, - Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2" - Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, - Help "100MHz, 133MHz." - Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, - Help "Memory Voltage Override (Vddq). Default = no override" - Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, - Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." - Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS, - Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, - Help "CAS Latency, 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, - Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34" - "Valid range: 0x00 ~ 0x22" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, - Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, - Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15" - "Valid range: 0x00 ~ 0x0F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, - Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63" - "Valid range: 0x00 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, - Help "RAS Active Time, 0: AUTO, max: 64" - "Valid range: 0x00 ~ 0x40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, - Help "Refresh Interval, 0: AUTO, max: 65535" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, - Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023" - "Valid range: 0x00 ~ 0x3FF" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, - Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12" - "Valid range: 0x00 ~ 0x0F" - Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, - Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, - Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, - Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" - "Valid range: 0x00 ~ 0x02" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX, - Help "DllBwEn[0], for 1067 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX, - Help "DllBwEn[1], for 1333 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX, - Help "DllBwEn[2], for 1600 (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX, - Help "DllBwEn[3], for 1867 and up (0..7)" - "Valid range: 0x00 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX, - Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default" - "Valid range: 0x00 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, - Help "Margin Limit Check. Choose level of margin check" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS, - Help "Enables/Disable MRC Safe Config" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, - Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." - Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, - Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." - Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, - Help "Enables/Disable Early Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, - Help "Enables/Disable SenseAmp Offset Training" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Early ReadMPR Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, - Help "Enables/Disable Read MPR Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, - Help "Enables/Disable Receive Enable Training" - Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, - Help "Enables/Disable Jedec Write Leveling" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Write Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, - Help "Enables/Disable Early Read Time Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, - Help "Enables/Disable Dimm ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, - Help "Enables/Disable DIMM RON Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, - Help "Enables/Disable Write Drive Strength/Equalization 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, - Help "Enables/Disable Write Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, - Help "Enables/Disable Read ODT Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, - Help "Enables/Disable Read Equalization Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, - Help "Enables/Disable Read Amplifier Training" - Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Write Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, - Help "Enables/Disable Read Timing Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Write Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, - Help "Enables/Disable Read Voltage Centering 2D" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, - Help "Enables/Disable Command Voltage Centering" - Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, - Help "Enables/Disable Late Command Training" - Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, - Help "Enables/Disable Round Trip Latency Training" - Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, - Help "Enables/Disable Turn Around Timing Training" - Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, - Help "Enables/Disable Memory Test" - Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, - Help "Enables/Disable DIMM SPD Alias Test" - Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, - Help "Enables/Disable Receive Enable Centering 1D" - Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, - Help "Enables/Disable Retrain Margin Check" - Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, - Help "Enables/Disable Write Drive Strength Up/Dn independently" - Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, - Help "Enables/Disable ECC Support" - Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, - Help "Enables/Disable Memory Remap" - Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, - Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." - Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, - Help "Enables/Disable Enhanced Interleave support" - Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS, - Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed." - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, - Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, - Help "Enables/Disable Extern Therm Status" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Closed Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS, - Help "Enables/Disable Open Loop Therm Manage" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter" - Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS, - Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS, - Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS, - Help "Enables/Disable RAPL PL Lock" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 2 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS, - Help "Enables/Disable RAPL PL 1 enable" - Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, - Help "Enables/Disable SelfRefresh Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" - Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, - Help "Enables/Disable Throttler CKEMin Defeature" - Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS, - Help "Enables/Disable RH Prevention" - Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, - Help "Enables/Disable Exit On Failure (MRC)" - Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS, - Help "Enables/Disable LPDDR Thermal Sensor" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, - Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" - EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, - Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6" - "Valid range: 0x0000 ~ 0x3FFF" - Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, - Help "Base reference clock value, in Hertz(Default is 125Hz)" - Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, - Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX, - Help "Energy Scale Factor, Default is 4" - "Valid range: 0x01 ~ 0x07" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, - Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" - "Valid range: 0x00 ~ 0x7D0" - EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, - Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" - "Valid range: 0x00 ~ 0x7D0" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, - Help "Enable/Disable CMD Slew Rate Training" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, - Help "Enable/Disable CMD Drive Strength and Tx Equalization" - Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, - Help "Enable/Disable CMD Normalization" - Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, - Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" - EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX, - Help "RH Activation Probability, Probability value is 1/2^(inputvalue)" - "Valid range: 0x01 ~ 0xF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX, - Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX, - Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX, - Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x03" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX, - Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)" - "Valid range: 0x01 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX, - Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)" - "Valid range: 0x0 ~ 0x3FFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX, - Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX, - Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX, - Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)" - "Valid range: 0x0 ~ 0x3F" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX, - Help "Activate Energy Contribution, range[255;0],(172= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX, - Help "Read Energy Contribution, range[255;0],(212= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX, - Help "Write Energy Contribution, range[255;0],(221= Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, - Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX, - Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to." - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, - Help "Power budget ,range[255;0],(0= 5.3W Def)" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, - Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" - Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, - Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" - Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, - Help "Enable/disable(default) Energy Performance Gain." - Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution, - Help "Type of method used to prevent Row Hammer. Default is Hardware RHP" - Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, - Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." - Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, - Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, " TcritMax", HEX, - Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax" - "Valid range: 0x0 ~ 0x7F" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS, - Help "Disable:Comparator mode.\n Enable:Interrupt mode" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS, - Help "Disable:Active LOW.\nEnable:Active HIGH" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS, - Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS, - Help "Disable:Event output disable.\nEnable:Event output enabled" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS, - Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS, - Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS, - Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable" - EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX, - Help "Thigh = ThighMax (Default is 93)" - "Valid range: 0x0 ~ 0x80" - Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS, - Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit." - Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS, - Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh." - EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, - Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" - "Valid range: 0x0 ~ 0xFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, - Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC MOT enable", &EN_DIS, - Help "GDXC MOT enable." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS, - Help "Fivr Faults; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS, - Help "Fivr Efficiency Management; 0: Disabled; 1: Enabled." - Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, - Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" - Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, - Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." - Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, - Help "Enables/Disable LpDdrDqDqsReTraining" - EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, - Help "This option configures Post Code Output Port" - "Valid range: 0x0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, - Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" - "Valid range: 0 ~ 0x20" - EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX, - Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation." - "Valid range: 0 ~ 0x20" - Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, - Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs." - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS, - Help "Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. Disable=0, Enable(Default)=1" - Combo $gPlatformFspPkgTokenSpaceGuid_FastBootRmt, "RMT on Fast flow", &EN_DIS, - Help "Enable/Disable RMT on Fast flow. Default: Disabled" - Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS, - Help "Reserved FspmConfig CFL" - Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, - Help "Run Base Memory Test on Warm Boot" - EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX, - Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS, - Help "Enables/Disable the MRC training on warm boot" - Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, - Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" - Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, - Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)" - Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, - Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX, - Help "deprecated" - "Valid range: 0x00 ~ 0x00" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, - Help "Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; 0: Legacy; 1: Selection." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, - Help "Array used to specifies the Offset Voltage applied to the each selected Core VF Point. This voltage is specified in millivolts." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, - Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, - Help "Array for the each selected Core VF Point to display the ration." - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX, - Help "Number of supported Core Voltage & Frequency Point Offset" - "Valid range: 0x0 ~ 0xFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, - Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, - Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" - Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS, - Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, - Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, - Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, - Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, - Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, - Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, - Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, - Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, - Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, - Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings" - Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, - Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS, - Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled", HEX, - Help "the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0" - "Valid range: 0 ~ 0xF" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data" - Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS, - Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, - Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX, - Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX, - Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 1. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 10000. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX, - Help "Range: 0-65535, default is 2. @warning Do not change from the default" - "Valid range: 0 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, - Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" - Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, - Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." - Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX, - Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX, - Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX, - Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX, - Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX, - Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86." - "Valid range: 0x00 ~ 0x56" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX, - Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX, - Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX, - Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX, - Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX, - Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX, - Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX, - Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX, - Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX, - Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX, - Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX, - Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54." - "Valid range: 0x00 ~ 0x36" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, - Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, - Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31" - "Valid range: 0x00 ~ 0x1F" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, - Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60" - "Valid range: 0x00 ~ 0x3C" - EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, - Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28" - "Valid range: 0x00 ~ 0x1C" - Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" -EndPage - -Page "PCH 1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, - Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, - Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, - Help "Select SerialIo Uart Controller mode" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC, - Help "Set default BaudRate Supported from 0 - default to 6000000" - "Valid range: 0 ~ 6000000" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, - Help "Set default Parity." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX, - Help "Set default word length. 0: Default, 5,6,7,8" - "Valid range: 0x0 ~ 0x08" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, - Help "Set default stop bits." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, - Help "Enables UART hardware flow control, CTS and RTS lines." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, "PcdSerialIoUartPinMux - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, - Help "Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, - Help "Enable to initialize LPC Uart device in FSP." - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, - Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." - "Valid range: 0x00 ~ 0x3F" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, - Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, - Help "Select ISA Serial Base address. Default is 0x3F8." - EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, - Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable" - "Valid range: 0x00 ~ 0xFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS, - Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once." - Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, - Help "Reserved for SA Pre-Mem Test" -EndPage - -Page "PCH 2" - EditNum $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX, - Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge" - "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" - Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, - Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." - Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, - Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" - Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &EN_DIS, - Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): Enable EOP message" - Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, - Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" -EndPage - diff --git a/CometLakeFspBinPkg/CometLakeV/Fsp.fd b/CometLakeFspBinPkg/CometLakeV/Fsp.fd deleted file mode 100644 index 1a0d540bba308ddd4349ef077a6263cfa6c30fc9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 815104 zcmeEtc|4R~`|ykz45r4GJ(LkeS(8GRtYy!>D~6;LhLEj6#%&^LUrDl+Hfyr4C41IL zl1A1dJM*4<===RX-{156p7(i|&*%N)J(~O6_c_;foohSSxz4%o5Qu*)=f1|rtHlYK z+}ulcjjr0=j?h5S0i1QM^l58ogg!z!-35VQP=s6A>0R^-?Qdl^YZ@VqKrF0DI0y<& zmzX?#swlYU<}O}t01bndYDip;+ODWqbT;al#9npm#VjP^4uFqBAoz8Un(FJ*scu7? z$|70thl~tC8-AUaFEkVaC7aBMK-^&cbA0%&8~Nw+5V!|8I)DcR5@DiaWNK~#cf;dz zBalc_SptlNOS4c27c^o4 z4fxYWBRH+>43Q|d4CDa@1VR-23TZ<$8216-3s#FLsD(hi$KU;&Kd8qx;1EEaF#KPO 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z$kkv{#A(aT!c{^EMQ3nLxA6Jh)bcgVrLcAjwcC4B%_;y4!$ z2(RV%K4nxP@WeUu_IddD3Mq&v6Ct| z;NtupBwbKh&*L?9*ls$AyZ=mst~WMz07ux7j*ktFI!{H0cQl7+czwv7S8L7^-!#?#RQaa* zF?`};(k?kHOegT8)9qc{T`Ig)<2ZwQkc$PR04#tdfYpFuKP`tp06;m^pN9FE| z%>r}*^k|O-(BXYG;03@|KnI|Q^1yi)um!KG1AXVAd#)N#UQA6#hv`;h&Tg{z*yUpOh5-NlD?Klob9+ zN#UQA6#hv`6{FyK;1jFiI{N@;0kkU}^!Z816MrK;Id7_AX6jtS?1~j4HFCMuWy?yd zs<^_Xl@%*09y8=uJYKPCZG~ah%BNQ^M|+??t#oCnSZc^vx?-iZvh+rMVdaY9)kF9* ztYu}Tm4>`ks|>kMEM2*h#tP8N6_>6oHKZwjFrBq(X^A1dvT{`=K1Z%tvvlQ(5`$%F z<6K2;H^A+5Axg};r)SiP#Es+4Fvv2^unh#J0W1x8wB z#VEf1RpL@*o~bJD{NOH547hI{s>q- z?NKTCH)6+h|gG4oH>5VLqADKOr0?^Ej3d$D`(a^ULN}&A&JQ#oTRvGJaG1miXQA8B-pa zk~d}kl%GGe^P#qf?)-^4Au(Y_LT19o1Y5#O30o50PH0K^OTxv3-h`UO*2MjZs;MDU zM@)^Hde7ARran9Mxv9UHdVK1#WH%X*9{W6!YjIk0j`>&S@c8@VH^zS%?}=AUaXxhT zq47!Pq|~I}CH-g8`$=s{@yR90KsI3CL1H(bHD53rrzTHrN$#GenZ9NEd(%Idp7wCg z!@qs_wTFR#4I>K4F;ivSnz(1;HpD#}_gtJk?)f-Wrr__-kyM*%P4%XqnO-oxX!?!m z71L(Z8>TI$w@h12@0xa+KER(??=`iWJ~nljJ~4HgzA$x}&X{CVx2eZ;#nfjSFmZ93 zIBlFRP9GN$7fE#ezc;UbuzH)fbJn)EFMMTre!{tThW-B<^fzPl=VAfe@1626AbJPm z3$rNItF%-eO|NW;0Fo(Ab}qw@Ph -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# @par Specification -## - - ## Specifies the AP target C-state for Mwait during POST phase. - # The default value 0 means C1 state. - # The value is defined as below.

- # @Prompt The specified AP target C-state for Mwait. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 20 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress | 0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength | 0x10000000 - - ## Specifies the base address of the first microcode Patch in the microcode Region. - # @Prompt Microcode Region base address. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FirmwareVersionInfoHob.h b/CometLakeFspBinPkg/CometLakeV/Include/FirmwareVersionInfoHob.h deleted file mode 100644 index 4d72102..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Header file for Firmware Version Information - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FspInfoHob.h b/CometLakeFspBinPkg/CometLakeV/Include/FspInfoHob.h deleted file mode 100644 index 34283b8..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FspInfoHob.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @file - Header file for FSP Information HOB. - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _FSP_INFO_HOB_H_ -#define _FSP_INFO_HOB_H_ - -extern EFI_GUID gFspInfoGuid; - -#pragma pack (push, 1) - -typedef struct { -UINT8 SiliconInitVersionMajor; -UINT8 SiliconInitVersionMinor; -UINT8 SiliconInitVersionRevision; -UINT8 SiliconInitVersionBuild; -UINT8 FspVersionRevision; -UINT8 FspVersionBuild; -UINT8 TimeStamp [12]; -UINT8 FspVersionMinor; -} FSP_INFO_HOB; - -#pragma pack (pop) - -#endif // _FSP_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FspUpd.h b/CometLakeFspBinPkg/CometLakeV/Include/FspUpd.h deleted file mode 100644 index 395a7a1..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FspUpd.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */ - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FspmUpd.h b/CometLakeFspBinPkg/CometLakeV/Include/FspmUpd.h deleted file mode 100644 index 335352b..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FspmUpd.h +++ /dev/null @@ -1,3002 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResistor settings - Indicates RcompResistor settings: CML - 0's means MRC auto configured based on - Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to - provide the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0096 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0097 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0098 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A4 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A6 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A7 - GDXC IOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcIotSize; - -/** Offset 0x00A8 - GDXC MOT SIZE - Size of IOT and MOT is in 8 MB chunks -**/ - UINT8 GdxcMotSize; - -/** Offset 0x00A9 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AD - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00AE - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00AF - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00B0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00B1 - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00B2 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00B4 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00B6 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00B7 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00B8 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00B9 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00BA - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00BB - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00BC - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00C0 - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00C1 - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00C2 - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00C3 - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00C4 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C5 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C6 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C8 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00CA - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00CC - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00CE - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CF - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00D0 - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00D1 - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00D2 - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00D3 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00D4 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D5 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D6 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D7 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00D8 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00DA - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00DB - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00DC - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00DD - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00DE - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00DF - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00E0 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x00E4 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x00E8 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x00EC - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x00EE - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x00F0 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x00F3 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x00F4 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x00F5 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x00F6 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x00F7 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x00F8 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x00F9 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x00FA - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x00FB - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x00FC - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x00FD - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x00FE - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x00FF - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0100 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0101 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0102 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0105 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x010D - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0115 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0122 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0130 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0134 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0154 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0155 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0156 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0158 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x015C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0160 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01C1 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01C2 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01C3 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01C4 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01C5 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x01C6 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01CA - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01CC - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01CF - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01D0 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01D1 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01D2 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01D3 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01D4 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01DA - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01DB - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[1]; - -/** Offset 0x01DC - Per-core HT Disable - Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, - 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value - of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have - HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1. -**/ - UINT16 PerCoreHtDisable; - -/** Offset 0x01DE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01E0 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01E1 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x01E2 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x01E3 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x01E4 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x01E5 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x01E6 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x01E7 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01E8 - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x01E9 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01EA - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01EC - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01ED - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01EE - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x01EF - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x01F0 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x01F1 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x01F2 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x01F4 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x01F6 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x01F8 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x01F9 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x01FA - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x01FC - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x01FE - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0200 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0201 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0202 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0203 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0204 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0205 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0208 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x020C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0210 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0214 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0218 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0220 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0224 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0228 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x022C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0230 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0238 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0240 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0241 - Intel Speed Optimizer Enable - When enabled this feature automatically overclocks your processor. It changes the - All Core Frequency along with PL1, PL2, and IccMax. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AutoEasyOverclock; - -/** Offset 0x0242 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[2]; - -/** Offset 0x0244 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0250 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x0251 - Platform Debug Consent - If 'Enabled' is selected, it is taken as user has 'opt-in' for debug. Default value - of other debug-related BIOS options/policies may change. Note: This policy does - not reflect the current platform debug status - 0:Disabled, 1:Enable -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x0252 - PCH HPET Enabled - Enable/disable PCH HPET. - $EN_DIS -**/ - UINT8 PchHpetEnable; - -/** Offset 0x0253 - PCH HPET BDF valid - Whether the BDF value is valid. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchHpetBdfValid; - -/** Offset 0x0254 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0255 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0256 - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0257 -**/ - UINT8 UnusedUpdSpace5; - -/** Offset 0x0258 - The HPET Base Address - The HPET base address. Default is 0xFED00000. -**/ - UINT32 PchHpetBase; - -/** Offset 0x025C - PCH HPET Bus Number - Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchHpetBusNumber; - -/** Offset 0x025D - PCH HPET Device Number - Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchHpetDeviceNumber; - -/** Offset 0x025E - PCH HPET Function Number - Function Number HPETn used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchHpetFunctionNumber; - -/** Offset 0x025F - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0277 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x028F - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02A7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02BF - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02D7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x02EF - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0307 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x031F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0337 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x034F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0367 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x037F - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03AF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03B7 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03BF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03C7 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03CF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03D7 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03DF - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03E7 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x03EF - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x03F7 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x03FF - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0407 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x040F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0417 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x041F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0427 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x042F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0437 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x043F - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0440 - PCH Acpi Base - Power management I/O base address. Default is 0x1800. -**/ - UINT16 PchAcpiBase; - -/** Offset 0x0442 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x0443 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x0444 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0446 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x0447 -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x0448 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x044C - Trace Hub Memory Region 0 - Trace Hub Memory Region 0. -**/ - UINT32 TraceHubMemReg0Size; - -/** Offset 0x0450 - Trace Hub Memory Region 1 - Trace Hub Memory Region 1. -**/ - UINT32 TraceHubMemReg1Size; - -/** Offset 0x0454 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0458 - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x0459 - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x045A - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x045B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x045C - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0460 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0461 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0462 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0463 - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0464 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[16]; - -/** Offset 0x0474 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0475 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0476 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0477 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0478 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0479 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x047A - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x047B - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x047C - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x047D - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x047E - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x047F - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0480 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0481 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0482 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0483 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0484 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0485 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0486 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x0487 - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x0488 - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x0489 - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x048A - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x048B - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x048C - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x048D - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x048E - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x048F - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0490 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0491 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0492 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0493 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0494 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0495 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0496 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x0497 - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x0498 - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x0499 - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x049A - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x049B - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x049C - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x049D - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x049E - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x049F - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x04A0 - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x04A1 - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x04A2 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x04A3 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x04A4 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x04A5 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x04A6 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x04A7 - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x04A8 - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x04A9 - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x04AA - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x04AB - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x04AC - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04AD - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04AE - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04AF - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04B0 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04B1 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04B2 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04B4 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04B8 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04B9 - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04BA - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04BC - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04BE - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04BF - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04C0 - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04C1 - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04C2 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04C3 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04C4 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04C5 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04C6 - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04C7 -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x04C8 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04CA - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04CC - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04CD - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04CE - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04CF - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04D0 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04D1 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04D2 - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04D3 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04D4 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04D5 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04D6 - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04D7 - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04D8 - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04D9 - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04DA - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04DB - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04DC - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04DD - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04DE - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04DF - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04E0 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04E1 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04E2 - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04E3 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04E4 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04E5 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04E6 - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04E7 - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04E8 - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04E9 - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04EA - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04EB - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04EC - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04ED - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04EE - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04EF - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04F0 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04F1 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04F2 - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04F3 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04F4 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04F5 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04F6 - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04F7 - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04F8 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04F9 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04FA - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04FB - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04FC - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04FD - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04FE - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04FF - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x0500 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x0501 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x0502 - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x0503 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x0504 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x0505 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x0506 - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x0507 - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x0508 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x0509 - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x050A - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x050B - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x050C - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x050D - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x050E - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x0510 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0511 - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x0512 - Dual Dimm Per-Channel Board Type - Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used - to limit maximum frequency for some SKUs. - 0:1DPC, 1:2DPC -**/ - UINT8 DualDimmPerChannelBoardType; - -/** Offset 0x0513 - DDR4 Mixed U-DIMM 2DPC Limitation - Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. - Disable=0, Enable(Default)=1 - $EN_DIS -**/ - UINT8 Ddr4Mixed2DpcLimit; - -/** Offset 0x0514 - RMT on Fast flow - Enable/Disable RMT on Fast flow. Default: Disabled - $EN_DIS -**/ - UINT8 FastBootRmt; - -/** Offset 0x0515 - CFL Reserved - Reserved FspmConfig CFL - $EN_DIS -**/ - UINT8 ReservedFspmUpdCfl; - -/** Offset 0x0516 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x0517 - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x0518 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x0519 - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x051A - Lpddr Dram Odt - Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO) - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 LpddrDramOdt; - -/** Offset 0x051B - DDR4 Skip Refresh Enable - Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled) - 0:Disable, 1:Enable -**/ - UINT8 Ddr4SkipRefreshEn; - -/** Offset 0x051C - SerialDebugMrcLevel - MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose -**/ - UINT8 SerialDebugMrcLevel; - -/** Offset 0x051D - Enable HD Audio Sndw Link IO Control - deprecated -**/ - UINT8 PchHdaSndwLinkIoControlEnabled[4]; - -/** Offset 0x0521 - Core VF Point Offset Mode - Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; - 0: Legacy; 1: Selection. - 0:Legacy, 1:Selection -**/ - UINT8 CoreVfPointOffsetMode; - -/** Offset 0x0522 - Core VF Point Offset - Array used to specifies the Offset Voltage applied to the each selected Core VF - Point. This voltage is specified in millivolts. -**/ - UINT16 CoreVfPointOffset[15]; - -/** Offset 0x0540 - Core VF Point Offset Prefix - Sets the CoreVfPointOffset value as positive or negative for corresponding core - VF Point; 0: Positive ; 1: Negative. - 0:Positive, 1:Negative -**/ - UINT8 CoreVfPointOffsetPrefix[15]; - -/** Offset 0x054F - Core VF Point Ratio - Array for the each selected Core VF Point to display the ration. -**/ - UINT8 CoreVfPointRatio[15]; - -/** Offset 0x055E - Core VF Point Count - Number of supported Core Voltage & Frequency Point Offset -**/ - UINT8 CoreVfPointCount; - -/** Offset 0x055F -**/ - UINT8 ReservedFspmUpd[1]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0560 -**/ - UINT32 Signature; - -/** Offset 0x0564 - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x0565 - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0566 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0567 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0568 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0569 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x056A - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x056B - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x056C - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x056D - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x056E - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x056F - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0570 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0571 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x0572 - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x0573 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x0574 - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x0575 - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x0576 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x0577 - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0578 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0579 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x057A - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x057B - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x057C - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x057D - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0591 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x05A5 - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x05B9 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x05BA - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x05BC - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x05BE - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x05C0 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x05C2 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x05C3 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x05C4 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x05C5 -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x05C6 - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x05C8 - Oem T12 Dealy Override - Oem T12 Dealy Override. 0(Default)=Disable 1=Enable - $EN_DIS -**/ - UINT8 OemT12DelayOverride; - -/** Offset 0x05C9 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x05D2 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x05D4 - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x05D6 - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x05D7 - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x05DA - PCH Dci Enable - Enable/disable PCH Dci. - $EN_DIS -**/ - UINT8 PchDciEn; - -/** Offset 0x05DB - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x05DC - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x05DD - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x05DE - ChipsetInit HECI message - Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. - If disabled, it prevents from sending ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x05DF - Bypass ChipsetInit sync reset. - 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x05E0 - ReservedPchPreMemTest - Reserved for Pch Pre-Mem Test - $EN_DIS -**/ - UINT8 ReservedPchPreMemTest[16]; - -/** Offset 0x05F0 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x05F1 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x05F2 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05F3 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05F4 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05F5 - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05F6 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05F7 - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05F8 - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05F9 - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05FA - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05FB - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05FC - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05FD - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05FE - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05FF - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x0600 - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x0601 - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x0602 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x0603 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x0604 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x0605 - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x0606 - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x0607 - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x0608 - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x0609 - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x060A - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x060B - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x060C -**/ - UINT8 UnusedUpdSpace11[1]; - -/** Offset 0x060D -**/ - UINT8 ReservedFspmTestUpd[7]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0560 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0614 -**/ - UINT8 UnusedUpdSpace12[2]; - -/** Offset 0x0616 -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FspsUpd.h b/CometLakeFspBinPkg/CometLakeV/Include/FspsUpd.h deleted file mode 100644 index 5a072f6..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FspsUpd.h +++ /dev/null @@ -1,3397 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0030 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0034 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0038 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0039 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x003A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x003B - HECI1 state - Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 Heci1Disabled; - -/** Offset 0x003C - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x003D - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 WatchDogEnabled; - -/** Offset 0x003E - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x003F - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x0040 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. - Setting is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x0041 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0042 - OS Timer - 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x0044 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x0046 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0047 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0048 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0049 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x004A - DMI ASPM - 0=Disable, 2(Default)=L1 - 0:Disable, 2:L1 -**/ - UINT8 DmiAspm; - -/** Offset 0x004B - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x004F - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x0053 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0058 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0060 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - CdClock Frequency selection - 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz - 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0063 - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x0065 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x0068 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0074 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0075 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0076 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0077 - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x0078 - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x0079 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x007A - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x007B - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x007C - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x007D - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0080 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0084 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0088 - Program GT Chicken bits - Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] -**/ - UINT8 ProgramGtChickenBits; - -/** Offset 0x0089 - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[34]; - -/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x00C4 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x00C9 - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x00CE - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x00D3 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x00DD - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x00E2 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x00E7 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x00EC - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x00ED - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x00EE - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x00F3 -**/ - UINT8 UnusedUpdSpace4[1]; - -/** Offset 0x00F4 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x00FE - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x0108 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x0112 - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x011C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0126 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0130 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x013A - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0146 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0147 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0148 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x014A - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x014B - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x014C - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x014E - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x014F - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0152 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x0159 -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x015A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0164 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0168 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0169 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x016A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x016B -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x016C - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x0170 - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0174 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace8[1]; - -/** Offset 0x0176 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x0180 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0188 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x0189 - Select HDAudio IoBuffer Ownership - Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / - I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link - owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 - of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports - own all the I/O buffers. - 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports -**/ - UINT8 PchHdaIoBufferOwnership; - -/** Offset 0x018A - Configure CLKSRC Number - Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid - clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for - port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkSrcNumber[24]; - -/** Offset 0x01A2 - Force Disable clock - Disables clock even if link is inactive default value is 0 -**/ - UINT8 PcieRpForceClkDisableWhenRpDisable[24]; - -/** Offset 0x01BA - Enable CIO2 Controller - Enable/disable SKYCAM CIO2 Controller. - $EN_DIS -**/ - UINT8 PchCio2Enable; - -/** Offset 0x01BB - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x01BD - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x01BF - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x01C1 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x01C3 - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[2]; - -/** Offset 0x01C5 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[2]; - -/** Offset 0x01C7 - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x01CD - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x01CE - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x01D1 -**/ - UINT8 UnusedUpdSpace9[3]; - -/** Offset 0x01D4 - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x01E0 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x01E3 - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x01E6 - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x01E9 - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x01EC - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x01EF - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x01F2 - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x01F5 - Enable PCH ISH Controller - Enable/disable ISH Controller. - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x01F6 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x01F7 - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x01F8 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x01F9 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x0201 - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0209 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0219 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x0223 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0224 - Enable XHCI SSIC Enable - Enable/disable XHCI SSIC port. - $EN_DIS -**/ - UINT8 SsicPortEnable; - -/** Offset 0x0225 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0226 -**/ - UINT8 UnusedUpdSpace10[2]; - -/** Offset 0x0228 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x022C - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0234 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0235 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0236 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x0237 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x0238 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0239 -**/ - UINT8 UnusedUpdSpace11[3]; - -/** Offset 0x023C - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x0240 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x0241 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0242 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x0252 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x0262 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x0272 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x0282 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x028C - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x0296 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x02A0 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x02AA - Enable xHCI LTR override - Enables override of recommended LTR values for xHCI - $EN_DIS -**/ - UINT8 PchUsbLtrOverrideEnable; - -/** Offset 0x02AB -**/ - UINT8 UnusedUpdSpace12; - -/** Offset 0x02AC - xHCI High Idle Time LTR override - Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting -**/ - UINT32 PchUsbLtrHighIdleTimeOverride; - -/** Offset 0x02B0 - xHCI Medium Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting -**/ - UINT32 PchUsbLtrMediumIdleTimeOverride; - -/** Offset 0x02B4 - xHCI Low Idle Time LTR override - Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting -**/ - UINT32 PchUsbLtrLowIdleTimeOverride; - -/** Offset 0x02B8 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x02B9 - Delay USB PDO Programming - Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: - disable, 1: enable - $EN_DIS -**/ - UINT8 DelayUsbPdoProgramming; - -/** Offset 0x02BA -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x02BC - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x02C0 - Enable PCIE RP CLKREQ Support - Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for - each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqSupport[24]; - -/** Offset 0x02D8 - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can - be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqNumber[24]; - -/** Offset 0x02F0 - Enable CPU PCIE RP CLKREQ Support - Enable/disable CPU PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte - for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 CpuPcieRpClkReqSupport[4]; - -/** Offset 0x02F4 - Configure CPU PCIE CLKREQ Number - Configure CPU Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary - can be between 0-3. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 CpuPcieRpClkReqNumber[4]; - -/** Offset 0x02F8 - Enable SkyCam PortA Termination override - Enable/disable PortA Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortATermOvrEnable; - -/** Offset 0x02F9 - Enable SkyCam PortB Termination override - Enable/disable PortB Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortBTermOvrEnable; - -/** Offset 0x02FA - Enable SkyCam PortC Termination override - Enable/disable PortC Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortCTermOvrEnable; - -/** Offset 0x02FB - Enable SkyCam PortD Termination override - Enable/disable PortD Termination override. - $EN_DIS -**/ - UINT8 PchSkyCamPortDTermOvrEnable; - -/** Offset 0x02FC - Enable SkyCam PortA Clk Trim - Enable/disable PortA Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortATrimEnable; - -/** Offset 0x02FD - Enable SkyCam PortB Clk Trim - Enable/disable PortB Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortBTrimEnable; - -/** Offset 0x02FE - Enable SkyCam PortC Clk Trim - Enable/disable PortC Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortCTrimEnable; - -/** Offset 0x02FF - Enable SkyCam PortD Clk Trim - Enable/disable PortD Clk Trim. - $EN_DIS -**/ - UINT8 PchSkyCamPortDTrimEnable; - -/** Offset 0x0300 - Enable SkyCam PortA Ctle - Enable/disable PortA Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortACtleEnable; - -/** Offset 0x0301 - Enable SkyCam PortB Ctle - Enable/disable PortB Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortBCtleEnable; - -/** Offset 0x0302 - Enable SkyCam PortCD Ctle - Enable/disable PortCD Ctle. - $EN_DIS -**/ - UINT8 PchSkyCamPortCDCtleEnable; - -/** Offset 0x0303 - Enable SkyCam PortA Ctle Cap Value - Enable/disable PortA Ctle Cap Value. -**/ - UINT8 PchSkyCamPortACtleCapValue; - -/** Offset 0x0304 - Enable SkyCam PortB Ctle Cap Value - Enable/disable PortB Ctle Cap Value. -**/ - UINT8 PchSkyCamPortBCtleCapValue; - -/** Offset 0x0305 - Enable SkyCam PortCD Ctle Cap Value - Enable/disable PortCD Ctle Cap Value. -**/ - UINT8 PchSkyCamPortCDCtleCapValue; - -/** Offset 0x0306 - Enable SkyCam PortA Ctle Res Value - Enable/disable PortA Ctle Res Value. -**/ - UINT8 PchSkyCamPortACtleResValue; - -/** Offset 0x0307 - Enable SkyCam PortB Ctle Res Value - Enable/disable PortB Ctle Res Value. -**/ - UINT8 PchSkyCamPortBCtleResValue; - -/** Offset 0x0308 - Enable SkyCam PortCD Ctle Res Value - Enable/disable PortCD Ctle Res Value. -**/ - UINT8 PchSkyCamPortCDCtleResValue; - -/** Offset 0x0309 - Enable SkyCam PortA Clk Trim Value - Enable/disable PortA Clk Trim Value. -**/ - UINT8 PchSkyCamPortAClkTrimValue; - -/** Offset 0x030A - Enable SkyCam PortB Clk Trim Value - Enable/disable PortB Clk Trim Value. -**/ - UINT8 PchSkyCamPortBClkTrimValue; - -/** Offset 0x030B - Enable SkyCam PortC Clk Trim Value - Enable/disable PortC Clk Trim Value. -**/ - UINT8 PchSkyCamPortCClkTrimValue; - -/** Offset 0x030C - Enable SkyCam PortD Clk Trim Value - Enable/disable PortD Clk Trim Value. -**/ - UINT8 PchSkyCamPortDClkTrimValue; - -/** Offset 0x030D -**/ - UINT8 UnusedUpdSpace14; - -/** Offset 0x030E - Enable SkyCam Port A Data Trim Value - Enable/disable Port A Data Trim Value. -**/ - UINT16 PchSkyCamPortADataTrimValue; - -/** Offset 0x0310 - Enable SkyCam Port B Data Trim Value - Enable/disable Port B Data Trim Value. -**/ - UINT16 PchSkyCamPortBDataTrimValue; - -/** Offset 0x0312 - Enable SkyCam C/D Data Trim Value - Enable/disable C/D Data Trim Value. -**/ - UINT16 PchSkyCamPortCDDataTrimValue; - -/** Offset 0x0314 - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x0315 - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support - 0: Disable, 1: Enable -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x0316 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0317 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x031C - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x0321 -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x0322 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x032C - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0336 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0337 - IO Buffer Voltage - I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V. -**/ - UINT8 PchHdaIoBufferVoltage; - -/** Offset 0x0338 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0339 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz. -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x033A - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x033B - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x033D - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x033E - Enable PCH Io Apic - Set to 1 if BDF value is valid. - $EN_DIS -**/ - UINT8 PchIoApicBdfValid; - -/** Offset 0x033F - PCH Io Apic Bus Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchIoApicBusNumber; - -/** Offset 0x0340 - PCH Io Apic Device Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchIoApicDeviceNumber; - -/** Offset 0x0341 - PCH Io Apic Function Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchIoApicFunctionNumber; - -/** Offset 0x0342 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x0343 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x0344 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x0345 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x0346 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x0347 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x0348 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x0349 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x034A - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x034B - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x034C - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x034D - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x034E - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x034F - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x0350 - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x0351 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x0352 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x0353 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x0354 - Enable PCH Lan use CLKREQ for GbE power management - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanK1OffEnable; - -/** Offset 0x0355 - Indicate whether dedicated CLKREQ# is supported - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanClkReqSupported; - -/** Offset 0x0356 - CLKREQ# used by GbE - Valid if ClkReqSupported is TRUE. -**/ - UINT8 PchLanClkReqNumber; - -/** Offset 0x0357 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x0358 - Enable LOCKDOWN SPI Eiss - Enable InSMM.STS (EISS) in SPI. - $EN_DIS -**/ - UINT8 PchLockDownSpiEiss; - -/** Offset 0x0359 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x035A - PCH Legacy IO Low Latency Enable - todo - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x035B - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x0373 - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x038B - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03A3 - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x03BB - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x03D3 - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x03EB - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x0403 - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x041B - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x0433 - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x044B - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x0463 - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x047B - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x0493 - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x04AB - PCIE RP Device Reset Pad Active High - Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad. -**/ - UINT8 PcieRpDeviceResetPadActiveHigh[24]; - -/** Offset 0x04C3 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x04DB - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; - 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x04F3 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x050B - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x0523 -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x0524 - PCIE RP Device Reset Pad - The PCH pin assigned to device PERST# signal if available, zero otherwise. See - also DeviceResetPadActiveHigh. -**/ - UINT32 PcieRpDeviceResetPad[24]; - -/** Offset 0x0584 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x059C - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05B4 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05CC - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x05E4 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x05FC - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x0614 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x062C - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x065C - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x0661 - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0666 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0667 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0668 - PCIE Allow No Ltr Icc PLL Shutdown - Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable - or leaving untouched. - $EN_DIS -**/ - UINT8 PcieAllowNoLtrIccPllShutdown; - -/** Offset 0x0669 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x066A - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x066B - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x066C - PCH Pm Slp S0 Voltage Margining Enable - Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. - $EN_DIS -**/ - UINT8 PchPmSlpS0VmEnable; - -/** Offset 0x066D - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x066E - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x066F - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0670 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0671 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0672 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0673 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0674 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0675 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0676 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x0677 - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x0678 - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x0679 - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x067A - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x067B - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x067C - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x067D - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x067E - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x067F - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0680 - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0681 - PCH Port 61h Config Enable/Disable - Used for the emulation feature for Port61h read. The port is trapped and the SMI - handler will toggle bit4 according to the handler's internal state. - $EN_DIS -**/ - UINT8 PchPort61hEnable; - -/** Offset 0x0682 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0683 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x0684 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0685 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x068D - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x0695 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x069D - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x06A5 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x06AD - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x06B5 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x06BD -**/ - UINT8 UnusedUpdSpace17[1]; - -/** Offset 0x06BE - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x06CE - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x06D6 - PCH Sata Rst Raid Alternate Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidAlternateId; - -/** Offset 0x06D7 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x06D8 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x06D9 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x06DA - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x06DB - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x06DC - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x06DD - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x06DE - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x06DF - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x06E0 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x06E1 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x06E2 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x06E5 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x06E8 - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x06EB - Enable Pch Serial IO GPIO - Determines if enable Serial IO GPIO. - $EN_DIS -**/ - UINT8 SerialIoGpio; - -/** Offset 0x06EC - IO voltage for I2C controllers - Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. -**/ - UINT8 SerialIoI2cVoltage[6]; - -/** Offset 0x06F2 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x06F3 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x06F4 - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x06F5 - Enable Thermal Device - Enable Thermal Device, 0: Disabled, 1: Enabled in PCI mode, 2: Enabled in ACPI mode. -**/ - UINT8 PchThermalDeviceEnable; - -/** Offset 0x06F6 - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x06F8 - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x06FA - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x06FC - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x06FD - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x06FE - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x06FF - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x0700 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x0701 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x0702 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x0703 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x0704 - Thermal Sensor 0 Target Width - Thermal Sensor 0 Target Width. -**/ - UINT8 DmiTS0TW; - -/** Offset 0x0705 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. -**/ - UINT8 DmiTS1TW; - -/** Offset 0x0706 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. -**/ - UINT8 DmiTS2TW; - -/** Offset 0x0707 - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. -**/ - UINT8 DmiTS3TW; - -/** Offset 0x0708 - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x0709 - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x070A - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x070B - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x070C - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x070D - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x070E - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x070F - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x0710 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x0711 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x0712 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x0713 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x0714 - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x0715 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x0716 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x0718 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x071A - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x071C - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x071E - Disable XHCI Compliance Mode - This policy will disable XHCI compliance mode on all ports. Complicance Mode should - be default enabled. - $EN_DIS -**/ - UINT8 PchDisableComplianceMode; - -/** Offset 0x071F - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x072F - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x0739 - Enable 8254 Static Clock Gating in early POST time - Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might - fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy - OS boot before enabling this. - $EN_DIS -**/ - UINT8 Early8254ClockGatingEnable; - -/** Offset 0x073A - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x073B - PCH SATA RST CPU attached storage - RST CPU attached storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x073C - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x0740 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0741 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x0742 - GPIO RCOMP Community Clock Gating - 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock - local clock gating, default value is 1 - $EN_DIS -**/ - UINT8 GpioPmRcompCommunityLocalClockGating; - -/** Offset 0x0743 - Hybrid Storage Mode - Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. - Default is 0: Disabled - 0: Disabled, 1: Dynamic Configuration -**/ - UINT8 HybridStorageMode; - -/** Offset 0x0744 - Set SATA DEVSLP GPIO Reset Config - Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, - 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte - for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlpResetConfig[8]; - -/** Offset 0x074C - ReservedPchPostMem - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[8]; - -/** Offset 0x0754 -**/ - UINT8 UnusedUpdSpace18[4]; - -/** Offset 0x0758 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0778 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x077C -**/ - UINT8 UnusedUpdSpace19[4]; - -/** Offset 0x0780 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0788 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x0790 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x0791 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x0792 -**/ - UINT8 UnusedUpdSpace20[6]; - -/** Offset 0x0798 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x07A0 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x07A8 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07A9 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07AA -**/ - UINT8 UnusedUpdSpace21[2]; - -/** Offset 0x07AC - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07B0 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07B2 - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07B3 - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07B4 -**/ - UINT8 UnusedUpdSpace22[3]; - -/** Offset 0x07B7 -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07B8 -**/ - UINT32 Signature; - -/** Offset 0x07BC - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07BD - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07BE - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07BF - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07C0 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07C1 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07C5 - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07C6 - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07C7 - Enable/Disable CdynmaxClamp - Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07C8 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07C9 - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07CA - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07CB - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07D6 - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07D7 - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07D8 - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07D9 - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07DA - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07DB - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07DC - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07DD - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07DE - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07DF - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07E0 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07E1 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07E2 - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07E3 - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07E4 - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07E5 - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07E6 - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07E7 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07E8 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07E9 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07EA - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07EB - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07EC - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07ED - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07EE - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07EF - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07F0 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07F1 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07F2 - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07F3 - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07F4 - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07F5 - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07F6 - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07F7 - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x07F8 - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x07F9 - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x07FA - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x07FB - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x07FC - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x07FD - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x07FE -**/ - UINT8 UnusedUpdSpace23[2]; - -/** Offset 0x0800 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0808 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x080C - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x080D - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x080E - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x080F - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable, 2: Auto / Silicon default - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0810 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0811 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x0812 - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x0813 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x0814 - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x0815 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x0816 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x0817 - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0818 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0819 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x081A - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x081B - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x081C - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x081D - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x081E - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x081F - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0820 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0821 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x0822 - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x0823 - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x0824 - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x0825 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x0826 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: - PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x0827 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0828 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x0829 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x082A - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x082B - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x0853 - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x0863 -**/ - UINT8 UnusedUpdSpace24; - -/** Offset 0x0864 - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x0866 - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x0868 - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x086A - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x086C - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0872 -**/ - UINT8 UnusedUpdSpace25[2]; - -/** Offset 0x0874 - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0878 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x087C - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0880 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x0884 - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x088C - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x089C - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x08A0 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x08A4 - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x08A8 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x08A9 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x08AA - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x08AB - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x08AC - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x08AD - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x08AE - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x08AF - Intel Turbo Boost Max Technology 3.0 Driver - @deprecated Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08B0 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08B1 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08B2 - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08B3 - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08B4 - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08B5 - Enable or Disable C3 Cstate Demotion - Enable or Disable C3 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateAutoDemotion; - -/** Offset 0x08B6 - Enable or Disable C3 Cstate UnDemotion - Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C3StateUnDemotion; - -/** Offset 0x08B7 - Ratio Limit Num Core 0 - Ratio Limit Num Core0: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore0; - -/** Offset 0x08B8 - Ratio Limit Num Core 1 - Ratio Limit Num Core1: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore1; - -/** Offset 0x08B9 - Ratio Limit Num Core 2 - Ratio Limit Num Core2: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore2; - -/** Offset 0x08BA - Ratio Limit Core 3 - Ratio Limit Num Core3: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore3; - -/** Offset 0x08BB - Ratio Limit Num Core 4 - Ratio Limit Num Core4: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore4; - -/** Offset 0x08BC - Ratio Limit Num Core 5 - Ratio Limit Num Core5: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore5; - -/** Offset 0x08BD - Ratio Limit Num Core 6 - Ratio Limit Num Core6: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore6; - -/** Offset 0x08BE - Ratio Limit Num Core 7 - Ratio Limit Num Core7: This register defines the active core ranges for each frequency point -**/ - UINT8 RatioLimitNumCore7; - -/** Offset 0x08BF - Dual Tau Boost - Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 DualTauBoost; - -/** Offset 0x08C0 - ITBMT 3.0 Runtime Periodic SMM timer - Periodic SMM Polling timer for ITBMT 3.0 Default 4 - 8 Sec. 0 = Diable periodic - SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, - 6 - 32 sec, 7 - 64 sec. -**/ - UINT8 ItbmPeriodicSmmTimer; - -/** Offset 0x08C1 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[9]; - -/** Offset 0x08CA - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08CB - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): - Enable EOP message - $EN_DIS -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08CC - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08CD - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08CE - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08D0 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08D1 - RTC CMOS RAM LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcLock; - -/** Offset 0x08D2 - PCH Sbi lock bit - This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchSbiUnlock; - -/** Offset 0x08D3 - PCH Psf lock bit - The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08D4 - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x0904 - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x0934 - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x094C - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x0964 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x09AC - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09C4 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09F4 - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x0A0C - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A3C - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A54 - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A6C - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A6D - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A6E - PCH Pm Disable Energy Report - Disable/Enable PCH to CPU enery report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A6F - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A70 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A71 - Xhci OverCurrent enable - Xhci Overcurrent enable. - $EN_DIS -**/ - UINT8 PchXhciOcEnable; - -/** Offset 0x0A72 - ReservedPchPostMemTest - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[16]; - -/** Offset 0x0A82 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A83 - Enforce Enhanced Debug Mode - Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 EnforceEDebugMode; - -/** Offset 0x0A84 - LogoPixelHeight Address - Address of LogoPixelHeight -**/ - UINT32 LogoPixelHeight; - -/** Offset 0x0A88 - LogoPixelWidth Address - Address of LogoPixelWidth -**/ - UINT32 LogoPixelWidth; - -/** Offset 0x0A8C -**/ - UINT8 ReservedFspsTestUpd[4]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07B8 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0A90 -**/ - UINT8 UnusedUpdSpace26[6]; - -/** Offset 0x0A96 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeV/Include/FsptUpd.h b/CometLakeFspBinPkg/CometLakeV/Include/FsptUpd.h deleted file mode 100644 index 9617105..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/FsptUpd.h +++ /dev/null @@ -1,180 +0,0 @@ -/** @file - -Copyright (c) 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT - Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - - F7 (PCH LP) J5 - J7 (PCH H) - 0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) -**/ - UINT8 PcdSerialIoUartPinMux; - -/** Offset 0x0059 - PcdLpcUartDebugEnable - Enable to initialize LPC Uart device in FSP. - 0:Disable, 1:Enable -**/ - UINT8 PcdLpcUartDebugEnable; - -/** Offset 0x005A - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x005B - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x005C - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x005D -**/ - UINT8 UnusedUpdSpace1[7]; - -/** Offset 0x0064 -**/ - UINT8 ReservedFsptUpd1[20]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0078 -**/ - UINT8 UnusedUpdSpace2[6]; - -/** Offset 0x007E -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/CometLakeFspBinPkg/CometLakeV/Include/GpioConfig.h b/CometLakeFspBinPkg/CometLakeV/Include/GpioConfig.h deleted file mode 100644 index eed3cb2..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/GpioConfig.h +++ /dev/null @@ -1,329 +0,0 @@ -/** @file - Header file for GpioConfig structure used by GPIO library. - -@copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _GPIO_CONFIG_H_ -#define _GPIO_CONFIG_H_ - -#pragma pack(push, 1) - -/// -/// For any GpioPad usage in code use GPIO_PAD type -/// -typedef UINT32 GPIO_PAD; - - -/// -/// For any GpioGroup usage in code use GPIO_GROUP type -/// -typedef UINT32 GPIO_GROUP; - -/** - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -**/ -typedef struct { - /** - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction (except Inversion), OutputState, - InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - **/ - UINT32 PadMode : 5; - /** - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - **/ - UINT32 HostSoftPadOwn : 2; - /** - GPIO Direction - Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - **/ - UINT32 Direction : 6; - /** - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - **/ - UINT32 OutputState : 2; - /** - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). - This setting is applicable only if GPIO is in GpioMode with input enabled. - Refer to definition of GPIO_INT_CONFIG for supported settings. - **/ - UINT32 InterruptConfig : 9; - /** - GPIO Power Configuration. - This setting controls Pad Reset Configuration. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - **/ - UINT32 PowerConfig : 8; - /** - GPIO Electrical Configuration - This setting controls pads termination. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - **/ - UINT32 ElectricalConfig : 9; - /** - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - **/ - UINT32 LockConfig : 4; - /** - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - **/ - UINT32 OtherSettings : 9; - UINT32 RsvdBits : 10; ///< Reserved bits for future extension -} GPIO_CONFIG; - - -typedef enum { - GpioHardwareDefault = 0x0 ///< Leave setting unmodified -} GPIO_HARDWARE_DEFAULT; - -/** - GPIO Pad Mode - Refer to GPIO documentation on native functions available for certain pad. - If GPIO is set to one of NativeX modes then following settings are not applicable - and can be skipped: - - Interrupt related settings - - Host Software Ownership - - Output/Input enabling/disabling - - Output lock -**/ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, - GpioPadModeNative5 = 0xB -} GPIO_PAD_MODE; - -/** - Host Software Pad Ownership modes - This setting affects GPIO interrupt status registers. Depending on chosen ownership - some GPIO Interrupt status register get updated and other masked. - Please refer to EDS for HOSTSW_OWN register description. -**/ -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - /** - Set HOST ownership to ACPI. - Use this setting if pad is not going to be used by GPIO OS driver. - If GPIO is configured to generate SCI/SMI/NMI then this setting must be - used for interrupts to work - **/ - GpioHostOwnAcpi = 0x1, - /** - Set HOST ownership to GPIO Driver mode. - Use this setting only if GPIO pad should be controlled by GPIO OS Driver. - GPIO OS Driver will be able to control the pad if appropriate entry in - ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) - **/ - GpioHostOwnGpio = 0x3 -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/** - GPIO Output State - This field is relevant only if output is enabled -**/ -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/** - GPIO interrupt configuration - This setting is applicable only if pad is in GPIO mode and has input enabled. - GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) - and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in - EDS for details on this settings. - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge - to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. - If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt. - When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this - interrupt cannot be shared and its IRQn number is not configurable. - Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) - If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor - exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). - This type of GPIO Driver interrupt doesn't have any additional routing setting - required to be set by BIOS. Interrupt is handled by GPIO OS Driver. -**/ - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source -#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type - -/** - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will - be used to reset certain GPIO settings. - Refer to EDS for settings that are controllable by PadRstCfg. -**/ -typedef enum { - GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified - /** - Resume Reset (RSMRST) - GPP: PadRstCfg = 00b = "Powergood" - GPD: PadRstCfg = 11b = "Resume Reset" - Pad setting will reset on: - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - **/ - GpioResumeReset = 0x01, - /** - Host Deep Reset - PadRstCfg = 01b = "Deep GPIO Reset" - Pad settings will reset on: - - Warm/Cold/Global reset - - DeepSx transition - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - **/ - GpioHostDeepReset = 0x03, - /** - Platform Reset (PLTRST) - PadRstCfg = 10b = "GPIO Reset" - Pad settings will reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - - G3 - **/ - GpioPlatformReset = 0x05, - /** - Deep Sleep Well Reset (DSW_PWROK) - GPP: not applicable - GPD: PadRstCfg = 00b = "Powergood" - Pad settings will reset on: - - G3 - Pad settings will not reset on: - - S3/S4/S5 transition - - Warm/Cold/Global reset - - DeepSx transition - **/ - GpioDswReset = 0x07 -} GPIO_RESET_CONFIG; - -/** - GPIO Electrical Configuration - Configuration options for GPIO termination setting -**/ -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - /** - Native function controls pads termination - This setting is applicable only to some native modes. - Please check EDS to determine which native functionality - can control pads termination - **/ - GpioTermNative = 0x1F -} GPIO_ELECTRICAL_CONFIG; - -#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value - -/** - GPIO LockConfiguration - Set GPIO configuration lock and output state lock. - GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. - By default GPIO pads will be locked unless GPIO lib is explicitly - informed that certain pad is to be left unlocked. - Lock settings reset is in Powergood domain. Care must be taken when using this setting - as fields it locks may be reset by a different signal and can be controlled - by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides - functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock - an already locked pad upon request for reconfiguration -**/ -typedef enum { - /** - Perform default action - - if pad is an GPO, lock configuration but leave output unlocked - - if pad is an GPI, lock everything - - if pad is in native, lock everything -**/ - GpioLockDefault = 0x0, - GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked - GpioPadConfigLock = 0x1, ///< Lock Pad configuration - GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked - GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked - GpioPadLock = 0x5 ///< Lock both Pad configuration and output control -} GPIO_LOCK_CONFIG; - -#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock -#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock - -/** - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This setting is applicable only if in input mode (both in GPIO and native usage). - The override takes place at the internal pad state directly from buffer and before the RXINV. -**/ -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting - -#pragma pack(pop) - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/GpioSampleDef.h b/CometLakeFspBinPkg/CometLakeV/Include/GpioSampleDef.h deleted file mode 100644 index 9cfc7c7..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/GpioSampleDef.h +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Sample enum definitions for GPIO table. - - @copyright - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include -#include -#include - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/HobUsageDataHob.h b/CometLakeFspBinPkg/CometLakeV/Include/HobUsageDataHob.h deleted file mode 100644 index 2712130..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/HobUsageDataHob.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Definitions for Hob Usage data HOB - - @copyright - Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _HOB_USAGE_DATA_HOB_H_ -#define _HOB_USAGE_DATA_HOB_H_ - -extern EFI_GUID gHobUsageDataGuid; - -#pragma pack (push, 1) - -/** - Hob Usage Data Hob - - Revision 1: - - Initial version. -**/ -typedef struct { - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - UINTN FreeMemory; -} HOB_USAGE_DATA_HOB; - -#pragma pack (pop) - -#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/MemInfoHob.h b/CometLakeFspBinPkg/CometLakeV/Include/MemInfoHob.h deleted file mode 100644 index 1c94e8e..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/MemInfoHob.h +++ /dev/null @@ -1,263 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ - -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; - -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/SmbiosCacheInfoHob.h b/CometLakeFspBinPkg/CometLakeV/Include/SmbiosCacheInfoHob.h deleted file mode 100644 index 87913d9..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/SmbiosCacheInfoHob.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @file - Header file for SMBIOS Cache Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_CACHE_INFO_HOB_H_ -#define _SMBIOS_CACHE_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Cache Info HOB Structure -/// -typedef struct { - UINT16 ProcessorSocketNumber; - UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 - UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" - UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 - UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 - UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. - UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 - UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 - UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 - // - // Add for smbios 3.1.0 - // - UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_CACHE_INFO; -#pragma pack() - -#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/Include/SmbiosProcessorInfoHob.h b/CometLakeFspBinPkg/CometLakeV/Include/SmbiosProcessorInfoHob.h deleted file mode 100644 index 1fa6795..0000000 --- a/CometLakeFspBinPkg/CometLakeV/Include/SmbiosProcessorInfoHob.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - Header file for SMBIOS Processor Info HOB - - @copyright - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - System Management BIOS (SMBIOS) Reference Specification v3.1.0 - dated 2016-Nov-16 (DSP0134) - http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf -**/ - -#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ -#define _SMBIOS_PROCESSOR_INFO_HOB_H_ - -#include -#include - -#pragma pack(1) -/// -/// SMBIOS Processor Info HOB Structure -/// -typedef struct { - UINT16 TotalNumberOfSockets; - UINT16 CurrentSocketNumber; - UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 - /** This info is used for both ProcessorFamily and ProcessorFamily2 fields - See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 - **/ - UINT16 ProcessorFamily; - UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer - UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 - UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer - UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 - UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. - UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot - UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 - UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 - /** This info is used for both CoreCount & CoreCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.6 - **/ - UINT16 CoreCount; - /** This info is used for both CoreEnabled & CoreEnabled2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.7 - **/ - UINT16 EnabledCoreCount; - /** This info is used for both ThreadCount & ThreadCount2 fields - See detailed description in SMBIOS Spec v3.1 Section 7.5.8 - **/ - UINT16 ThreadCount; - UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 - /** - String Buffer - each string terminated by NULL "0x00" - String buffer terminated by double NULL "0x0000" - **/ -} SMBIOS_PROCESSOR_INFO; -#pragma pack() - -#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/CometLakeFspBinPkg/CometLakeV/README.md b/CometLakeFspBinPkg/CometLakeV/README.md deleted file mode 100644 index 045a7ed..0000000 --- a/CometLakeFspBinPkg/CometLakeV/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# CometLakeFspBinPkg/CometLakeV -These FSP binaries are intended to be used with 10th Generation Intel® Core™ desktop processors and chipsets formerly known as Comet Lake with a 22nm Platform Controller Hub (PCH). Please consult CometLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use. diff --git a/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bin b/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bin deleted file mode 100644 index e1298a1fa0dcdca38f1f697c1f461085d7c614c1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4608 zcmeHKU2GIp6h5=FzjtP~vr{7573<+Auv=)EEwExOakjg~E?wAdw=^Z1bb%ePVWG7@ zS`4OZ(kKr~_CXCAl)ey^7xBsXhHoS$N;JVIBPJ#&zDVT7fQ)B;+DZv@B>}~7X3stM zp1J$obM8I&-ZQKEJNmHDy(^pS?nH-5pu(vTN9C>5k;xSX)5*T%U`IBW>c*eo5f~5M zxC~I@xCSw8{->WHf%(UuWzNF8s9`!wJn}#+w`Qw(w(W?_IxIr z?91eKV6GR_nL@Hq=-l3s-G%wyTvw(e)7P1n*qj@w;gQ3mL;If}$7m{stu#in1!|d$ zso~L)7EG4Q*lYF~!(M$%AAM0TwMfhaISYO_2f%rtP6H19Yz0z)UjsjaUk0}ZZUnas z8iFPR%HRiZ184vUAe%bA=1=CTGh-*QNGn~;!gw1m@*gx7kfa%hiEEp$wkq08weH~@e*b(_`R zSILvt*I%X~9q&2dOacgUDjW+mLXMBZ5#9x_@tdK^eGb$BLLnf-KH|f~-+CB)Pkf2^ z3h^~!kC#CmaRc#6;%4F}h?B(K#5;)xiHC^26L8&dRe)B4sKPliWJ{3Ua4ZIu6OR6b zqYwN>i%!HGDLB$n)=(IR&j&Y*ufkv${w<~j8X=I|T-rhEa%9$$JfC;keI(7f8gSZ% z5hzmAMbEt}*_S{8ZIfX<=ryq(w$V=H{q57sEMIm47$+qjCV_=$k2|D@vq5PomV5x- zi2cgfKHF!Z{5Ri3%m{c?7ax=T#TE8{8}Cl@_;VDqEEP*2At^CSwox?X7S(^$G z>dXy%2Z}Zl_}DESP7~S6*jvEwXZR*lPBQi}!>^h0BV)fZ3<=6gfi(+Q5ENZt!vel7 zC?5*!QvtsdlwSn)yMPU%vQ}i9M0{3M4vOq05#JY;Pek^)h(CzR6_H&Nak->ykk}Rp z_e#oy#HJ)XB`Kdt>?vtXOxaf>trs2n zizAd8Kuf}EHGDK-BZL!Eyq(LDncy}N+9|oZy%%Z|9Pa^DQ%CCOY@k1yb#c-YsR>~c zdm^$X{|$kwT8Uzf2p_GVyx0?2tqmNXw}Go#$)Tuu&(vT;*VCH1=S-`not;PU+F6p= z@2O=b_bu-~-2;v4)~d4>=1f+t`;|SRA-8jMomR$Eoe2}RV#}XE52I1h_+W| zM$W7xgr@nms9L#$o)Sq{zHKnJO5Lw0L^Fu(hdUf!|$p#DE-*bd&QT>C0` zx1FOr{`9>ojRoXdKS diff --git a/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bsf b/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bsf deleted file mode 100644 index 004abf0..0000000 --- a/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bsf +++ /dev/null @@ -1,11669 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Skylake/Kabylake - -SKIP 2 bit ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -SKIP 1 bit ; Obsolete. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits ; Reserved bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from SKL/KBL -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; Internal LFP Data structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -$Int_LFP_Slave_Dvo_Port 1 byte ; Slave DVO port for LFP display. - -SKIP 3 bytes ; Skip reserved_1 and add-in offset fields -$Int_eDP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip 11 bytes -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct -SKIP 1 byte ; Skip DP Max link rate for EDP. - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP1_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 1 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP1_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP2_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 2 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP2_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate. - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP3_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 3 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$LSPcon3_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP3_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -; Device 4 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP4_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP4_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP4_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP4_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP4_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP4_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP4_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP4_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP4_EDIDless_en 1 bit ; EDIDless enable bit -$EFP4_Compression_Enable 1 bit ; Compression enable bit -$EFP4_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP4_Dual_Pipe_Ganged_Enable 1 bit ; EFP4 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP4_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -$EFP4_Slave_Dvo_Port 1 byte ; Slave DVO port number for EFP 4 -SKIP 1 byte ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP4_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP4_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing Info Ptr and DVO Config -$Int_EFP4_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP4_Lane_Reversal 1 bit ; Port Reversal -$LSPcon4_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP4_IBoost_Enable 1 bit ; IBoost enable/disable bit -SKIP 1 bit ; HPD inversion bit for BXT. -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP4_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP4_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -$EFP4_Thunderbolt_Feature_Enabled 1 bit ; Thunderbolt feature enabled -SKIP 2 bits ; Reserved -$EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for this port -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level -SKIP 1 byte ; Skip DP Max link rate - -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure -SKIP 39 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -SKIP 2 bits ; Obsolete: Was used for LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -SKIP 1 bit ; Obsolete. -SKIP 1 bit ; Obsolete. -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -SKIP 4 bits ; Obsolete. Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -SKIP 4 bits ; Obsolete. Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_01 4 bits ; eDp selects VSwing Preemph table for panel #01 -$eDP_VSwingPreEmph_02 4 bits ; eDp selects VSwing Preemph table for panel #02 -$eDP_VSwingPreEmph_03 4 bits ; eDp selects VSwing Preemph table for panel #03 -$eDP_VSwingPreEmph_04 4 bits ; eDp selects VSwing Preemph table for panel #04 -$eDP_VSwingPreEmph_05 4 bits ; eDp selects VSwing Preemph table for panel #05 -$eDP_VSwingPreEmph_06 4 bits ; eDp selects VSwing Preemph table for panel #06 -$eDP_VSwingPreEmph_07 4 bits ; eDp selects VSwing Preemph table for panel #07 -$eDP_VSwingPreEmph_08 4 bits ; eDp selects VSwing Preemph table for panel #08 -$eDP_VSwingPreEmph_09 4 bits ; eDp selects VSwing Preemph table for panel #09 -$eDP_VSwingPreEmph_10 4 bits ; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits ; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits ; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits ; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits ; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits ; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits ; eDp selects VSwing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -$eDP_Fast_Link_Training_Data_Rate_01 2 bytes ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_02 2 bytes ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_03 2 bytes ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_04 2 bytes ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_05 2 bytes ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_06 2 bytes ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_07 2 bytes ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_08 2 bytes ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_09 2 bytes ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_10 2 bytes ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_11 2 bytes ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_12 2 bytes ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_13 2 bytes ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_14 2 bytes ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_15 2 bytes ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz -$eDP_Fast_Link_Training_Data_Rate_16 2 bytes ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for SKL/KBL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for SKL/KBL -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsolete -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -$Panel_Rotation_01 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_02 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_03 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_04 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_05 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_06 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_07 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_08 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_09 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_10 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_11 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_12 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_13 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_14 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_15 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. -$Panel_Rotation_16 2 bits ; 00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree. - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -SKIP 2 bytes ; EnableScaling - -SKIP 16 bytes ; Seamless_DRRS_Min_RR - -SKIP 16 bytes ; Pixel overlap count field -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Obsolete. - -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -SKIP 3 bits ; Obsolete. -SKIP 5 bits ; Reserved - -$DPST_Enable_01 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01. -$DPST_Enable_02 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02. -$DPST_Enable_03 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03. -$DPST_Enable_04 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04. -$DPST_Enable_05 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05. -$DPST_Enable_06 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06. -$DPST_Enable_07 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07. -$DPST_Enable_08 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08. -$DPST_Enable_09 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09. -$DPST_Enable_10 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10. -$DPST_Enable_11 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11. -$DPST_Enable_12 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12. -$DPST_Enable_13 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13. -$DPST_Enable_14 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14. -$DPST_Enable_15 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15. -$DPST_Enable_16 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16. - -$PSR_Enable_01 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01. -$PSR_Enable_02 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02. -$PSR_Enable_03 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03. -$PSR_Enable_04 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04. -$PSR_Enable_05 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05. -$PSR_Enable_06 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06. -$PSR_Enable_07 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07. -$PSR_Enable_08 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08. -$PSR_Enable_09 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09. -$PSR_Enable_10 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10. -$PSR_Enable_11 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11. -$PSR_Enable_12 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12. -$PSR_Enable_13 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13. -$PSR_Enable_14 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14. -$PSR_Enable_15 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15. -$PSR_Enable_16 1 bit ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16. - -$DRRS_Enable_01 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01. -$DRRS_Enable_02 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02. -$DRRS_Enable_03 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03. -$DRRS_Enable_04 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04. -$DRRS_Enable_05 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05. -$DRRS_Enable_06 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06. -$DRRS_Enable_07 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07. -$DRRS_Enable_08 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08. -$DRRS_Enable_09 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09. -$DRRS_Enable_10 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10. -$DRRS_Enable_11 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11. -$DRRS_Enable_12 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12. -$DRRS_Enable_13 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13. -$DRRS_Enable_14 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14. -$DRRS_Enable_15 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15. -$DRRS_Enable_16 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16. - -$LACE_Enable_01 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #01. -$LACE_Enable_02 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #02. -$LACE_Enable_03 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #03. -$LACE_Enable_04 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #04. -$LACE_Enable_05 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #05. -$LACE_Enable_06 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #06. -$LACE_Enable_07 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #07. -$LACE_Enable_08 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #08. -$LACE_Enable_09 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #09. -$LACE_Enable_10 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #10. -$LACE_Enable_11 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #11. -$LACE_Enable_12 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #12. -$LACE_Enable_13 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #13. -$LACE_Enable_14 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #14. -$LACE_Enable_15 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #15. -$LACE_Enable_16 1 bit ; Display LACE Support Feature Enable/Disable Flag for Panel #16. - - -$ADT_Enable_01 1 bit ; Assertive display technology enable/disable for Panel #01. -$ADT_Enable_02 1 bit ; Assertive display technology enable/disable for Panel #02. -$ADT_Enable_03 1 bit ; Assertive display technology enable/disable for Panel #03. -$ADT_Enable_04 1 bit ; Assertive display technology enable/disable for Panel #04. -$ADT_Enable_05 1 bit ; Assertive display technology enable/disable for Panel #05. -$ADT_Enable_06 1 bit ; Assertive display technology enable/disable for Panel #06. -$ADT_Enable_07 1 bit ; Assertive display technology enable/disable for Panel #07. -$ADT_Enable_08 1 bit ; Assertive display technology enable/disable for Panel #08. -$ADT_Enable_09 1 bit ; Assertive display technology enable/disable for Panel #09. -$ADT_Enable_10 1 bit ; Assertive display technology enable/disable for Panel #10. -$ADT_Enable_11 1 bit ; Assertive display technology enable/disable for Panel #11. -$ADT_Enable_12 1 bit ; Assertive display technology enable/disable for Panel #12. -$ADT_Enable_13 1 bit ; Assertive display technology enable/disable for Panel #13. -$ADT_Enable_14 1 bit ; Assertive display technology enable/disable for Panel #14. -$ADT_Enable_15 1 bit ; Assertive display technology enable/disable for Panel #15. -$ADT_Enable_16 1 bit ; Assertive display technology enable/disable for Panel #16. - -$DMRRS_Enable_01 1 bit ; Dynamic media refresh rate enable/disable for Panel #01. -$DMRRS_Enable_02 1 bit ; Dynamic media refresh rate enable/disable for Panel #02. -$DMRRS_Enable_03 1 bit ; Dynamic media refresh rate enable/disable for Panel #03. -$DMRRS_Enable_04 1 bit ; Dynamic media refresh rate enable/disable for Panel #04. -$DMRRS_Enable_05 1 bit ; Dynamic media refresh rate enable/disable for Panel #05. -$DMRRS_Enable_06 1 bit ; Dynamic media refresh rate enable/disable for Panel #06. -$DMRRS_Enable_07 1 bit ; Dynamic media refresh rate enable/disable for Panel #07. -$DMRRS_Enable_08 1 bit ; Dynamic media refresh rate enable/disable for Panel #08. -$DMRRS_Enable_09 1 bit ; Dynamic media refresh rate enable/disable for Panel #09. -$DMRRS_Enable_10 1 bit ; Dynamic media refresh rate enable/disable for Panel #10. -$DMRRS_Enable_11 1 bit ; Dynamic media refresh rate enable/disable for Panel #11. -$DMRRS_Enable_12 1 bit ; Dynamic media refresh rate enable/disable for Panel #12. -$DMRRS_Enable_13 1 bit ; Dynamic media refresh rate enable/disable for Panel #13. -$DMRRS_Enable_14 1 bit ; Dynamic media refresh rate enable/disable for Panel #14. -$DMRRS_Enable_15 1 bit ; Dynamic media refresh rate enable/disable for Panel #15. -$DMRRS_Enable_16 1 bit ; Dynamic media refresh rate enable/disable for Panel #16. - -$ADB_Enable_01 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01. -$ADB_Enable_02 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02. -$ADB_Enable_03 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03. -$ADB_Enable_04 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04. -$ADB_Enable_05 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05. -$ADB_Enable_06 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06. -$ADB_Enable_07 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07. -$ADB_Enable_08 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08. -$ADB_Enable_09 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09. -$ADB_Enable_10 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10. -$ADB_Enable_11 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11. -$ADB_Enable_12 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12. -$ADB_Enable_13 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13. -$ADB_Enable_14 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14. -$ADB_Enable_15 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15. -$ADB_Enable_16 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16. - -$LACE_Status_01 1 bit ;Default Display LACE Status enable/disable Flag for Panel #01. -$LACE_Status_02 1 bit ;Default Display LACE Status enable/disable Flag for Panel #02. -$LACE_Status_03 1 bit ;Default Display LACE Status enable/disable Flag for Panel #03. -$LACE_Status_04 1 bit ;Default Display LACE Status enable/disable Flag for Panel #04. -$LACE_Status_05 1 bit ;Default Display LACE Status enable/disable Flag for Panel #05. -$LACE_Status_06 1 bit ;Default Display LACE Status enable/disable Flag for Panel #06. -$LACE_Status_07 1 bit ;Default Display LACE Status enable/disable Flag for Panel #07. -$LACE_Status_08 1 bit ;Default Display LACE Status enable/disable Flag for Panel #08. -$LACE_Status_09 1 bit ;Default Display LACE Status enable/disable Flag for Panel #09. -$LACE_Status_10 1 bit ;Default Display LACE Status enable/disable Flag for Panel #10. -$LACE_Status_11 1 bit ;Default Display LACE Status enable/disable Flag for Panel #11. -$LACE_Status_12 1 bit ;Default Display LACE Status enable/disable Flag for Panel #12. -$LACE_Status_13 1 bit ;Default Display LACE Status enable/disable Flag for Panel #13. -$LACE_Status_14 1 bit ;Default Display LACE Status enable/disable Flag for Panel #14. -$LACE_Status_15 1 bit ;Default Display LACE Status enable/disable Flag for Panel #15. -$LACE_Status_16 1 bit ;Default Display LACE Status enable/disable Flag for Panel #16. - -$DPST_Aggressiveness_Profile_01 4 bits ;DPST Aggressiveness profile Input Selection for Panel #01. -$LACE_Aggressiveness_Profile_01 4 bits ;Lace Aggressiveness profile Input Selection for Panel #01. - -$DPST_Aggressiveness_Profile_02 4 bits ;DPST Aggressiveness profile Input Selection for Panel #02. -$LACE_Aggressiveness_Profile_02 4 bits ;Lace Aggressiveness profile Input Selection for Panel #02. - -$DPST_Aggressiveness_Profile_03 4 bits ;DPST Aggressiveness profile Input Selection for Panel #03. -$LACE_Aggressiveness_Profile_03 4 bits ;Lace Aggressiveness profile Input Selection for Panel #03. - -$DPST_Aggressiveness_Profile_04 4 bits ;DPST Aggressiveness profile Input Selection for Panel #04. -$LACE_Aggressiveness_Profile_04 4 bits ;Lace Aggressiveness profile Input Selection for Panel #04. - -$DPST_Aggressiveness_Profile_05 4 bits ;DPST Aggressiveness profile Input Selection for Panel #05. -$LACE_Aggressiveness_Profile_05 4 bits ;Lace Aggressiveness profile Input Selection for Panel #05. - -$DPST_Aggressiveness_Profile_06 4 bits ;DPST Aggressiveness profile Input Selection for Panel #06. -$LACE_Aggressiveness_Profile_06 4 bits ;Lace Aggressiveness profile Input Selection for Panel #06. - -$DPST_Aggressiveness_Profile_07 4 bits ;DPST Aggressiveness profile Input Selection for Panel #07. -$LACE_Aggressiveness_Profile_07 4 bits ;Lace Aggressiveness profile Input Selection for Panel #07. - -$DPST_Aggressiveness_Profile_08 4 bits ;DPST Aggressiveness profile Input Selection for Panel #08. -$LACE_Aggressiveness_Profile_08 4 bits ;Lace Aggressiveness profile Input Selection for Panel #08. - -$DPST_Aggressiveness_Profile_09 4 bits ;DPST Aggressiveness profile Input Selection for Panel #09. -$LACE_Aggressiveness_Profile_09 4 bits ;Lace Aggressiveness profile Input Selection for Panel #09. - -$DPST_Aggressiveness_Profile_10 4 bits ;DPST Aggressiveness profile Input Selection for Panel #10. -$LACE_Aggressiveness_Profile_10 4 bits ;Lace Aggressiveness profile Input Selection for Panel #10. - -$DPST_Aggressiveness_Profile_11 4 bits ;DPST Aggressiveness profile Input Selection for Panel #11. -$LACE_Aggressiveness_Profile_11 4 bits ;Lace Aggressiveness profile Input Selection for Panel #11. - -$DPST_Aggressiveness_Profile_12 4 bits ;DPST Aggressiveness profile Input Selection for Panel #12. -$LACE_Aggressiveness_Profile_12 4 bits ;Lace Aggressiveness profile Input Selection for Panel #12. - -$DPST_Aggressiveness_Profile_13 4 bits ;DPST Aggressiveness profile Input Selection for Panel #13. -$LACE_Aggressiveness_Profile_13 4 bits ;Lace Aggressiveness profile Input Selection for Panel #13. - -$DPST_Aggressiveness_Profile_14 4 bits ;DPST Aggressiveness profile Input Selection for Panel #14. -$LACE_Aggressiveness_Profile_14 4 bits ;Lace Aggressiveness profile Input Selection for Panel #14. - -$DPST_Aggressiveness_Profile_15 4 bits ;DPST Aggressiveness profile Input Selection for Panel #15. -$LACE_Aggressiveness_Profile_15 4 bits ;Lace Aggressiveness profile Input Selection for Panel #15. - -$DPST_Aggressiveness_Profile_16 4 bits ;DPST Aggressiveness profile Input Selection for Panel #16. -$LACE_Aggressiveness_Profile_16 4 bits ;Lace Aggressiveness profile Input Selection for Panel #16. - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -; Luminance and gamma data structure - -; Flat Panel #01 -$Override_LUM_Data_01 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_01 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_01 2 bytes ; Native minimum luminance -$MaxFullLuminance_01 2 bytes ; Native maximum luminance -$MaxLuminance_01 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_01 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #02 -$Override_LUM_Data_02 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_02 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_02 2 bytes ; Native minimum luminance -$MaxFullLuminance_02 2 bytes ; Native maximum luminance -$MaxLuminance_02 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_02 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #03 -$Override_LUM_Data_03 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_03 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_03 2 bytes ; Native minimum luminance -$MaxFullLuminance_03 2 bytes ; Native maximum luminance -$MaxLuminance_03 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_03 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #04 -$Override_LUM_Data_04 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_04 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_04 2 bytes ; Native minimum luminance -$MaxFullLuminance_04 2 bytes ; Native maximum luminance -$MaxLuminance_04 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_04 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #05 -$Override_LUM_Data_05 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_05 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_05 2 bytes ; Native minimum luminance -$MaxFullLuminance_05 2 bytes ; Native maximum luminance -$MaxLuminance_05 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_05 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #06 -$Override_LUM_Data_06 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_06 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_06 2 bytes ; Native minimum luminance -$MaxFullLuminance_06 2 bytes ; Native maximum luminance -$MaxLuminance_06 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_06 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #07 -$Override_LUM_Data_07 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_07 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_07 2 bytes ; Native minimum luminance -$MaxFullLuminance_07 2 bytes ; Native maximum luminance -$MaxLuminance_07 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_07 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #08 -$Override_LUM_Data_08 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_08 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_08 2 bytes ; Native minimum luminance -$MaxFullLuminance_08 2 bytes ; Native maximum luminance -$MaxLuminance_08 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_08 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #09 -$Override_LUM_Data_09 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_09 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_09 2 bytes ; Native minimum luminance -$MaxFullLuminance_09 2 bytes ; Native maximum luminance -$MaxLuminance_09 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_09 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #10 -$Override_LUM_Data_10 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_10 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_10 2 bytes ; Native minimum luminance -$MaxFullLuminance_10 2 bytes ; Native maximum luminance -$MaxLuminance_10 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_10 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #11 -$Override_LUM_Data_11 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_11 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_11 2 bytes ; Native minimum luminance -$MaxFullLuminance_11 2 bytes ; Native maximum luminance -$MaxLuminance_11 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_11 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #12 -$Override_LUM_Data_12 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_12 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_12 2 bytes ; Native minimum luminance -$MaxFullLuminance_12 2 bytes ; Native maximum luminance -$MaxLuminance_12 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_12 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #13 -$Override_LUM_Data_13 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_13 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_13 2 bytes ; Native minimum luminance -$MaxFullLuminance_13 2 bytes ; Native maximum luminance -$MaxLuminance_13 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_13 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #14 -$Override_LUM_Data_14 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_14 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_14 2 bytes ; Native minimum luminance -$MaxFullLuminance_14 2 bytes ; Native maximum luminance -$MaxLuminance_14 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_14 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #15 -$Override_LUM_Data_15 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_15 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_15 2 bytes ; Native minimum luminance -$MaxFullLuminance_15 2 bytes ; Native maximum luminance -$MaxLuminance_15 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_15 1 byte ; Gamma Range from 00h to FFh. - -; Luminance data structure -; Flat Panel #16 -$Override_LUM_Data_16 1 bit ; Override Luminance value enable bit -$Override_Gamma_Data_16 1 bit ; Override gamma value enable bit. -SKIP 6 bits ; Reserved -$MinLuminance_16 2 bytes ; Native minimum luminance -$MaxFullLuminance_16 2 bytes ; Native maximum luminance -$MaxLuminance_16 2 bytes ; Native Maximum Luminance (1% Rectangular Coverage) -$Gamma_16 1 byte ; Gamma Range from 00h to FFh. - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -; This is the list for the selection of the Device Class for DDI-E only. -List &Int_EFP4_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Supported_List - Selection 0, "Not supported" - Selection 1, "Supported" -EndList -List &Aggressiveness_Level_Profile - Selection 0x00, "Minimum" - Selection 0x01, "Moderate" - Selection 0x02, "High" -EndList -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x03, "HDMI-D" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" - Selection 0x09, "DisplayPort-D" -EndList - -List &Int_EFP4_Port_List - Selection 0x00, "N/A" - Selection 0x0B, "DisplayPort-E" -EndList - -List &eDP_Port_List - Selection 0x0A, "DisplayPort-A" - ;Selection 0x09, "DisplayPort-D" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "AUX Channel A" - Selection 0x10, "AUX Channel B" - Selection 0x20, "AUX Channel C" - Selection 0x30, "AUX Channel D" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "AUX Channel A" - ;Selection 0x30, "AUX Channel D" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" - Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" - Selection 0x06, "Integrated HDMI-D DDC GPIO Pins" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &Panel_Rotation_List - Selection 0x00, " 0 Degree" - ;Selection 0x01, " 90 Degree" - Selection 0x02, "180 Degree" - ;Selection 0x03, "270 Degree" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &DP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" -EndList - -List &IBoost_Magnitude_List - Selection 0, "0x1" - Selection 1, "0x3" - Selection 2, "0x7" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - Selection 0xFF, "PANEL #FF" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - Selection 0x00, "400mV 0.0dB" - Selection 0x01, "400mV 3.5dB" - Selection 0x02, "400mV 6.0dB" - Selection 0x03, "450mV 0.0dB" - Selection 0x04, "600mV 0.0dB" - Selection 0x05, "600mV 2.5dB" - Selection 0x06, "600mV 4.5dB" - Selection 0x07, "800mV 0.0dB" - Selection 0x08, "800mV 2.0dB" - Selection 0x09, "1000mV 2.0dB" - Selection 0x0A, "1200mV 0.0dB" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "1 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PrimaryDisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &SecondaryDisplayList - Selection 0x04, "EFP" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x10, "EFP4" - Selection 0x00, "None" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - ; Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface (OLED)" - Selection 0x5, "VESA eDP AUX Interface" -EndList - -List &Dp_Port_Trace_Length_List - Selection 0x0, "RVP Default" - Selection 0x1, "Short trace length" - Selection 0x2, "Long trace length" -EndList -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Skylake/Kabylake" - Title "VBT version: 228" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - Windows Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "Windows Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, "VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if there’s no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel® Rapid Memory Power Management (RMPM)\r\n" - "2. Intel® Smart 2D Display Technology (S2DDT)\r\n" - "3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "4. Graphics Render Standby (RS)\r\n" - "5. Intel® Turbo Boost Technology\r\n" - "6. Dynamic Frames Per Second (DFPS)\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel® Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Turbo Boost Technology is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "Windows Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List, - Help "This feature is for configuring LFP usage.\r\n" - "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device." - - Title " " - Combo $Int_eDP_Port, "Select Output port: ", &eDP_Port_List, - Help "This feature, when enabled, will activate support for an eDP. " - "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n" - "Note: For both mobile and desktop SKL/KBL boards, eDP is supported on Port A only." - - Combo $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n" - "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT." - "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF." - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - - Combo $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List, - Help "This feature allows for configuring two different ports to be used for a single eDP panel.\n" - "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n" - "When disabled, eDP display will always use DDI-A" - - Combo $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List, - Help "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n" - "This field will be ignored by the software if dual port ganged support for eDP is disabled." - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - - ;============================================================================== - ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #01 " - EditText $Panel_Name_01, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_01, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_01, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" , "PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_01, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_01,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_01, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_01, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_01, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_01, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; Panel #01 - - ;============================================================================== - ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - EditText $Panel_Name_02, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_02, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_02, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_02, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_02,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_02, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_02, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_02, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_02, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #03 " - EditText $Panel_Name_03, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_03, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_03, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_03, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_03,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_03, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_03, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_03, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_03, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #04 " - EditText $Panel_Name_04, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_04, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_04, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_04, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_04,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_04, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_04, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_04, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_04, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #05 " - EditText $Panel_Name_05, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_05, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_05, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_05, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_05,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_05, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_05, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_05, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_05, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #06 " - EditText $Panel_Name_06, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_06, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_06, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_06, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_06,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_06, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_06, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_06, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_06, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - EditText $Panel_Name_07, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_07, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_07, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_07, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_07,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_07, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_07, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_07, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_07, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery) " - - Combo $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - EditText $Panel_Name_08, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_08, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_08, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_08, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_08,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_08, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_08, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_08, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled." - - Combo $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_08, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - EditText $Panel_Name_09, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_09, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_09, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_09, " BackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_09, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_09,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_09, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_09, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_09, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_09, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - - Combo $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - EditText $Panel_Name_10, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_10, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_10, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_10, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_10,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_10, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_10, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_10, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_10, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - EditText $Panel_Name_11, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_11, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_11, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_11, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_11,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_11, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_11, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_11, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_11, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST )\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - EditText $Panel_Name_12, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_12, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_12, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_12, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_12,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_12, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_12, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_12, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADB_Enable_12, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - EditText $Panel_Name_13, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_13, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_13, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_13, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_13,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_13, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_13, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_13, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_13, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - EditText $Panel_Name_14, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_14, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_14, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_14, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_14,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_14, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - Combo $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_14, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_14, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_14, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - EditText $Panel_Name_15, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_15, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_15, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_15, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_15,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_15, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_15, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_15, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_15, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - EditText $Panel_Name_16, "LFP panel name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - EditNum $Panel_Width_16, "LFP Width:", DEC, - Help "This value specifies the LFP pixel width for this panel type." - - EditNum $Panel_Height_16, "LFP Height:", DEC, - Help "This value specifies the LFP pixel height (number of scan lines) for this panel type." - - Combo $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Skylake/Kabylake, based on the selection respective table will be used.\r\n" - "Tables for Skylake/Kabylake: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List, - Help "This feature specifies the Panel Rotation of eDP panel used." - - TitleB "eDP Spread Spectrum Clock Features" - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP." - - TitleB "DPS Panel Type Features (Mobile only)" - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - TitleB "BackLight Technology Type Features (Mobile only)" - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology." - - Title " " - Link "PSR feature" ,"PSR feature" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - Link "Apical Feature" , "Apical Feature" - Link "Power Features" , "Power Features" - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - - Combo $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override luminance values following VBT values" - - EditNum $MinLuminance_16, "\tMinimum Luminance" , EHEX, - Help "Minimum luminance value. \r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX, - Help "Maximum Full frame luminance value.\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - EditNum $MaxLuminance_16,"\tMaximum Luminance" , EHEX, - Help "Maximum luminance value(Relatively smaller portion of screen).\r\n" - "2 byte value, encoded in IEEE 754 half-precision binary floating point format" - - Combo $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override gamma values through following VBT data" - - EditNum $Gamma_16, "\tPanel gamma" , EHEX, - Help " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n" - " Field Value = (Gamma (value in float) x 100) - 100 \n" - " Field values range from 00h through FFh. \n" - " FFh = No gamma information shall be provided \n" - - EndPage ; Chromaticity Control - - Page "eDP Link Training Configuration Parameters" - Link "Close Table" , ".." - - TitleB "Full Link Training Parameters" - - Combo $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List, - Help "This feature allows for the enable/disable of providing initial parameters for full link training." - - Combo $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Title " " - - TitleB "Fast Link Training Parameters" - - Combo $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - EditNum $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC, - Help "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - - Combo $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training.\r\n" - "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n" - "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n" - "For Example: Panel #3 is configured for eDP. " - "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. " - "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 1 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - - Page "Power Features" - Link "Close Table" , ".." - - Combo $DPST_Enable_16, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $DRRS_Enable_16, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Display Lace Support " - "otherwise, the functionality will be disabled. " - - Combo $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Combo $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled. " - - Combo $ADB_Enable_16, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Combo $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List, - Help "This feature, when enabled, will set Default Display LACE Enabled status " - "otherwise, the functionality will be disabled." - - Combo $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List, - Help "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n" - "1 (Maximum Quality with No DPST)\n" - "2\n" - "3\n" - "4\n" - "5\n" - "6 (Maximum Battery)" - - Combo $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile, - Help "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n" - "Minimum 0\n" - "Moderate 1\n" - "High 2" - EndPage ; Power Features - EndPage ; "Panel #16 " - EndPage ; "LFP Configuration" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - Link "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - Combo $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Combo $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - - Title " " - - Combo $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List, - Help "This field determines the DP port trace length from silicon to the DP output port.\r\n" - "The default setting is as per Intel Reference boards or RVP.\r\n" - "Custom boards with short of long trace length may select the trace length appropriately." - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link." - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - EndPage ; "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 4 (EFP4) - ;------------------------------------------------------------------------------ - Page "Device 4 (EFP4 for DDI-E only)" - Link "Close Window" , ".." - - Combo $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels" - - Combo $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List, - Help "This field is applicable only if IBoost is enabled for the selected port." - "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7" - - EndPage ; "Device 4 (EFP4)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00001000b ; Toggle display to second DP Port on EFP3 and LFP combination." - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table (Mobile only)" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" - "\t00000100 00001000b ; Second DP Port on EFP3 and LFP to be removed." -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - EditNum $OEM_Mode_X1, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/CometLakeFspBinPkg/Docs/CometLake_FSP_Integration_Guide.chm b/CometLakeFspBinPkg/Docs/CometLake_FSP_Integration_Guide.chm deleted file mode 100644 index ab4b4fa646295793d6390d89b4770c64025e8c73..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 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All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ - -#pragma pack() - -#endif diff --git a/ApolloLakeFspBinPkg/Include/FspmUpd.h b/ApolloLakeFspBinPkg/Include/FspmUpd.h deleted file mode 100644 index f0ed779..0000000 --- a/ApolloLakeFspBinPkg/Include/FspmUpd.h +++ /dev/null @@ -1,903 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 4 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT16 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Debug Serial Port Base address - Debug serial port base address. This option will be used only when the 'Serial Port - Debug Device' option is set to 'External Device'. 0x00000000(Default). -**/ - UINT32 SerialDebugPortAddress; - -/** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. - 0x02:MMIO(Default). - 0:NONE, 1:I/O, 2:MMIO -**/ - UINT8 SerialDebugPortType; - -/** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port - Base' options will be ignored. 0x02:SOC UART2(Default). - 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device -**/ - UINT8 SerialDebugPortDevice; - -/** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). - 0:1, 2:4 -**/ - UINT8 SerialDebugPortStrideSize; - -/** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video - Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 Igd; - -/** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal - Graphics Device. 0x02:64 MB(Default). - 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 - MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, - 0x0F:480 MB, 0x10:512 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), - 0x2:256 MB, 0x3:512 MB. - 0x1:128 MB, 0x2:256 MB, 0x3:512 MB -**/ - UINT8 IgdApertureSize; - -/** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 - MB(Default). - 0x1:2 MB, 0x2:4 MB, 0x3:8 MB -**/ - UINT8 GttSize; - -/** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), - 0x2:IGD, 0x3:PCI - 0x0:AUTO, 0x2:IGD, 0x3:PCI -**/ - UINT8 PrimaryVideoAdaptor; - -/** Offset 0x004D - Package - NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); - 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored - (DDR3L); Refer to the IAFW spec for specific details about each CA mapping. - 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank - 1 Mirrored (DDR3L) -**/ - UINT8 Package; - -/** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 -**/ - UINT8 Profile; - -/** Offset 0x004F - MemoryDown - Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 -**/ - UINT8 MemoryDown; - -/** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB. - 0x1:1KB, 0x2:2KB -**/ - UINT8 DDR3LPageSize; - -/** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment - in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported. - 0x0:Not Supported, 0x1:Supported -**/ - UINT8 DDR3LASR; - -/** Offset 0x0052 - ScramblerSupport - Scrambler Support - Enable or disable the memory scrambler. Data scrambling is - provided as a means to increase signal integrity/reduce RFI generated by the DRAM - interface. This is achieved by randomizing seed that encodes/decodes memory data - so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, - 01: Enable Scrambler Support - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x0053 - InterleavedMode - This field is ignored if one of the PnP channel configurations is used. If the memory - configuration is different, then the field is used directly to populate. 0x00:Disable(Default), - 0x02:Enable. - 0x0:Disable, 0x2:Enable -**/ - UINT8 InterleavedMode; - -/** Offset 0x0054 - ChannelHashMask - ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be - modified. These inputs are not used for configurations where an optimized ChannelHashMask - has been provided by the PnP validation teams. 0x00(Default). -**/ - UINT16 ChannelHashMask; - -/** Offset 0x0056 - SliceHashMask - ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be - modified. These inputs are not used for configurations where an optimized ChannelHashMask - has been provided by the PnP validation teams. 0x00(Default). -**/ - UINT16 SliceHashMask; - -/** Offset 0x0058 - ChannelsSlicesEnable - ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration - is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 ChannelsSlicesEnable; - -/** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 MinRefRate2xEnable; - -/** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 DualRankSupportEnable; - -/** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled). - 0x0:Disabled, 0x3:Enabled -**/ - UINT8 RmtMode; - -/** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and - the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, - 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) -**/ - UINT16 MemorySizeLimit; - -/** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below - 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 - = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). -**/ - UINT16 LowMemoryMaxValue; - -/** Offset 0x0060 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above - 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, - 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). -**/ - UINT16 HighMemoryMaxValue; - -/** Offset 0x0062 - DisableFastBoot - 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; - Full re-train of memory on every boot. - $EN_DIS -**/ - UINT8 DisableFastBoot; - -/** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). -**/ - UINT8 DIMM0SPDAddress; - -/** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). -**/ - UINT8 DIMM1SPDAddress; - -/** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch0_RankEnable; - -/** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch0_DeviceWidth; - -/** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch0_DramDensity; - -/** Offset 0x0068 - Ch0_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch0_Option; - -/** Offset 0x0069 - Ch0_OdtConfig - [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination - during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 - OHMS or so roughly. Purpose: Save power on these technologies which burn power - directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. - a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, - 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The - customer needs to choose this based on their actual board strapping (how they tie - the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW - ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, - which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS - signals). Purpose: To improve signal integrity and provide a much more optimized - CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), - 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: - 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 - Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care -**/ - UINT8 Ch0_OdtConfig; - -/** Offset 0x006A - Ch0_TristateClk1 - Not used -**/ - UINT8 Ch0_TristateClk1; - -/** Offset 0x006B - Ch0_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch0_Mode2N; - -/** Offset 0x006C - Ch0_OdtLevels - Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to - SoC, 1 - ODT held high -**/ - UINT8 Ch0_OdtLevels; - -/** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch1_RankEnable; - -/** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch1_DeviceWidth; - -/** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch1_DramDensity; - -/** Offset 0x0070 - Ch1_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch1_Option; - -/** Offset 0x0071 - Ch1_OdtConfig - [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination - during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 - OHMS or so roughly. Purpose: Save power on these technologies which burn power - directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. - a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, - 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The - customer needs to choose this based on their actual board strapping (how they tie - the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW - ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, - which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS - signals). Purpose: To improve signal integrity and provide a much more optimized - CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), - 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: - 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 - Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care -**/ - UINT8 Ch1_OdtConfig; - -/** Offset 0x0072 - Ch1_TristateClk1 - Not used -**/ - UINT8 Ch1_TristateClk1; - -/** Offset 0x0073 - Ch1_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch1_Mode2N; - -/** Offset 0x0074 - Ch1_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch1_OdtLevels; - -/** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch2_RankEnable; - -/** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch2_DeviceWidth; - -/** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch2_DramDensity; - -/** Offset 0x0078 - Ch2_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch2_Option; - -/** Offset 0x0079 - Ch2_OdtConfig - [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination - during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 - OHMS or so roughly. Purpose: Save power on these technologies which burn power - directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. - a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, - 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The - customer needs to choose this based on their actual board strapping (how they tie - the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW - ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, - which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS - signals). Purpose: To improve signal integrity and provide a much more optimized - CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), - 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: - 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 - Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care -**/ - UINT8 Ch2_OdtConfig; - -/** Offset 0x007A - Ch2_TristateClk1 - Not used -**/ - UINT8 Ch2_TristateClk1; - -/** Offset 0x007B - Ch2_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch2_Mode2N; - -/** Offset 0x007C - Ch2_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch2_OdtLevels; - -/** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. - NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank - 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be - set to 1 to enable use of this rank. -**/ - UINT8 Ch3_RankEnable; - -/** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel - (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 - and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 - device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch3_DeviceWidth; - -/** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device - density per rank (per Chip Select). The simplest way of identifying the density - per rank is to divide the total SoC memory channel density by the number of ranks. - For DDR3L: Must specify the DRAM device density per DRAM device. For example, an - 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, - a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch3_DramDensity; - -/** Offset 0x0080 - Ch3_Option - BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: - 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] - Bank Address Hashing Enable. See Address Mapping section for full description: - 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 - CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board - designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 - CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register - specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) -**/ - UINT8 Ch3_Option; - -/** Offset 0x0081 - Ch3_OdtConfig - [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination - during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 - OHMS or so roughly. Purpose: Save power on these technologies which burn power - directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. - a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, - 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The - customer needs to choose this based on their actual board strapping (how they tie - the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW - ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, - which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS - signals). Purpose: To improve signal integrity and provide a much more optimized - CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), - 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: - 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 - Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care -**/ - UINT8 Ch3_OdtConfig; - -/** Offset 0x0082 - Ch3_TristateClk1 - Not used -**/ - UINT8 Ch3_TristateClk1; - -/** Offset 0x0083 - Ch3_Mode2N - DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command - mode that provides more setup and hold time for DRAM commands on the DRAM command - bus. This is useful for platforms with unusual CMD bus routing or marginal signal - integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and - Control training), 1 - Force 2N Mode - 0x0:Auto, 0x1:Force 2N CMD Timing Mode -**/ - UINT8 Ch3_Mode2N; - -/** Offset 0x0084 - Ch3_OdtLevels - DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW - (default), 1 - ODT_AB_HIGH_HIGH -**/ - UINT8 Ch3_OdtLevels; - -/** Offset 0x0085 - RmtCheckRun - Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM - MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK -**/ - UINT8 RmtCheckRun; - -/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold - Percentage used to determine the margin tolerances over the failing margin. -**/ - UINT16 RmtMarginCheckScaleHighThreshold; - -/** Offset 0x0088 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently - asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes - on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes - need to follow the DQ byte lane they correspond too. So for example if you have - DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. - Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that - specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion - can arrise from the fact that the indexes to the array do not necessarily map 1:1 - to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value - of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates - a 2 physical channels need to be stuffed and operated together. Are the CHx_A and - CHx_B physical channels operated in tandem or completely separate? If separate, - why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting - up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you - have 2 channels in order to power gate one PHY, those two channel populated must - be on one PHY instance. So yes all channels are independent of each other, but - there are some restrictions on how they need to be populated. Q: How is it that - an LPDDR4 device is identified as having a x16 width when all 32-bits are used - at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 - DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel - the CS of the two devices in the same die are connected together to make a single - rank of one x32 channel (SDP). The second die in the DDP package makes the second rank. -**/ - UINT8 Ch0_Bit_swizzling[32]; - -/** Offset 0x00A8 - Ch1_Bit_swizzling - Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch1_Bit_swizzling[32]; - -/** Offset 0x00C8 - Ch2_Bit_swizzling - Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch2_Bit_swizzling[32]; - -/** Offset 0x00E8 - Ch3_Bit_swizzling - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch3_Bit_swizzling[32]; - -/** Offset 0x0108 - MsgLevelMask - 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages. -**/ - UINT32 MsgLevelMask; - -/** Offset 0x010C -**/ - UINT8 UnusedUpdSpace0[4]; - -/** Offset 0x0110 - PreMem GPIO Pin Number for each table - Number of Pins in each PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTablePinNum[4]; - -/** Offset 0x0114 - PreMem GPIO Table Pointer - Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). -**/ - UINT32 PreMemGpioTablePtr; - -/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 - Number of Entries in PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTableEntryNum; - -/** Offset 0x0119 - Enhance the port 8xh decoding - Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnhancePort8xhDecoding; - -/** Offset 0x011A - SPD Data Write - Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SpdWriteEnable; - -/** Offset 0x011B - MRC Training Data Saving - Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 MrcDataSaving; - -/** Offset 0x011C - OEM File Loading Address - Determine the memory base address to load a specified file from CSE file system - after memory is available. -**/ - UINT32 OemLoadingBase; - -/** Offset 0x0120 - OEM File Name to Load - Specify a file name to load from CSE file system after memory is available. Empty - indicates no file needs to be loaded. -**/ - UINT8 OemFileName[16]; - -/** Offset 0x0130 -**/ - VOID* MrcBootDataPtr; - -/** Offset 0x0134 - eMMC Trace Length - Select eMMC trace length to load OEM file from when loading OEM file name is specified. - 0x0:Long(Default), 0x1:Short. - 0x0:Long, 0x1:Short -**/ - UINT8 eMMCTraceLen; - -/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB - Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of - CSE. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SkipCseRbp; - -/** Offset 0x0136 - Npk Enable - Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). - 0:Disable, 1:Enable, 2:Debugger, 3:Auto -**/ - UINT8 NpkEn; - -/** Offset 0x0137 - FW Trace Enable - Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 FwTraceEn; - -/** Offset 0x0138 - FW Trace Destination - FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, - 4-NPK_TRACE_TO_PTI(Default). -**/ - UINT8 FwTraceDestination; - -/** Offset 0x0139 - NPK Recovery Dump - Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 RecoverDump; - -/** Offset 0x013A - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc0Wrap; - -/** Offset 0x013B - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc1Wrap; - -/** Offset 0x013C - Memory Region 0 Buffer Size - Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc0Size; - -/** Offset 0x0140 - Memory Region 1 Buffer Size - Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc1Size; - -/** Offset 0x0144 - PTI Mode - PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. -**/ - UINT8 PtiMode; - -/** Offset 0x0145 - PTI Training - PTI Training. 0-off(Default), 1-6=1-6. -**/ - UINT8 PtiTraining; - -/** Offset 0x0146 - PTI Speed - PTI Speed. 0-full, 1-half, 2-quarter(Default). -**/ - UINT8 PtiSpeed; - -/** Offset 0x0147 - Punit Message Level - Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PunitMlvl; - -/** Offset 0x0148 - PMC Message Level - PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PmcMlvl; - -/** Offset 0x0149 - SW Trace Enable - Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SwTraceEn; - -/** Offset 0x014A - Periodic Retraining Disable - Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic - Retraining for debug purposes. Periodic Retraining should be enabled in production. - Periodic retraining allows the platform to operate reliably over a larger voltage - and temperature range. This field has no effect for DDR3L and LPDDR3 memory type - configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic - Retraining (debug configuration only) - 0x0:Enabled, 0x1:Disabled -**/ - UINT8 PeriodicRetrainingDisable; - -/** Offset 0x014B - Enable Reset System - Enable FSP to trigger reset instead of returning reset request. 0x00: Return the - Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside - FSP instead of returning from the API. - 0x0:Disabled, 0x1:Eabled -**/ - UINT8 EnableResetSystem; - -/** Offset 0x014C - Enable HECI2 in S3 resume path - Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ; - 0x01: Enable HECI2 in S3 resume path.(Default) - 0x0:Disabled, 0x1:Enabled -**/ - UINT8 EnableS3Heci2; - -/** Offset 0x014D -**/ - UINT8 UnusedUpdSpace1[3]; - -/** Offset 0x0150 -**/ - VOID* VariableNvsBufferPtr; - -/** Offset 0x0154 - PCIE SLOT Power Enable Assert Time - PFET. - ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will - wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer - who designed the board PCIE slot Power automatically enabled, can pass value of - zero here. -**/ - UINT64 StartTimerTickerOfPfetAssert; - -/** Offset 0x015C - Real Time Enabling - Real-Time Feature Configuration Bits settings. 0x0:Disabled (default), 0x1:Enabled - $EN_DIS -**/ - UINT8 RtEn; - -/** Offset 0x015D - Skip Pcie Power Sequence - UPD To Skip PciePowerSequence in FSP if set this UPD is set to 1. 0x0:Disabled (default), 0x1:Skip - 0x0:Disabled, 0x1:Skip -**/ - UINT8 SkipPciePowerSequence; - -/** Offset 0x015E -**/ - UINT8 ReservedFspmUpd[2]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0160 -**/ - UINT8 UnusedUpdSpace2[158]; - -/** Offset 0x01FE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/ApolloLakeFspBinPkg/Include/FspsUpd.h b/ApolloLakeFspBinPkg/Include/FspsUpd.h deleted file mode 100644 index 05b1575..0000000 --- a/ApolloLakeFspBinPkg/Include/FspsUpd.h +++ /dev/null @@ -1,1609 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - ActiveProcessorCores - Number of active cores. 0:Disable(Default), 1:Enable. -**/ - UINT8 ActiveProcessorCores; - -/** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore1; - -/** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore2; - -/** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore3; - -/** Offset 0x0024 - VMX Enable - Enable or Disable VMX. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to - 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) -**/ - UINT8 ProcTraceMemSize; - -/** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ProcTraceEnable; - -/** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. -**/ - UINT8 BootPState; - -/** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableCx; - -/** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, - 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x002D - C-State auto-demotion - C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 - Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion - to C1 and C3. -**/ - UINT8 CStateAutoDemotion; - -/** Offset 0x002E - C-State un-demotion - C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, - 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. -**/ - UINT8 CStateUnDemotion; - -/** Offset 0x002F - Max Core C-State - Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). -**/ - UINT8 MaxCoreCState; - -/** Offset 0x0030 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0031 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0032 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0033 - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. 0(Default). -**/ - UINT8 HdaVerbTableEntryNum; - -/** Offset 0x0034 - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. 0x00000000(Default). -**/ - UINT32 HdaVerbTablePtr; - -/** Offset 0x0038 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 P2sbUnhide; - -/** Offset 0x0039 - IPU Enable/Disable - Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IpuEn; - -/** Offset 0x003A - IMGU ACPI mode selection - 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. - 0:Disable, 1:IGFX Child device, 2:ACPI device -**/ - UINT8 IpuAcpiMode; - -/** Offset 0x003B - Enable ForceWake - Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ForceWake; - -/** Offset 0x003C - GttMmAdr - GttMmAdr structure for initialization. 0xBF000000(Default). -**/ - UINT32 GttMmAdr; - -/** Offset 0x0040 - GmAdr - GmAdr structure for initialization. 0xA0000000(Default). -**/ - UINT32 GmAdr; - -/** Offset 0x0044 - Enable PavpLock - Enable/disable PavpLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PavpLock; - -/** Offset 0x0045 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqModify; - -/** Offset 0x0046 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqReq; - -/** Offset 0x0047 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsVideoFreq; - -/** Offset 0x0048 - Enable PmLock - Enable/disable PmLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmLock; - -/** Offset 0x0049 - Enable DopClockGating - Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DopClockGating; - -/** Offset 0x004A - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnsolicitedAttackOverride; - -/** Offset 0x004B - Enable WOPCMSupport - Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSupport; - -/** Offset 0x004C - Enable WOPCMSize - Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSize; - -/** Offset 0x004D - Enable PowerGating - Enable/disable PowerGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PowerGating; - -/** Offset 0x004E - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnitLevelClockGating; - -/** Offset 0x004F - Enable FastBoot - Enable/disable FastBoot. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 FastBoot; - -/** Offset 0x0050 - Enable DynSR - Enable/disable DynSR. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DynSR; - -/** Offset 0x0051 - Enable SaIpuEnable - Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x0052 - GT PM Support - Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x0053 - RC6(Render Standby) - Enable/Disable render standby support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableRenderStandby; - -/** Offset 0x0054 - BMP Logo Data Size - BMP logo data buffer size. 0x00000000(Default). -**/ - UINT32 LogoSize; - -/** Offset 0x0058 - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. 0x00000000(Default). -**/ - UINT32 LogoPtr; - -/** Offset 0x005C - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. 0x00000000(Default). -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x0060 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0061 - PAVP PR3 - Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpPr3; - -/** Offset 0x0062 - CdClock Frequency selection - 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz -**/ - UINT8 CdClock; - -/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit - Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0064 - Write Protection Support - Enable/disable Write Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 WriteProtectionEnable[5]; - -/** Offset 0x0069 - Read Protection Support - Enable/disable Read Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 ReadProtectionEnable[5]; - -/** Offset 0x006E - Protected Range Limitation - The address of the upper limit of protection, 0x0FFFh(Default). -**/ - UINT16 ProtectedRangeLimit[5]; - -/** Offset 0x0078 - Protected Range Base - The base address of the upper limit of protection. 0x0000(Default). -**/ - UINT16 ProtectedRangeBase[5]; - -/** Offset 0x0082 - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Gmm; - -/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk - Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPgcbClkTrunk; - -/** Offset 0x0084 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSb; - -/** Offset 0x0085 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkTrunk; - -/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition - Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkPartition; - -/** Offset 0x0087 - GMM Clock Gating - Core - Enable/disable Core. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingCore; - -/** Offset 0x0088 - GMM Clock Gating - DMA - Enable/disable DMA. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingDma; - -/** Offset 0x0089 - GMM Clock Gating - Register Access - Enable/disable Register Access. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingRegAccess; - -/** Offset 0x008A - GMM Clock Gating - Host - Enable/disable Host. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingHost; - -/** Offset 0x008B - GMM Clock Gating - Partition - Enable/disable Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPartition; - -/** Offset 0x008C - Clock Gating - Trunk - Enable/disable Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingTrunk; - -/** Offset 0x008D - HD Audio Support - Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 HdaEnable; - -/** Offset 0x008E - HD Audio DSP Support - Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEnable; - -/** Offset 0x008F - Azalia wake-on-ring - Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Pme; - -/** Offset 0x0090 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) - 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and - I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers -**/ - UINT8 HdAudioIoBufferOwnership; - -/** Offset 0x0091 - HD-Audio I/O Buffer Voltage - HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. - 0: 3.3V, 1: 1.8V -**/ - UINT8 HdAudioIoBufferVoltage; - -/** Offset 0x0092 - HD-Audio Virtual Channel Type - HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. - 0: VC0, 1: VC1 -**/ - UINT8 HdAudioVcType; - -/** Offset 0x0093 - HD-Audio Link Frequency - HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioLinkFrequency; - -/** Offset 0x0094 - HD-Audio iDisp-Link Frequency - HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioIDispLinkFrequency; - -/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode - HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. - 0: 2T, 1: 1T -**/ - UINT8 HdAudioIDispLinkTmode; - -/** Offset 0x0096 - HD-Audio Disp DMIC - HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. - 0: Disable, 1: 2ch array, 2: 4ch array -**/ - UINT8 DspEndpointDmic; - -/** Offset 0x0097 - HD-Audio Bluetooth - Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEndpointBluetooth; - -/** Offset 0x0098 - HD-Audio I2S SHK - Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sSkp; - -/** Offset 0x0099 - HD-Audio I2S HP - Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sHp; - -/** Offset 0x009A - HD-Audio Controller Power Gating - Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioCtlPwrGate; - -/** Offset 0x009B - HD-Audio ADSP Power Gating - Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioDspPwrGate; - -/** Offset 0x009C - HD-Audio CSME Memory Transfers - Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Mmt; - -/** Offset 0x009D - HD-Audio Host Memory Transfers - Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Hmt; - -/** Offset 0x009E - HD-Audio Power Gating - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioPwrGate; - -/** Offset 0x009F - HD-Audio Clock Gatingn - Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioClkGate; - -/** Offset 0x00A0 - Bitmask of DSP Feature - Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspFeatureMask; - -/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules - Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspPpModuleMask; - -/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - This option is deprecated - $EN_DIS -**/ - UINT8 BiosCfgLockDown; - -/** Offset 0x00A9 - Enable High Precision Timer - Enable/Disable Hpet. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Hpet; - -/** Offset 0x00AA - Hpet Valid BDF Value - Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HpetBdfValid; - -/** Offset 0x00AB - Bus Number of Hpet - Completer ID of Bus Number of Hpet. Default = 0xFA(Default). -**/ - UINT8 HpetBusNumber; - -/** Offset 0x00AC - Device Number of Hpet - Completer ID of Device Number of Hpet. 0x1F(Default). -**/ - UINT8 HpetDeviceNumber; - -/** Offset 0x00AD - Function Number of Hpet - Completer ID of Function Number of Hpet. 0x00(Default). -**/ - UINT8 HpetFunctionNumber; - -/** Offset 0x00AE - IoApic Valid BDF Value - Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 IoApicBdfValid; - -/** Offset 0x00AF - Bus Number of IoApic - Completer ID of Bus Number of IoApic. 0xFA(Default). -**/ - UINT8 IoApicBusNumber; - -/** Offset 0x00B0 - Device Number of IoApic - Completer ID of Device Number of IoApic. 0x0F(Default). -**/ - UINT8 IoApicDeviceNumber; - -/** Offset 0x00B1 - Function Number of IoApic - Completer ID of Function Number of IoApic. 0x00(Default). -**/ - UINT8 IoApicFunctionNumber; - -/** Offset 0x00B2 - IOAPIC Entry 24-119 - Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IoApicEntry24_119; - -/** Offset 0x00B3 - IO APIC ID - This member determines IOAPIC ID. 0x01(Default). -**/ - UINT8 IoApicId; - -/** Offset 0x00B4 - IoApic Range - Define address bits 19:12 for the IOxAPIC range. 0x00(Default). -**/ - UINT8 IoApicRangeSelect; - -/** Offset 0x00B5 - ISH Controller - Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IshEnable; - -/** Offset 0x00B6 - BIOS Interface Lock Down - Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control - Register. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiosInterface; - -/** Offset 0x00B7 - Bios LockDown Enable - Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosLock; - -/** Offset 0x00B8 - SPI EISS Status - Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SpiEiss; - -/** Offset 0x00B9 - BiosLock SWSMI Number - This member describes the SwSmi value for Bios Lock. 0xA9(Default). -**/ - UINT8 BiosLockSwSmiNumber; - -/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable - Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 LPSS_S0ixEnable; - -/** Offset 0x00BB -**/ - UINT8 UnusedUpdSpace0[1]; - -/** Offset 0x00BC - LPSS I2C Clock Gating Configuration - Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 I2cClkGateCfg[8]; - -/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration - Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 HsuartClkGateCfg[4]; - -/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration - Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 SpiClkGateCfg[3]; - -/** Offset 0x00CB - I2C Device 0 - Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c0Enable; - -/** Offset 0x00CC - I2C Device 1 - Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c1Enable; - -/** Offset 0x00CD - I2C Device 2 - Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c2Enable; - -/** Offset 0x00CE - I2C Device 3 - Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c3Enable; - -/** Offset 0x00CF - I2C Device 4 - Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c4Enable; - -/** Offset 0x00D0 - I2C Device 5 - Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c5Enable; - -/** Offset 0x00D1 - I2C Device 6 - Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c6Enable; - -/** Offset 0x00D2 - I2C Device 7 - Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c7Enable; - -/** Offset 0x00D3 - UART Device 0 - Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart0Enable; - -/** Offset 0x00D4 - UART Device 1 - Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart1Enable; - -/** Offset 0x00D5 - UART Device 2 - Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart2Enable; - -/** Offset 0x00D6 - UART Device 3 - Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart3Enable; - -/** Offset 0x00D7 - SPI UART Device 0 - Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi0Enable; - -/** Offset 0x00D8 - SPI UART Device 1 - Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi1Enable; - -/** Offset 0x00D9 - SPI UART Device 2 - Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi2Enable; - -/** Offset 0x00DA - OS Debug Feature - Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 OsDbgEnable; - -/** Offset 0x00DB - DCI Feature - Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x00DC - UART Debug Base Address - UART Debug Base Address. 0x00000000(Default). -**/ - UINT32 Uart2KernelDebugBaseAddress; - -/** Offset 0x00E0 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). - 0:Enable, 1:Disable -**/ - UINT8 PcieClockGatingDisabled; - -/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PcieRootPort8xhDecode; - -/** Offset 0x00E2 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. 0x00(Default). -**/ - UINT8 Pcie8xhDecodePortIndex; - -/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PcieRootPortPeerMemoryWriteEnable; - -/** Offset 0x00E4 - PCIE SWSMI Number - This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). -**/ - UINT8 PcieAspmSwSmiNumber; - -/** Offset 0x00E5 -**/ - UINT8 UnusedUpdSpace1[1]; - -/** Offset 0x00E6 - PCI Express Root Port - Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRootPortEn[6]; - -/** Offset 0x00EC - Hide PCIE Root Port Configuration Space - Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpHide[6]; - -/** Offset 0x00F2 - PCIE Root Port Slot Implement - Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSlotImplemented[6]; - -/** Offset 0x00F8 - Hot Plug - PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpHotPlug[6]; - -/** Offset 0x00FE - PCIE PM SCI - Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpPmSci[6]; - -/** Offset 0x0104 - PCIE Root Port Extended Sync - Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpExtSync[6]; - -/** Offset 0x010A - Transmitter Half Swing - Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpTransmitterHalfSwing[6]; - -/** Offset 0x0110 - ACS - Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpAcsEnabled[6]; - -/** Offset 0x0116 - Clock Request Support - Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpClkReqSupported[6]; - -/** Offset 0x011C - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, - 0x01, 0x02, 0x03. -**/ - UINT8 PcieRpClkReqNumber[6]; - -/** Offset 0x0122 - CLKREQ# Detection - Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. -**/ - UINT8 PcieRpClkReqDetect[6]; - -/** Offset 0x0128 - Advanced Error Reporting - Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. -**/ - UINT8 AdvancedErrorReporting[6]; - -/** Offset 0x012E - PME Interrupt - Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. -**/ - UINT8 PmeInterrupt[6]; - -/** Offset 0x0134 - URR - PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 UnsupportedRequestReport[6]; - -/** Offset 0x013A - FER - PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 FatalErrorReport[6]; - -/** Offset 0x0140 - NFER - PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 NoFatalErrorReport[6]; - -/** Offset 0x0146 - CER - PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 CorrectableErrorReport[6]; - -/** Offset 0x014C - SEFE - Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnFatalError[6]; - -/** Offset 0x0152 - SENFE - Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnNonFatalError[6]; - -/** Offset 0x0158 - SECE - Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnCorrectableError[6]; - -/** Offset 0x015E - PCIe Speed - Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. -**/ - UINT8 PcieRpSpeed[6]; - -/** Offset 0x0164 - Physical Slot Number - Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. -**/ - UINT8 PhysicalSlotNumber[6]; - -/** Offset 0x016A - CTO - Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpCompletionTimeout[6]; - -/** Offset 0x0170 - PTM Support - Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. -**/ - UINT8 PtmEnable[6]; - -/** Offset 0x0176 - ASPM - PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, - 4:Auto(Default). -**/ - UINT8 PcieRpAspm[6]; - -/** Offset 0x017C - L1 Substates - PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). -**/ - UINT8 PcieRpL1Substates[6]; - -/** Offset 0x0182 - PCH PCIe LTR - PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpLtrEnable[6]; - -/** Offset 0x0188 - PCIE LTR Lock - PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpLtrConfigLock[6]; - -/** Offset 0x018E - PME_B0_S5 Disable bit - PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmeB0S5Dis; - -/** Offset 0x018F - PCI Clock Run - This member describes whether or not the PCI ClockRun feature of SC should be enabled. - 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PciClockRun; - -/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Timer8254ClkSetting; - -/** Offset 0x0191 - Chipset SATA - Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports - the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableSata; - -/** Offset 0x0192 - SATA Mode Selection - Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0193 - Aggressive LPM Support - Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0194 - SATA Power Optimization - Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0195 - eSATA Speed Limit - Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 eSATASpeedLimit; - -/** Offset 0x0196 - SATA Speed Limit - SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). - 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) -**/ - UINT8 SpeedLimit; - -/** Offset 0x0197 -**/ - UINT8 UnusedUpdSpace2[1]; - -/** Offset 0x0198 - SATA Port - Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsEnable[2]; - -/** Offset 0x019A - SATA Port DevSlp - Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsDevSlp[2]; - -/** Offset 0x019C - SATA Port HotPlug - Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsHotPlug[2]; - -/** Offset 0x019E - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\n - Note:Requires hardware support. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsInterlockSw[2]; - -/** Offset 0x01A0 - External SATA Ports - Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsExternal[2]; - -/** Offset 0x01A2 - Spin Up Device - Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsSpinUp[2]; - -/** Offset 0x01A4 - SATA Solid State - Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard - Disk Drive(Default), 1:Solid State Drive. -**/ - UINT8 SataPortsSolidStateDrive[2]; - -/** Offset 0x01A6 - DITO Configuration - Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsEnableDitoConfig[2]; - -/** Offset 0x01A8 - DM Value - DM Value. 0:Minimum, 0x0F:Maximum(Default). -**/ - UINT8 SataPortsDmVal[2]; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace3[2]; - -/** Offset 0x01AC - DITO Value - DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). -**/ - UINT16 SataPortsDitoVal[2]; - -/** Offset 0x01B0 - Subsystem Vendor ID - Subsystem Vendor ID. 0x8086(Default). -**/ - UINT16 SubSystemVendorId; - -/** Offset 0x01B2 - Subsystem ID - Subsystem ID. 0x7270(Default). -**/ - UINT16 SubSystemId; - -/** Offset 0x01B4 - CRIDSettings - PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. -**/ - UINT8 CRIDSettings; - -/** Offset 0x01B5 - ResetSelect - ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. -**/ - UINT8 ResetSelect; - -/** Offset 0x01B6 - SD Card Support (D27:F0) - Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdcardEnabled; - -/** Offset 0x01B7 - SeMMC Support (D28:F0) - Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 eMMCEnabled; - -/** Offset 0x01B8 - eMMC Max Speed - Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. - 0:HS400, 1: HS200, 2:DDR50 -**/ - UINT8 eMMCHostMaxSpeed; - -/** Offset 0x01B9 - UFS Support (D29:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 UfsEnabled; - -/** Offset 0x01BA - SDIO Support (D30:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdioEnabled; - -/** Offset 0x01BB - GPP Lock Feature - Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GppLock; - -/** Offset 0x01BC - Serial IRQ - Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SirqEnable; - -/** Offset 0x01BD - Serial IRQ Mode - Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. - $EN_DIS -**/ - UINT8 SirqMode; - -/** Offset 0x01BE - Start Frame Pulse Width - Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk -**/ - UINT8 StartFramePulse; - -/** Offset 0x01BF - Enable SMBus - Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x01C0 - SMBus ARP Support - Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ArpEnable; - -/** Offset 0x01C1 -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x01C2 - SMBus Table Elements - The number of elements in the Reserved SMBus Address Table. 0x0080(Default). -**/ - UINT16 NumRsvdSmbusAddresses; - -/** Offset 0x01C4 - Reserved SMBus Address Table - Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). -**/ - UINT8 RsvdSmbusAddressTable[128]; - -/** Offset 0x0244 - XHCI Disable Compliance Mode - Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance - Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. - $EN_DIS -**/ - UINT8 DisableComplianceMode; - -/** Offset 0x0245 - USB Per-Port Control - Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UsbPerPortCtl; - -/** Offset 0x0246 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Usb30Mode; - -/** Offset 0x0247 -**/ - UINT8 UnusedUpdSpace5[1]; - -/** Offset 0x0248 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb20Enable[8]; - -/** Offset 0x0250 - USB20 Over Current Pin - Over Current Pin number of USB 2.0 Port. 0x00(Default). -**/ - UINT8 PortUs20bOverCurrentPin[8]; - -/** Offset 0x0258 - XDCI Support - Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - 0:Disable, 1:PCI_Mode, 2:ACPI_mode -**/ - UINT8 UsbOtg; - -/** Offset 0x0259 - Enable XHCI HSIC Support - Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HsicSupportEnable; - -/** Offset 0x025A - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb30Enable[6]; - -/** Offset 0x0260 - USB20 Over Current Pin - Over Current Pin number of USB 3.0 Port. 0x01(Default). -**/ - UINT8 PortUs30bOverCurrentPin[6]; - -/** Offset 0x0266 - Enable XHCI SSIC Support - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for - port1. 0x00(Default). -**/ - UINT8 SsicPortEnable[2]; - -/** Offset 0x0268 - SSIC Dlane PowerGating - Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT16 DlanePwrGating; - -/** Offset 0x026A - VT-d - Enable/Disable VT-d. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 VtdEnable; - -/** Offset 0x026B - SMI Lock bit - Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, - 1:Enable(Default). - $EN_DIS -**/ - UINT8 LockDownGlobalSmi; - -/** Offset 0x026C - HDAudio Delay Timer - The delay timer after Azalia reset. 0x012C(Default). -**/ - UINT16 ResetWaitTimer; - -/** Offset 0x026E - RTC Lock Bits - Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 RtcLock; - -/** Offset 0x026F - SATA Test Mode Selection - Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0270 - XHCI SSIC RATE - Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. -**/ - UINT8 SsicRate[2]; - -/** Offset 0x0272 - SMBus Dynamic Power Gating - Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT16 DynamicPowerGating; - -/** Offset 0x0274 - Max Snoop Latency - Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxSnoopLatency[6]; - -/** Offset 0x0280 - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[6]; - -/** Offset 0x0286 -**/ - UINT8 UnusedUpdSpace6[2]; - -/** Offset 0x0288 - Snoop Latency Value - LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[6]; - -/** Offset 0x0294 - Snoop Latency Multiplier - LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, - 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x029A - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x029B - DCI Auto Detect - Deprecated: Enable/disable DCI AUTO mode. Enabled(Default). - $EN_DIS -**/ - UINT8 DciAutoDetect; - -/** Offset 0x029C - Max Non-Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxNonSnoopLatency[6]; - -/** Offset 0x02A8 - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; - -/** Offset 0x02AE - Halt and Lock TCO Timer - Halt and Lock the TCO Timer (Watchdog). - 0:No, 1:Yes (default) -**/ - UINT8 TcoTimerHaltLock; - -/** Offset 0x02AF - Power Button Override Period - specifies how long will PMC wait before initiating a global reset. 000b-4s(default), - 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) - 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s -**/ - UINT8 PwrBtnOverridePeriod; - -/** Offset 0x02B0 - Non Snoop Latency Value - LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; - -/** Offset 0x02BC - Non Snoop Latency Multiplier - LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), - 3:32768ns, 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale - Specifies scale used for slot power limit value. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitScale[6]; - -/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value - Specifies upper limit on power supplie by slot. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitValue[6]; - -/** Offset 0x02CE - Power Button Native Mode Disable - Disable power button native mode, when 1, this will result in the PMC logic constantly - seeing the power button as de-asserted. 0 (default)) - $EN_DIS -**/ - UINT8 DisableNativePowerButton; - -/** Offset 0x02CF - Power Button Debounce Mode - Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) - $EN_DIS -**/ - UINT8 PowerButterDebounceMode; - -/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL - SDIO_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdioTxCmdCntl; - -/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1 - SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). -**/ - UINT32 SdioTxDataCntl1; - -/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2 - SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). -**/ - UINT32 SdioTxDataCntl2; - -/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1 - SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). -**/ - UINT32 SdioRxCmdDataCntl1; - -/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2 - SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdioRxCmdDataCntl2; - -/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL - SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdcardTxCmdCntl; - -/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1 - SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). -**/ - UINT32 SdcardTxDataCntl1; - -/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2 - SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). -**/ - UINT32 SdcardTxDataCntl2; - -/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1 - SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). -**/ - UINT32 SdcardRxCmdDataCntl1; - -/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL - SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). -**/ - UINT32 SdcardRxStrobeCntl; - -/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2 - SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdcardRxCmdDataCntl2; - -/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL - EMMC_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 EmmcTxCmdCntl; - -/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1 - EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). -**/ - UINT32 EmmcTxDataCntl1; - -/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2 - EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). -**/ - UINT32 EmmcTxDataCntl2; - -/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1 - EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). -**/ - UINT32 EmmcRxCmdDataCntl1; - -/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL - EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). -**/ - UINT32 EmmcRxStrobeCntl; - -/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2 - EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). -**/ - UINT32 EmmcRxCmdDataCntl2; - -/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL - EMMC_MASTER_DLL_CNTL. 0x001(Default). -**/ - UINT32 EmmcMasterSwCntl; - -/** Offset 0x0318 - PCIe Selectable De-emphasis - When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis - for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSelectableDeemphasis[6]; - -/** Offset 0x031E - Monitor Mwait Enable - Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux - based OS, this should be Disabled. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 HdAudioDspUaaCompliance; - -/** Offset 0x0320 - IRQ Interrupt Polarity Control - Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low -**/ - UINT32 IPC[4]; - -/** Offset 0x0330 - Disable ModPHY dynamic power gate - Disable ModPHY dynamic power gate for the specific SATA port. -**/ - UINT8 SataPortsDisableDynamicPg[2]; - -/** Offset 0x0332 - Init CPU during S3 resume - 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume. - $EN_DIS -**/ - UINT8 InitS3Cpu; - -/** Offset 0x0333 - Skip P-unit Initialization - When this is skipped, boot loader must initialize P-unit before SilicionInit API. - 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipPunitInit; - -/** Offset 0x0334 -**/ - UINT8 UnusedUpdSpace7[4]; - -/** Offset 0x0338 - PerPort Half Bit Pre-emphasis - PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14] -**/ - UINT8 PortUsb20PerPortTxPeHalf[8]; - -/** Offset 0x0340 - PerPort HS Pre-emphasis Bias - PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11] -**/ - UINT8 PortUsb20PerPortPeTxiSet[8]; - -/** Offset 0x0348 - PerPort HS Transmitter Bias - PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8] -**/ - UINT8 PortUsb20PerPortTxiSet[8]; - -/** Offset 0x0350 - Select the skew direction for HS transition - Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25] -**/ - UINT8 PortUsb20HsSkewSel[8]; - -/** Offset 0x0358 - Per Port HS Transmitter Emphasis - Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23] -**/ - UINT8 PortUsb20IUsbTxEmphasisEn[8]; - -/** Offset 0x0360 - PerPort HS Receiver Bias - PerPort HS Receiver Bias. Value of register USB2_PER_PORT_PPX [19:17] -**/ - UINT8 PortUsb20PerPortRXISet[8]; - -/** Offset 0x0368 - Delay/skew's strength control for HS driver - Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0] -**/ - UINT8 PortUsb20HsNpreDrvSel[8]; - -/** Offset 0x0370 - OS Selection - Windows or Android or Linux OS selection to be used by HDA, USB Common, PWM and - PEI Graphics modules. Windows (default), Android, Linux - 0x0:Windows, 0x1:Android, 0x3:Linux -**/ - UINT8 OsSelection; - -/** Offset 0x0371 - DPTF - Intel® Dynamic Platform and Thermal Framework. 0x0:Disabled (default), 0x1:Enabled - $EN_DIS -**/ - UINT8 DptfEnabled; - -/** Offset 0x0372 - PWM Enabled - PWM Device Enabling. Windows needs this to be disabled, while Android needs this - to be enabled. 0x0:Disabled (default), 0x1:Enabled - $EN_DIS -**/ - UINT8 PWMEnabled; - -/** Offset 0x0373 -**/ - UINT8 ReservedFspsUpd[13]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0380 -**/ - UINT8 UnusedUpdSpace8[46]; - -/** Offset 0x03AE -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/ApolloLakeFspBinPkg/Include/FsptUpd.h b/ApolloLakeFspBinPkg/Include/FsptUpd.h deleted file mode 100644 index afe8ec9..0000000 --- a/ApolloLakeFspBinPkg/Include/FsptUpd.h +++ /dev/null @@ -1,101 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Common UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT8 Revision; - -/** Offset 0x0021 -**/ - UINT8 Reserved[3]; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0028 -**/ - UINT32 MicrocodeRegionLength; - -/** Offset 0x002C -**/ - UINT32 CodeRegionBase; - -/** Offset 0x0030 -**/ - UINT32 CodeRegionLength; - -/** Offset 0x0034 -**/ - UINT8 Reserved1[12]; -} FSPT_COMMON_UPD; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_COMMON_UPD FsptCommonUpd; - -/** Offset 0x0040 -**/ - UINT8 ReservedFsptUpd1[16]; - -/** Offset 0x0050 -**/ - UINT8 UnusedUpdSpace0[6]; - -/** Offset 0x0056 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/ApolloLakeFspBinPkg/Include/GpioSampleDef.h b/ApolloLakeFspBinPkg/Include/GpioSampleDef.h deleted file mode 100644 index ddce547..0000000 --- a/ApolloLakeFspBinPkg/Include/GpioSampleDef.h +++ /dev/null @@ -1,579 +0,0 @@ -/** @file - -Copyright (c) 2015, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __GPIOCONFIG_H__ -#define __GPIOCONFIG_H__ -#include - -/* For any GpioPad usage in code use GPIO_PAD type*/ -typedef u32 GPIO_PAD; - -/* For any GpioGroup usage in code use GPIO_GROUP type */ -typedef u32 GPIO_GROUP; - -/* - GPIO configuration structure used for pin programming. - Structure contains fields that can be used to configure pad. -*/ -typedef struct { - /* - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction, OutputState, Interrupt is unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - */ - u32 PadMode : 3; - /* - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - */ - u32 HostSoftPadOwn : 2; - /* - GPIO Direction - Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d -isabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - */ - u32 Direction : 5; - /* - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - */ - u32 OutputState : 2; - /* - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO -is in input mode. - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Refer to definition of GPIO_INT_CONFIG for supported settings. - */ - u32 InterruptConfig : 8; - /* - GPIO Power Configuration. - This setting controls Pad Reset Configuration and Power Rail Type. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - */ - u32 PowerConfig : 5; - /* - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - */ - u32 ElectricalConfig : 7; - /* - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - */ - u32 LockConfig : 3; - /* - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - */ - u32 OtherSettings : 2; - u32 RsvdBits : 27; -} GPIO_CONFIG; - -typedef struct { - GPIO_PAD GpioPad; - GPIO_CONFIG GpioConfig; -} GPIO_INIT_CONFIG; - -typedef enum { - GpioHardwareDefault = 0x0 -} GPIO_HARDWARE_DEFAULT; - -/* GPIO Pad Mode */ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7 -} GPIO_PAD_MODE; - - -/* Host Software Pad Ownership modes */ -typedef enum { - GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ - GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ - GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ -} GPIO_HOSTSW_OWN; - -/* GPIO Direction */ -typedef enum { - GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ - GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ - GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ - GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ - GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ - GpioDirOut = 0x5, /* Set pad for output only */ - GpioDirNone = 0x7 /* Disable both output and input */ -} GPIO_DIRECTION; - -/* GPIO Output State */ -typedef enum { - GpioOutDefault = 0x0, - GpioOutLow = 0x1, - GpioOutHigh = 0x3 -} GPIO_OUTPUT_STATE; - -/* - GPIO interrupt configuration - This setting is applicable only if GPIO is in input mode. - GPIO_INT_CONFIG allows to choose which interrupt is generted - (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). - Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to - GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Not all GPIO are capable of generating an SMI or NMI interrupt -*/ -typedef enum { - GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ - GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ - GpioIntNmi = 0x3, /* Enable NMI interrupt only */ - GpioIntSmi = 0x5, /* Enable SMI interrupt only */ - GpioIntSci = 0x9, /* Enable SCI interrupt only */ - GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ - GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ - GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ - GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ - GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ -} GPIO_INT_CONFIG; - -/* - GPIO Power Configuration - GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified - Pad Register fields). -*/ -typedef enum { - GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ - GpioResetPwrGood = 0x1, /* Powergood reset */ - GpioResetDeep = 0x3, /* Deep GPIO Reset */ - GpioResetNormal = 0x5, /* GPIO Reset */ - GpioResetResume = 0x7 /* Resume Reset */ -} GPIO_RESET_CONFIG; - -/* - GPIO Electrical Configuration - Set GPIO termination and Pad Tolerance (applicable only for some pads) - Field from GpioTermDefault to GpioTermNative can be OR'ed with - GpioTolerance1v8. -*/ -typedef enum { - GpioTermDefault = 0x0, /* Leave termination setting unmodified */ - GpioTermNone = 0x1, /* none */ - GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ - GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ - GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ - GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ - GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ - GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ - GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ - GpioTermNative = 0x1F, /* Native function for pads termination */ - GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ - GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ -} GPIO_ELECTRICAL_CONFIG; - -/* - GPIO LockConfiguration - Set GPIO configuration lock and output state lock - GpioLockPadConfig and GpioLockOutputState can be OR'ed -*/ -typedef enum { - GpioLockDefault = 0x0, /* Leave lock setting unmodified */ - GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ - GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ -} GPIO_LOCK_CONFIG; - -/* - Other GPIO Configuration - GPIO_OTHER_CONFIG is used for less often settings and for future extensions - Supported settings: - - RX raw override to '1' - allows to override input value to '1' - This is applicable only if in input mode (both in GPIO and native usage) - The override takes place at the internal pad state directly from buffer - and before the RXINV. -*/ -typedef enum { - GpioRxRaw1Default = 0x0, /* Use default input override value */ - GpioRxRaw1Dis = 0x1, /* Don't override input */ - GpioRxRaw1En = 0x3 /* Override input to '1' */ -} GPIO_OTHER_CONFIG; - -/* - SKL LP GPIO pins - Use below for functions from PCH GPIO Lib which - require GpioPad as argument. Encoding used here - has all information required by library functions -*/ -#define GPIO_SKL_LP_GPP_A0 0x02000000 -#define GPIO_SKL_LP_GPP_A1 0x02000001 -#define GPIO_SKL_LP_GPP_A2 0x02000002 -#define GPIO_SKL_LP_GPP_A3 0x02000003 -#define GPIO_SKL_LP_GPP_A4 0x02000004 -#define GPIO_SKL_LP_GPP_A5 0x02000005 -#define GPIO_SKL_LP_GPP_A6 0x02000006 -#define GPIO_SKL_LP_GPP_A7 0x02000007 -#define GPIO_SKL_LP_GPP_A8 0x02000008 -#define GPIO_SKL_LP_GPP_A9 0x02000009 -#define GPIO_SKL_LP_GPP_A10 0x0200000A -#define GPIO_SKL_LP_GPP_A11 0x0200000B -#define GPIO_SKL_LP_GPP_A12 0x0200000C -#define GPIO_SKL_LP_GPP_A13 0x0200000D -#define GPIO_SKL_LP_GPP_A14 0x0200000E -#define GPIO_SKL_LP_GPP_A15 0x0200000F -#define GPIO_SKL_LP_GPP_A16 0x02000010 -#define GPIO_SKL_LP_GPP_A17 0x02000011 -#define GPIO_SKL_LP_GPP_A18 0x02000012 -#define GPIO_SKL_LP_GPP_A19 0x02000013 -#define GPIO_SKL_LP_GPP_A20 0x02000014 -#define GPIO_SKL_LP_GPP_A21 0x02000015 -#define GPIO_SKL_LP_GPP_A22 0x02000016 -#define GPIO_SKL_LP_GPP_A23 0x02000017 -#define GPIO_SKL_LP_GPP_B0 0x02010000 -#define GPIO_SKL_LP_GPP_B1 0x02010001 -#define GPIO_SKL_LP_GPP_B2 0x02010002 -#define GPIO_SKL_LP_GPP_B3 0x02010003 -#define GPIO_SKL_LP_GPP_B4 0x02010004 -#define GPIO_SKL_LP_GPP_B5 0x02010005 -#define GPIO_SKL_LP_GPP_B6 0x02010006 -#define GPIO_SKL_LP_GPP_B7 0x02010007 -#define GPIO_SKL_LP_GPP_B8 0x02010008 -#define GPIO_SKL_LP_GPP_B9 0x02010009 -#define GPIO_SKL_LP_GPP_B10 0x0201000A -#define GPIO_SKL_LP_GPP_B11 0x0201000B -#define GPIO_SKL_LP_GPP_B12 0x0201000C -#define GPIO_SKL_LP_GPP_B13 0x0201000D -#define GPIO_SKL_LP_GPP_B14 0x0201000E -#define GPIO_SKL_LP_GPP_B15 0x0201000F -#define GPIO_SKL_LP_GPP_B16 0x02010010 -#define GPIO_SKL_LP_GPP_B17 0x02010011 -#define GPIO_SKL_LP_GPP_B18 0x02010012 -#define GPIO_SKL_LP_GPP_B19 0x02010013 -#define GPIO_SKL_LP_GPP_B20 0x02010014 -#define GPIO_SKL_LP_GPP_B21 0x02010015 -#define GPIO_SKL_LP_GPP_B22 0x02010016 -#define GPIO_SKL_LP_GPP_B23 0x02010017 -#define GPIO_SKL_LP_GPP_C0 0x02020000 -#define GPIO_SKL_LP_GPP_C1 0x02020001 -#define GPIO_SKL_LP_GPP_C2 0x02020002 -#define GPIO_SKL_LP_GPP_C3 0x02020003 -#define GPIO_SKL_LP_GPP_C4 0x02020004 -#define GPIO_SKL_LP_GPP_C5 0x02020005 -#define GPIO_SKL_LP_GPP_C6 0x02020006 -#define GPIO_SKL_LP_GPP_C7 0x02020007 -#define GPIO_SKL_LP_GPP_C8 0x02020008 -#define GPIO_SKL_LP_GPP_C9 0x02020009 -#define GPIO_SKL_LP_GPP_C10 0x0202000A -#define GPIO_SKL_LP_GPP_C11 0x0202000B -#define GPIO_SKL_LP_GPP_C12 0x0202000C -#define GPIO_SKL_LP_GPP_C13 0x0202000D -#define GPIO_SKL_LP_GPP_C14 0x0202000E -#define GPIO_SKL_LP_GPP_C15 0x0202000F -#define GPIO_SKL_LP_GPP_C16 0x02020010 -#define GPIO_SKL_LP_GPP_C17 0x02020011 -#define GPIO_SKL_LP_GPP_C18 0x02020012 -#define GPIO_SKL_LP_GPP_C19 0x02020013 -#define GPIO_SKL_LP_GPP_C20 0x02020014 -#define GPIO_SKL_LP_GPP_C21 0x02020015 -#define GPIO_SKL_LP_GPP_C22 0x02020016 -#define GPIO_SKL_LP_GPP_C23 0x02020017 -#define GPIO_SKL_LP_GPP_D0 0x02030000 -#define GPIO_SKL_LP_GPP_D1 0x02030001 -#define GPIO_SKL_LP_GPP_D2 0x02030002 -#define GPIO_SKL_LP_GPP_D3 0x02030003 -#define GPIO_SKL_LP_GPP_D4 0x02030004 -#define GPIO_SKL_LP_GPP_D5 0x02030005 -#define GPIO_SKL_LP_GPP_D6 0x02030006 -#define GPIO_SKL_LP_GPP_D7 0x02030007 -#define GPIO_SKL_LP_GPP_D8 0x02030008 -#define GPIO_SKL_LP_GPP_D9 0x02030009 -#define GPIO_SKL_LP_GPP_D10 0x0203000A -#define GPIO_SKL_LP_GPP_D11 0x0203000B -#define GPIO_SKL_LP_GPP_D12 0x0203000C -#define GPIO_SKL_LP_GPP_D13 0x0203000D -#define GPIO_SKL_LP_GPP_D14 0x0203000E -#define GPIO_SKL_LP_GPP_D15 0x0203000F -#define GPIO_SKL_LP_GPP_D16 0x02030010 -#define GPIO_SKL_LP_GPP_D17 0x02030011 -#define GPIO_SKL_LP_GPP_D18 0x02030012 -#define GPIO_SKL_LP_GPP_D19 0x02030013 -#define GPIO_SKL_LP_GPP_D20 0x02030014 -#define GPIO_SKL_LP_GPP_D21 0x02030015 -#define GPIO_SKL_LP_GPP_D22 0x02030016 -#define GPIO_SKL_LP_GPP_D23 0x02030017 -#define GPIO_SKL_LP_GPP_E0 0x02040000 -#define GPIO_SKL_LP_GPP_E1 0x02040001 -#define GPIO_SKL_LP_GPP_E2 0x02040002 -#define GPIO_SKL_LP_GPP_E3 0x02040003 -#define GPIO_SKL_LP_GPP_E4 0x02040004 -#define GPIO_SKL_LP_GPP_E5 0x02040005 -#define GPIO_SKL_LP_GPP_E6 0x02040006 -#define GPIO_SKL_LP_GPP_E7 0x02040007 -#define GPIO_SKL_LP_GPP_E8 0x02040008 -#define GPIO_SKL_LP_GPP_E9 0x02040009 -#define GPIO_SKL_LP_GPP_E10 0x0204000A -#define GPIO_SKL_LP_GPP_E11 0x0204000B -#define GPIO_SKL_LP_GPP_E12 0x0204000C -#define GPIO_SKL_LP_GPP_E13 0x0204000D -#define GPIO_SKL_LP_GPP_E14 0x0204000E -#define GPIO_SKL_LP_GPP_E15 0x0204000F -#define GPIO_SKL_LP_GPP_E16 0x02040010 -#define GPIO_SKL_LP_GPP_E17 0x02040011 -#define GPIO_SKL_LP_GPP_E18 0x02040012 -#define GPIO_SKL_LP_GPP_E19 0x02040013 -#define GPIO_SKL_LP_GPP_E20 0x02040014 -#define GPIO_SKL_LP_GPP_E21 0x02040015 -#define GPIO_SKL_LP_GPP_E22 0x02040016 -#define GPIO_SKL_LP_GPP_E23 0x02040017 -#define GPIO_SKL_LP_GPP_F0 0x02050000 -#define GPIO_SKL_LP_GPP_F1 0x02050001 -#define GPIO_SKL_LP_GPP_F2 0x02050002 -#define GPIO_SKL_LP_GPP_F3 0x02050003 -#define GPIO_SKL_LP_GPP_F4 0x02050004 -#define GPIO_SKL_LP_GPP_F5 0x02050005 -#define GPIO_SKL_LP_GPP_F6 0x02050006 -#define GPIO_SKL_LP_GPP_F7 0x02050007 -#define GPIO_SKL_LP_GPP_F8 0x02050008 -#define GPIO_SKL_LP_GPP_F9 0x02050009 -#define GPIO_SKL_LP_GPP_F10 0x0205000A -#define GPIO_SKL_LP_GPP_F11 0x0205000B -#define GPIO_SKL_LP_GPP_F12 0x0205000C -#define GPIO_SKL_LP_GPP_F13 0x0205000D -#define GPIO_SKL_LP_GPP_F14 0x0205000E -#define GPIO_SKL_LP_GPP_F15 0x0205000F -#define GPIO_SKL_LP_GPP_F16 0x02050010 -#define GPIO_SKL_LP_GPP_F17 0x02050011 -#define GPIO_SKL_LP_GPP_F18 0x02050012 -#define GPIO_SKL_LP_GPP_F19 0x02050013 -#define GPIO_SKL_LP_GPP_F20 0x02050014 -#define GPIO_SKL_LP_GPP_F21 0x02050015 -#define GPIO_SKL_LP_GPP_F22 0x02050016 -#define GPIO_SKL_LP_GPP_F23 0x02050017 -#define GPIO_SKL_LP_GPP_G0 0x02060000 -#define GPIO_SKL_LP_GPP_G1 0x02060001 -#define GPIO_SKL_LP_GPP_G2 0x02060002 -#define GPIO_SKL_LP_GPP_G3 0x02060003 -#define GPIO_SKL_LP_GPP_G4 0x02060004 -#define GPIO_SKL_LP_GPP_G5 0x02060005 -#define GPIO_SKL_LP_GPP_G6 0x02060006 -#define GPIO_SKL_LP_GPP_G7 0x02060007 -#define GPIO_SKL_LP_GPD0 0x02070000 -#define GPIO_SKL_LP_GPD1 0x02070001 -#define GPIO_SKL_LP_GPD2 0x02070002 -#define GPIO_SKL_LP_GPD3 0x02070003 -#define GPIO_SKL_LP_GPD4 0x02070004 -#define GPIO_SKL_LP_GPD5 0x02070005 -#define GPIO_SKL_LP_GPD6 0x02070006 -#define GPIO_SKL_LP_GPD7 0x02070007 -#define GPIO_SKL_LP_GPD8 0x02070008 -#define GPIO_SKL_LP_GPD9 0x02070009 -#define GPIO_SKL_LP_GPD10 0x0207000A -#define GPIO_SKL_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -//Sample GPIO Table - -static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = -{ -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//INT_SERIRQ -//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_SLP_S0ix_R_N - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N - {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_PWR_EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//GNSS_CHUB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//FPS_SLP_N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//V0.85A_VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//V0.85A_VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//GP_VRALERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetNormal, GpioTermNone}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//BT_RF_KILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//MPHY_EXT_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_SLP_S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PLT_RST_N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//TCH_PNL_PWREN - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_DFU - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioResetDeep, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//FPS_GSPI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SMB_DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML0_CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML0_DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML1_CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SML1_DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CSI2_FLASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_CLK_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_CLK_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP_MCLK - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioResetDeep, GpioTermNone}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA_ODD_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioResetDeep, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//EINK_SSR_DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_SATA_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_IRQ - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI1_HPD_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI2_HPD_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioResetDeep, GpioTermNone}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI1_CTRL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DDI1_CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI2_CTRL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DDI2_CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//TCH_PNL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_SCLK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_SFRM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_TXD - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_RXD - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_CMD - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_RCLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_CLK - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetPwrGood, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermWpu20K}},//PM_PWRBTN_R_N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PCH_SLP_WLAN_N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PM_LANPHY_ENABLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//Marking End of Table -}; - -#endif //_GPIO_CONFIG_H_ diff --git a/ApolloLakeFspBinPkg/Include/for_coreboot_MR4.zip b/ApolloLakeFspBinPkg/Include/for_coreboot_MR4.zip deleted file mode 100644 index 24494245b68977da09d9cd494df66b6a70ce6ae6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 28625 zcmZ^~W2`tn&?b6p+qP}nwr$(C&+pi_ZQHhO+xvfaH#fP-z5UR3CNu3cX*+qQQw3>Y z5EOv_DKF_#^8dT@e=EfQS~GhmePeqkQzLtO7kybJ7J7yMD-HqBq0KGdf8qdcKm-6# zoecnh_5UR<=Imgr>R>`=aii<$OeKo&w@1}CjQ_;ekW|i3Jzvp}h=-rU8oP zK0u=7=kCA5+XQZd)E!S0pVp7V>nrOnKUe=Wt8HHqPjed9G%T{(Lel?6KK4m9?+fN8$RedjAc;5EAryV~pBRnR)A z7q>#@kldvb*!Ca}m$uz0z2&cfJf{zW>3UXcKKb-f*QQw&%I-#f8v#Dm{r&HT+v?;U z+P%kZ)at~Wztgx|bMBhek28QN&)fahsZwm$=~}5yK(Q>esTM)Xz5;@>;)M(g+Xb`e zfJ`I!U&{?0W})xZPef$`rnLP{TsF+*_Wns)awagwK*T6i|z4K+!-XYB`aW)p!D`o4KmwXZF22D$_~8C3p(-F~u2ZV93P8TR2TgZNQ3&ff7g!K~ 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a/ApolloLakeFspBinPkg/Vbt/Vbt.bsf +++ /dev/null @@ -1,11676 +0,0 @@ -; TITLE BMP.bsf - BMP Script File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2015). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ -StructDef - -Find "BIOS_DATA_BLOCK " - -; The following block will determine the reference -; pointer for all table pointer variables. -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 25 - Skylake - -SKIP 2 bits ; Obsolete -$Integrated_EFP 1 bit ; Integrated EFP Support: -$eDP 1 bit ; eDP: -SKIP 4 bits -ALIGN - -SKIP 4 bytes ; Skip build number string - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - -; General Byte Definitions -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Pop-up Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -; bmp_Allow_Config -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; bmp_Bits_1 -SKIP 1 byte ; Skip bmp_bits_1 completely. -ALIGN - -; bmp_Bits_2 -$Kvmr_Session_Enable 1 bit ; KVMR session enable/boot to fake DVI Display feature -SKIP 5 bits -$bmp_Dynamic_CdClock_Supported 1 bit ; Enable/Disable Dynamic CD Clock select -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS -ALIGN - -; bmp_Bits_3 -SKIP 2 bits ; Skip 2 bits -$180_Deg_Rotation_Enable 1 bit ; 180 degree rotation enable for LFP in GOP driver. -SKIP 5 bits ; Skip remaining bits. -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Reserved/Obsolete -SKIP 7 bits -ALIGN - -; Int_Displays_Support -SKIP 3 bits -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -SKIP 1 bit ; Obsolete/Reserved from BXT -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits ; Reserved -ALIGN - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte ; Displays attached field is relevant in VBIOS only -$ChildDevice1Primary 1 byte ; Primary -$ChildDevice1Secondary 1 byte ; Secondary -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; bmp_DDC_GPIO_Pins -SKIP 1 byte ; Obsolete: Was used for CRT DDC GMBUS pin pair - -; bmp_DPMS_Bits -SKIP 1 byte ; Skip bmp_dpms_bits completely. - -; bmp_Boot_Dev_Bits -SKIP 2 bytes ; Skip Boot display type - -$size_ChildStruc 1 byte - -; LFP Child Structure -SKIP 2 bytes ; Skip Device Handle -$LFP_Device_Class 2 bytes ; Device class -SKIP 6 bytes ; Skip till Flags 0 field -SKIP 1 bit ; Skip EDID less enable bit used for EFP's -$Int_LFP_Compression_Enable 1 bit ; Compression enable bit -$Int_LFP_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$Int_LFP_Dual_Pipe_Ganged_Enable 1 bit ; Dual pipe ganged support enable bit for LFP -SKIP 4 bits ; Skip remaining bits of Flags 0 -ALIGN - -$Int_LFP_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Skip remaining bits -ALIGN - -SKIP 4 bytes ; Skip reserved_1 and add-in offset fields -$LFP_Port 1 byte ; eDP port select -SKIP 6 bytes ; Skip remaining Data structure -SKIP 1 bit -$LFP_Lane_Reversal 1 bit ; Port Reversal -SKIP 1 bit ; LSPCON bit skipped for LFP -$LFP_IBoost_Enable 1 bit ; IBoost enable/disable for LFP. -$HPD1_Inversion_Enable 1 bit ; HPD inversion bit -SKIP 3 bits ; Reserved -SKIP 1 byte -$Int_LFP_AUX_Channel 1 byte ; eDP AUX channel -SKIP 11 bytes ; Skip remaining Data structure -$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level -SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct - -; Internal EFP (HDMI/DP) Data structure -; Device 1 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP1_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP1_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP1_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP1_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP1_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP1_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -$EFP1_Compression_Enable 1 bit ; Compression enable bit -$EFP1_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP1_Dual_Pipe_Ganged_Enable 1 bit ; EFP1 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP1_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -SKIP 2 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Skip Timing info pointer and DVO Config -$Int_EFP1_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP1_Lane_Reversal 1 bit ; Port Reversal -$LSPcon1_Options 1 bit ; Hdmi2.0 supported options -$Int_EFP1_IBoost_Enable 1 bit ; IBoost enable/disable bit -$HPD2_Inversion_Enable 1 bit ; HPD inversion bit -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP1_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -SKIP 7 bits ; Reserved -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level - -; Device 2 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP2_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP2_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP2_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP2_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP2_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP2_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -$EFP2_Compression_Enable 1 bit ; Compression enable bit -$EFP2_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP2_Dual_Pipe_Ganged_Enable 1 bit ; EFP2 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP2_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -SKIP 2 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP2_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP2_Lane_Reversal 1 bit ; Port Reversal -$LSPcon2_Options 1 bit ; Hdmi2.0 support options -$Int_EFP2_IBoost_Enable 1 bit ; IBoost enable/disable bit -$HPD3_Inversion_Enable 1 bit ; HPD inversion bit -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP2_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -SKIP 7 bits ; Reserved -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level - -; Device 3 -SKIP 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; I2C Speed -$Int_EFP3_OnBoard_Pre_emphasis 3 bits ; Set DisplayPort pre-emphasis level for onboard Redriver -$Int_EFP3_OnBoard_Voltage_swing 3 bits ; Set DisplayPort voltage swing level for onboard Redriver -$Int_EFP3_OnBoard_Redriver_Present 1 bit ; Set if onboard Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_Dock_Pre_emphasis 3 bits ; Set DisplayPort Redriver pre-emphasis level for dock Redriver -$Int_EFP3_Dock_Voltage_swing 3 bits ; Set DisplayPort Redriver voltage swing level for dock Redriver -$Int_EFP3_Dock_Redriver_Present 1 bit ; Set if dock Redriver is present -SKIP 1 bit ; Reserved -ALIGN -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -$Int_EFP3_HDMI_Maximum_Data_Rate 3 bits ; HDMI maximum data rate -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -$EFP3_Compression_Enable 1 bit ; Compression enable bit -$EFP3_Compression_Method_Select 1 bit ; Compression method select PPS/CPS -$EFP3_Dual_Pipe_Ganged_Enable 1 bit ; EFP3 dual pipe ganged display enable bit -SKIP 4 bits ; Skip remaining bits -ALIGN -$EFP3_Compression_Struct_Index 4 bits ; Compression structure index in Block 55 -SKIP 4 bits ; Reserved bits -ALIGN -SKIP 2 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip add-in module table offset -$Int_EFP3_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip I2C bus and slave address -$Int_EFP3_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes ; Timing info pointer and DVO Config -$Int_EFP3_Port_Dockable 1 bit ; HDMI/DP Docked Port -$EFP3_Lane_Reversal 1 bit ; Port Reversal -$EFP3_LSPcon_Options 1 bit ; Hdmi2.0 support options -$Int_EFP3_IBoost_Enable 1 bit ; IBoost enable/disable bit -$EFP3_HPD_Inversion_Enable 1 bit ; HPD inversion bit -SKIP 3 bits ; Reserved -ALIGN -SKIP 1 byte ; Obsolete: Was used for EFP compatibility field -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -SKIP 1 byte ; Obsolete: Was used for Dongle Detect -SKIP 6 bytes ; Skip to end of child structure -$EFP3_USB_C_DongleFeature_Enabled 1 bit ; USB type C dongle feature enabled -SKIP 7 bits ; Reserved -SKIP 3 bytes ; GPIO resource ID and GPIO number -$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level -$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level - -SKIP 38 bytes ; Skip device data structure -SKIP 38 bytes ; Skip device data structure -SKIP 38 bytes ; Skip device data structure -SKIP 38 bytes ; Skip device data structure - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Obsolete - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 18 bytes ; Skip 18 SBIOS hooks. - -; BMP - Pointer tables -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at Display Configurations Removal table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes ; Start of IO SWF Table -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes ; Start of MMIO SWF Table -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - -$Mode_Rem_Table_Ptr 2 bytes ; Start at Mode Removal table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -$Toggle_List1_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List1_Size 2 bytes -$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte - -$Toggle_List2_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List2_Size 2 bytes -$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte - -$Toggle_List3_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List3_Size 2 bytes -$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte - -$Toggle_List4_Ptr 2 bytes ; Start at BMP Boot table -$Toggle_List4_Size 2 bytes -$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte - -$eDP_Pwr_Seq_01_Ptr 2 bytes -$eDP_Pwr_Seq_01_Size 2 bytes -$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes -$eDP_Pwr_Seq_02_Ptr 2 bytes -$eDP_Pwr_Seq_02_Size 2 bytes -$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes -$eDP_Pwr_Seq_03_Ptr 2 bytes -$eDP_Pwr_Seq_03_Size 2 bytes -$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes -$eDP_Pwr_Seq_04_Ptr 2 bytes -$eDP_Pwr_Seq_04_Size 2 bytes -$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes -$eDP_Pwr_Seq_05_Ptr 2 bytes -$eDP_Pwr_Seq_05_Size 2 bytes -$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes -$eDP_Pwr_Seq_06_Ptr 2 bytes -$eDP_Pwr_Seq_06_Size 2 bytes -$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes -$eDP_Pwr_Seq_07_Ptr 2 bytes -$eDP_Pwr_Seq_07_Size 2 bytes -$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes -$eDP_Pwr_Seq_08_Ptr 2 bytes -$eDP_Pwr_Seq_08_Size 2 bytes -$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes -$eDP_Pwr_Seq_09_Ptr 2 bytes -$eDP_Pwr_Seq_09_Size 2 bytes -$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes -$eDP_Pwr_Seq_10_Ptr 2 bytes -$eDP_Pwr_Seq_10_Size 2 bytes -$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes -$eDP_Pwr_Seq_11_Ptr 2 bytes -$eDP_Pwr_Seq_11_Size 2 bytes -$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes -$eDP_Pwr_Seq_12_Ptr 2 bytes -$eDP_Pwr_Seq_12_Size 2 bytes -$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes -$eDP_Pwr_Seq_13_Ptr 2 bytes -$eDP_Pwr_Seq_13_Size 2 bytes -$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes -$eDP_Pwr_Seq_14_Ptr 2 bytes -$eDP_Pwr_Seq_14_Size 2 bytes -$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes -$eDP_Pwr_Seq_15_Ptr 2 bytes -$eDP_Pwr_Seq_15_Size 2 bytes -$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes -$eDP_Pwr_Seq_16_Ptr 2 bytes -$eDP_Pwr_Seq_16_Size 2 bytes -$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initialization -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 61 bytes ; Skip data - -;============================================================================== -; Block 9 - PSR/SRD feature control block -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 -$PSR_FullLink_Enable_01 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_01 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_01 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_01 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_01 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_01 2 bytes ; TP2/TP3 wake up time in multiples of 100 -ALIGN - -; Panel #02 -$PSR_FullLink_Enable_02 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_02 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_02 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_02 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_02 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_02 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #03 -$PSR_FullLink_Enable_03 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_03 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_03 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_03 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_03 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_03 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #04 -$PSR_FullLink_Enable_04 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_04 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_04 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_04 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_04 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_04 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #05 -$PSR_FullLink_Enable_05 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_05 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_05 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_05 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_05 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_05 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #06 -$PSR_FullLink_Enable_06 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_06 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_06 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_06 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_06 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_06 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #07 -$PSR_FullLink_Enable_07 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_07 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_07 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_07 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_07 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_07 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #08 -$PSR_FullLink_Enable_08 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_08 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_08 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_08 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_08 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_08 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #09 -$PSR_FullLink_Enable_09 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_09 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_09 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_09 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_09 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_09 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #10 -$PSR_FullLink_Enable_10 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_10 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_10 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_10 3 bits ; Lines to wait before link standby -SKIP 1 bit -ALIGN - -$PSR_TP1_WaitTime_10 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_10 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #11 -$PSR_FullLink_Enable_11 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_11 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_11 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_11 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_11 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_11 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #12 -$PSR_FullLink_Enable_12 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_12 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_12 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_12 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_12 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_12 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #13 -$PSR_FullLink_Enable_13 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_13 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_13 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_13 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_13 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_13 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #14 -$PSR_FullLink_Enable_14 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_14 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_14 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_14 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_14 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_14 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #15 -$PSR_FullLink_Enable_15 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_15 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_15 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_15 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_15 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_15 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -; Panel #16 -$PSR_FullLink_Enable_16 1 bit ; Full link disable -$PSR_Require_AUX2Wakeup_16 1 bit ; Require AUX to wake up -SKIP 6 bits ; Reserved -ALIGN - -$PSR_IdleFrames2Wait_16 4 bits ; Idle frames to wait for PSR enable -$PSR_Lines2Wait_B4LinkS3_16 3 bits ; Lines to wait before link standby -SKIP 1 bit ; Reserved -ALIGN - -$PSR_TP1_WaitTime_16 2 bytes ; TP1 wake up time in multiples of 100 -$PSR_TP_2_3_WaitTime_16 2 bytes ; TP2/TP3 wake up time in multiples of 100 - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 203 bytes ; Skip data - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit -SKIP 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Obsolete -$Hot_Plug_DVO 1 bit -SKIP 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit ; Obsolete -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; Obsolete -$Driver_Boot_Mode_Y 2 bytes ; Obsolete -$Driver_Boot_Mode_BPP 1 byte ; Obsolete -$Driver_Boot_Mode_RR 1 byte ; Obsolete - -; bmp_Ext_Driver_Bits_1 -$Enable_LFP_Primary 1 bit ; Obsolete -$GTF_Mode_Pruning 1 bit ; Obsolete -SKIP 4 bits -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; Obsolete -SKIP 1 bit ; Obsolete: Was used for CRT hot plug -$LVDS_Config 2 bits ; LVDS configuration -SKIP 1 bit ; Hot plug TV enable/disable -SKIP 2 bits ; Integrated HDMI Configuration -ALIGN - -; bmp_Driver_Flags_1 -$CUIHotK_Static_Display 1 bit -$Embedded_Platform 1 bit -$Disable_DisplayEnum 1 bit ; Used in RCR 2262110 -SKIP 5 bits -ALIGN - -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes - -; bmp_Ext2_Driver_Bits -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits ; Reserved -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number - -; bmp_Driver_Feature_Flags -$PM_RMPM_Enable 1 bit ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag. -$PM_S2DDT_Enable 1 bit ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag. -$PM_DPST_Enable 1 bit ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag. -$PM_BLC_Enable 1 bit ; Backlight Control (BLC) Enable/Disable Flag. -$PM_ADB_Enable 1 bit ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag. -$PM_DRRS_Enable 1 bit ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag. -$PM_RS_Enable 1 bit ; Graphics Render Standby (RS) Enable/Disable Flag. -$PM_GPMT_Enable 1 bit ; Obsolete -$PM_Turbo_Enable 1 bit ; Intel Turbo Boost Technology Enable/Disable Flag. -$Panel_Self_Refresh 1 bit ; Panel Self refresh feature (PSR) -$Inter_Pixel_Storage 1 bit ; Hidden feature. -$Dynamic_FPS_Enable 1 bit ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag. -$DMRRS 1 bit ; Dynamic media refresh rate enable/disable -$ADT 1 bit ; Assertive display technology enable/disable -$HPD_Wake 1 bit ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable -$PC_Fields_Enable 1 bit ; PC Feature field's validity Flag. -ALIGN - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 3 bytes ; Skip block data since it is obsolete. - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -SKIP 8 bytes ; Skip block data - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$Rot_Enable 1 bit ; Rotation Enable bit -SKIP 7 bits -SKIP 11 bytes ; Reserved - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID - -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV features -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip ID and size - -$Under_Over_Scan_Via_YPrPb 2 bits ; Obsolete -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Obsolete -$Add_Overscan_Mode 1 bit ; Obsolete -$D_Connector 1 bit ; Obsolete -ALIGN - -;============================================================================== -; Block 27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Panel #01 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - -; Panel #02 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - -; Panel #03 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - -; Panel #04 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - -; Panel #05 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - -; Panel #06 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - -; Panel #07 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - -; Panel #08 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - -; Panel #09 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - -; Panel #10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - -; Panel #11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - -; Panel #12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - -; Panel #13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - -; Panel #14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - -; Panel #15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - -; Panel #16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -$eDP_Link_DataRate_01 4 bits ; Panel #01 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #01 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #01 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #01 Link Voltage Swing - -$eDP_Link_DataRate_02 4 bits ; Panel #02 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #02 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #02 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #02 Link Voltage Swing - -$eDP_Link_DataRate_03 4 bits ; Panel #03 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #03 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #03 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #03 Link Voltage Swing - -$eDP_Link_DataRate_04 4 bits ; Panel #04 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #04 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #04 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #04 Link Voltage Swing - -$eDP_Link_DataRate_05 4 bits ; Panel #05 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #05 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #05 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #05 Link Voltage Swing - -$eDP_Link_DataRate_06 4 bits ; Panel #06 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #06 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #06 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #06 Link Voltage Swing - -$eDP_Link_DataRate_07 4 bits ; Panel #07 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #07 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #07 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #07 Link Voltage Swing - -$eDP_Link_DataRate_08 4 bits ; Panel #08 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #08 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #08 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #08 Link Voltage Swing - -$eDP_Link_DataRate_09 4 bits ; Panel #09 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #09 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #09 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #09 Link Voltage Swing - -$eDP_Link_DataRate_10 4 bits ; Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -$eDP_Link_DataRate_11 4 bits ; Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -$eDP_Link_DataRate_12 4 bits ; Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -$eDP_Link_DataRate_13 4 bits ; Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -$eDP_Link_DataRate_14 4 bits ; Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -$eDP_Link_DataRate_15 4 bits ; Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -$eDP_Link_DataRate_16 4 bits ; Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -SKIP 4 bytes ; Obsolete: Was used for DRRS MSA Delay. - -SKIP 2 bytes ; Obsolete: S3D enable disable VBT bit for 16 panels. - -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VswingPreEmph_1 4 bits ; eDp selects Vswing Preemph table for panel #01 -$eDP_VswingPreEmph_2 4 bits ; eDp selects Vswing Preemph table for panel #02 -$eDP_VswingPreEmph_3 4 bits ; eDp selects Vswing Preemph table for panel #03 -$eDP_VswingPreEmph_4 4 bits ; eDp selects Vswing Preemph table for panel #04 -$eDP_VswingPreEmph_5 4 bits ; eDp selects Vswing Preemph table for panel #05 -$eDP_VswingPreEmph_6 4 bits ; eDp selects Vswing Preemph table for panel #06 -$eDP_VswingPreEmph_7 4 bits ; eDp selects Vswing Preemph table for panel #07 -$eDP_VswingPreEmph_8 4 bits ; eDp selects Vswing Preemph table for panel #08 -$eDP_VswingPreEmph_9 4 bits ; eDp selects Vswing Preemph table for panel #09 -$eDP_VswingPreEmph_10 4 bits ; eDp selects Vswing Preemph table for panel #10 -$eDP_VswingPreEmph_11 4 bits ; eDp selects Vswing Preemph table for panel #11 -$eDP_VswingPreEmph_12 4 bits ; eDp selects Vswing Preemph table for panel #12 -$eDP_VswingPreEmph_13 4 bits ; eDp selects Vswing Preemph table for panel #13 -$eDP_VswingPreEmph_14 4 bits ; eDp selects Vswing Preemph table for panel #14 -$eDP_VswingPreEmph_15 4 bits ; eDp selects Vswing Preemph table for panel #15 -$eDP_VswingPreEmph_16 4 bits ; eDp selects Vswing Preemph table for panel #16 - -$eDP_Fast_Link_Training_Supported_01 1 bit ; eDP Fast Link Training enable disable VBT bit panel #01 -$eDP_Fast_Link_Training_Supported_02 1 bit ; eDP Fast Link Training enable disable VBT bit panel #02 -$eDP_Fast_Link_Training_Supported_03 1 bit ; eDP Fast Link Training enable disable VBT bit panel #03 -$eDP_Fast_Link_Training_Supported_04 1 bit ; eDP Fast Link Training enable disable VBT bit panel #04 -$eDP_Fast_Link_Training_Supported_05 1 bit ; eDP Fast Link Training enable disable VBT bit panel #05 -$eDP_Fast_Link_Training_Supported_06 1 bit ; eDP Fast Link Training enable disable VBT bit panel #06 -$eDP_Fast_Link_Training_Supported_07 1 bit ; eDP Fast Link Training enable disable VBT bit panel #07 -$eDP_Fast_Link_Training_Supported_08 1 bit ; eDP Fast Link Training enable disable VBT bit panel #08 -$eDP_Fast_Link_Training_Supported_09 1 bit ; eDP Fast Link Training enable disable VBT bit panel #09 -$eDP_Fast_Link_Training_Supported_10 1 bit ; eDP Fast Link Training enable disable VBT bit panel #10 -$eDP_Fast_Link_Training_Supported_11 1 bit ; eDP Fast Link Training enable disable VBT bit panel #11 -$eDP_Fast_Link_Training_Supported_12 1 bit ; eDP Fast Link Training enable disable VBT bit panel #12 -$eDP_Fast_Link_Training_Supported_13 1 bit ; eDP Fast Link Training enable disable VBT bit panel #13 -$eDP_Fast_Link_Training_Supported_14 1 bit ; eDP Fast Link Training enable disable VBT bit panel #14 -$eDP_Fast_Link_Training_Supported_15 1 bit ; eDP Fast Link Training enable disable VBT bit panel #15 -$eDP_Fast_Link_Training_Supported_16 1 bit ; eDP Fast Link Training enable disable VBT bit panel #16 - -SKIP 2 bytes ; Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #01 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #01 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #02 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #02 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #03 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #03 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #04 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #04 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #05 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #05 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #06 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #06 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #07 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #07 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #08 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #08 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #09 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #09 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel #16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panel #16 - -$eDP_Full_Link_Training_Params_Enable_01 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #01 -$eDP_Full_Link_Training_Params_Enable_02 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #02 -$eDP_Full_Link_Training_Params_Enable_03 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #03 -$eDP_Full_Link_Training_Params_Enable_04 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #04 -$eDP_Full_Link_Training_Params_Enable_05 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #05 -$eDP_Full_Link_Training_Params_Enable_06 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #06 -$eDP_Full_Link_Training_Params_Enable_07 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #07 -$eDP_Full_Link_Training_Params_Enable_08 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #08 -$eDP_Full_Link_Training_Params_Enable_09 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #09 -$eDP_Full_Link_Training_Params_Enable_10 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #10 -$eDP_Full_Link_Training_Params_Enable_11 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #11 -$eDP_Full_Link_Training_Params_Enable_12 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #12 -$eDP_Full_Link_Training_Params_Enable_13 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #13 -$eDP_Full_Link_Training_Params_Enable_14 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #14 -$eDP_Full_Link_Training_Params_Enable_15 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #15 -$eDP_Full_Link_Training_Params_Enable_16 1 bit ; eDP Full Link Training initial parameters in VBT enable bit panel #16 - -$eDP_Full_Link_Train_PreEmp_01 4 bits ; Panel #01 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_01 4 bits ; Panel #01 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_02 4 bits ; Panel #02 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_02 4 bits ; Panel #02 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_03 4 bits ; Panel #03 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_03 4 bits ; Panel #03 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_04 4 bits ; Panel #04 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_04 4 bits ; Panel #04 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_05 4 bits ; Panel #05 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_05 4 bits ; Panel #05 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_06 4 bits ; Panel #06 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_06 4 bits ; Panel #06 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_07 4 bits ; Panel #07 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_07 4 bits ; Panel #07 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_08 4 bits ; Panel #08 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_08 4 bits ; Panel #08 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_09 4 bits ; Panel #09 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_09 4 bits ; Panel #09 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_10 4 bits ; Panel #10 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_10 4 bits ; Panel #10 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_11 4 bits ; Panel #11 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_11 4 bits ; Panel #11 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_12 4 bits ; Panel #12 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_12 4 bits ; Panel #12 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_13 4 bits ; Panel #13 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_13 4 bits ; Panel #13 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_14 4 bits ; Panel #14 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_14 4 bits ; Panel #14 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_15 4 bits ; Panel #15 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_15 4 bits ; Panel #15 Full link training initial Voltage Swing - -$eDP_Full_Link_Train_PreEmp_16 4 bits ; Panel #16 Full link training initial Pre-emphasis -$eDP_Full_Link_Train_Vswing_16 4 bits ; Panel #16 Full link training initial Voltage Swing - -$eDP_Apical_Display_Ip_Enable_01 1 bit ; Panel #01 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_02 1 bit ; Panel #02 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_03 1 bit ; Panel #03 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_04 1 bit ; Panel #04 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_05 1 bit ; Panel #05 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_06 1 bit ; Panel #06 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_07 1 bit ; Panel #07 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_08 1 bit ; Panel #08 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_09 1 bit ; Panel #09 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_10 1 bit ; Panel #10 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_11 1 bit ; Panel #11 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_12 1 bit ; Panel #12 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_13 1 bit ; Panel #13 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_14 1 bit ; Panel #14 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_15 1 bit ; Panel #15 Apical Display IP Enable bit -$eDP_Apical_Display_Ip_Enable_16 1 bit ; Panel #16 Apical Display IP Enable bit - -; Panel #01 Apical Display IP parameters -$eDP_Panel_Oui_01 4 bytes ; Panel #01 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_01 4 bytes ; Panel #01 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_01 4 bytes ; Panel #01 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_01 4 bytes ; Panel #01 Apical specific DPCD option select -$eDP_Dpcd_Backlight_01 4 bytes ; Panel #01 Apical specific DPCD backlight -$eDP_Ambient_Light_01 4 bytes ; Panel #01 Apical specific Ambient light -$eDP_Backlight_Scale_01 4 bytes ; Panel #01 Apical specific backlight scale value - -; Panel #02 Apical Display IP parameters -$eDP_Panel_Oui_02 4 bytes ; Panel #02 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_02 4 bytes ; Panel #02 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_02 4 bytes ; Panel #02 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_02 4 bytes ; Panel #02 Apical specific DPCD option select -$eDP_Dpcd_Backlight_02 4 bytes ; Panel #02 Apical specific DPCD backlight -$eDP_Ambient_Light_02 4 bytes ; Panel #02 Apical specific Ambient light -$eDP_Backlight_Scale_02 4 bytes ; Panel #02 Apical specific backlight scale value - -; Panel #03 Apical Display IP parameters -$eDP_Panel_Oui_03 4 bytes ; Panel #03 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_03 4 bytes ; Panel #03 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_03 4 bytes ; Panel #03 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_03 4 bytes ; Panel #03 Apical specific DPCD option select -$eDP_Dpcd_Backlight_03 4 bytes ; Panel #03 Apical specific DPCD backlight -$eDP_Ambient_Light_03 4 bytes ; Panel #03 Apical specific Ambient light -$eDP_Backlight_Scale_03 4 bytes ; Panel #03 Apical specific backlight scale value - -; Panel #04 Apical Display IP parameters -$eDP_Panel_Oui_04 4 bytes ; Panel #04 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_04 4 bytes ; Panel #04 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_04 4 bytes ; Panel #04 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_04 4 bytes ; Panel #04 Apical specific DPCD option select -$eDP_Dpcd_Backlight_04 4 bytes ; Panel #04 Apical specific DPCD backlight -$eDP_Ambient_Light_04 4 bytes ; Panel #04 Apical specific Ambient light -$eDP_Backlight_Scale_04 4 bytes ; Panel #04 Apical specific backlight scale value - -; Panel #05 Apical Display IP parameters -$eDP_Panel_Oui_05 4 bytes ; Panel #05 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_05 4 bytes ; Panel #05 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_05 4 bytes ; Panel #05 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_05 4 bytes ; Panel #05 Apical specific DPCD option select -$eDP_Dpcd_Backlight_05 4 bytes ; Panel #05 Apical specific DPCD backlight -$eDP_Ambient_Light_05 4 bytes ; Panel #05 Apical specific Ambient light -$eDP_Backlight_Scale_05 4 bytes ; Panel #05 Apical specific backlight scale value - -; Panel #06 Apical Display IP parameters -$eDP_Panel_Oui_06 4 bytes ; Panel #06 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_06 4 bytes ; Panel #06 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_06 4 bytes ; Panel #06 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_06 4 bytes ; Panel #06 Apical specific DPCD option select -$eDP_Dpcd_Backlight_06 4 bytes ; Panel #06 Apical specific DPCD backlight -$eDP_Ambient_Light_06 4 bytes ; Panel #06 Apical specific Ambient light -$eDP_Backlight_Scale_06 4 bytes ; Panel #06 Apical specific backlight scale value - -; Panel #07 Apical Display IP parameters -$eDP_Panel_Oui_07 4 bytes ; Panel #07 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_07 4 bytes ; Panel #07 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_07 4 bytes ; Panel #07 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_07 4 bytes ; Panel #07 Apical specific DPCD option select -$eDP_Dpcd_Backlight_07 4 bytes ; Panel #07 Apical specific DPCD backlight -$eDP_Ambient_Light_07 4 bytes ; Panel #07 Apical specific Ambient light -$eDP_Backlight_Scale_07 4 bytes ; Panel #07 Apical specific backlight scale value - -; Panel #08 Apical Display IP parameters -$eDP_Panel_Oui_08 4 bytes ; Panel #08 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_08 4 bytes ; Panel #08 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_08 4 bytes ; Panel #08 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_08 4 bytes ; Panel #08 Apical specific DPCD option select -$eDP_Dpcd_Backlight_08 4 bytes ; Panel #08 Apical specific DPCD backlight -$eDP_Ambient_Light_08 4 bytes ; Panel #08 Apical specific Ambient light -$eDP_Backlight_Scale_08 4 bytes ; Panel #08 Apical specific backlight scale value - -; Panel #09 Apical Display IP parameters -$eDP_Panel_Oui_09 4 bytes ; Panel #09 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_09 4 bytes ; Panel #09 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_09 4 bytes ; Panel #09 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_09 4 bytes ; Panel #09 Apical specific DPCD option select -$eDP_Dpcd_Backlight_09 4 bytes ; Panel #09 Apical specific DPCD backlight -$eDP_Ambient_Light_09 4 bytes ; Panel #09 Apical specific Ambient light -$eDP_Backlight_Scale_09 4 bytes ; Panel #09 Apical specific backlight scale value - -; Panel #10 Apical Display IP parameters -$eDP_Panel_Oui_10 4 bytes ; Panel #10 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_10 4 bytes ; Panel #10 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_10 4 bytes ; Panel #10 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_10 4 bytes ; Panel #10 Apical specific DPCD option select -$eDP_Dpcd_Backlight_10 4 bytes ; Panel #10 Apical specific DPCD backlight -$eDP_Ambient_Light_10 4 bytes ; Panel #10 Apical specific Ambient light -$eDP_Backlight_Scale_10 4 bytes ; Panel #10 Apical specific backlight scale value - -; Panel #11 Apical Display IP parameters -$eDP_Panel_Oui_11 4 bytes ; Panel #11 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_11 4 bytes ; Panel #11 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_11 4 bytes ; Panel #11 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_11 4 bytes ; Panel #11 Apical specific DPCD option select -$eDP_Dpcd_Backlight_11 4 bytes ; Panel #11 Apical specific DPCD backlight -$eDP_Ambient_Light_11 4 bytes ; Panel #11 Apical specific Ambient light -$eDP_Backlight_Scale_11 4 bytes ; Panel #11 Apical specific backlight scale value - -; Panel #12 Apical Display IP parameters -$eDP_Panel_Oui_12 4 bytes ; Panel #12 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_12 4 bytes ; Panel #12 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_12 4 bytes ; Panel #12 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_12 4 bytes ; Panel #12 Apical specific DPCD option select -$eDP_Dpcd_Backlight_12 4 bytes ; Panel #12 Apical specific DPCD backlight -$eDP_Ambient_Light_12 4 bytes ; Panel #12 Apical specific Ambient light -$eDP_Backlight_Scale_12 4 bytes ; Panel #12 Apical specific backlight scale value - -; Panel #13 Apical Display IP parameters -$eDP_Panel_Oui_13 4 bytes ; Panel #13 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_13 4 bytes ; Panel #13 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_13 4 bytes ; Panel #13 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_13 4 bytes ; Panel #13 Apical specific DPCD option select -$eDP_Dpcd_Backlight_13 4 bytes ; Panel #13 Apical specific DPCD backlight -$eDP_Ambient_Light_13 4 bytes ; Panel #13 Apical specific Ambient light -$eDP_Backlight_Scale_13 4 bytes ; Panel #13 Apical specific backlight scale value - -; Panel #14 Apical Display IP parameters -$eDP_Panel_Oui_14 4 bytes ; Panel #14 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_14 4 bytes ; Panel #14 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_14 4 bytes ; Panel #14 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_14 4 bytes ; Panel #14 Apical specific DPCD option select -$eDP_Dpcd_Backlight_14 4 bytes ; Panel #14 Apical specific DPCD backlight -$eDP_Ambient_Light_14 4 bytes ; Panel #14 Apical specific Ambient light -$eDP_Backlight_Scale_14 4 bytes ; Panel #14 Apical specific backlight scale value - -; Panel #15 Apical Display IP parameters -$eDP_Panel_Oui_15 4 bytes ; Panel #15 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_15 4 bytes ; Panel #15 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_15 4 bytes ; Panel #15 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_15 4 bytes ; Panel #15 Apical specific DPCD option select -$eDP_Dpcd_Backlight_15 4 bytes ; Panel #15 Apical specific DPCD backlight -$eDP_Ambient_Light_15 4 bytes ; Panel #15 Apical specific Ambient light -$eDP_Backlight_Scale_15 4 bytes ; Panel #15 Apical specific backlight scale value - -; Panel #16 Apical Display IP parameters -$eDP_Panel_Oui_16 4 bytes ; Panel #16 Apical specific Panel OUI -$eDP_Dpcd_Base_Address_16 4 bytes ; Panel #16 Apical specific DPCD base address -$eDP_Dpcd_Irdidix_Control0_16 4 bytes ; Panel #16 Apical specific DPCD Idridix control 0 -$eDP_Dpcd_Option_Select_16 4 bytes ; Panel #16 Apical specific DPCD option select -$eDP_Dpcd_Backlight_16 4 bytes ; Panel #16 Apical specific DPCD backlight -$eDP_Ambient_Light_16 4 bytes ; Panel #16 Apical specific Ambient light -$eDP_Backlight_Scale_16 4 bytes ; Panel #16 Apical specific backlight scale value - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -SKIP 18 bytes ; Skip DTD for Device 3 DP/HDMI/DVI panel -SKIP 18 bytes ; Skip DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for BXT -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 92 bytes ; Skip Toggle lists -ALIGN - -;============================================================================== -; Block 32 - Display Removal Configurations for BXT -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsoleted -SKIP 6 bits ; Skip bits 0:5 of bmp_LVDS_Capabilities -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit ; Skip bit 7 of bmp_LVDS_Capabilities -SKIP 1 byte ; Skip bits 8:15 of bmp_LVDS_Capabilities - -; INT_LVDS_Panel_Channel_Bits -SKIP 4 bytes ; Obsolete: Was used for LVDS panel channel type. - -; LVDS Spread Spectrum Clock -; Enable/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - -SKIP 2 bytes ; Obsolete: Was used for SSC frequency for LVDS. - -SKIP 2 bytes ; Obsolete: Was used for Disable SSC in DDT mode. - -SKIP 2 bytes ; Obsolete: Was used for panel color depth for LVDS panels. - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - -$LcdVcc_On_During_S0_State_01 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #01 -$LcdVcc_On_During_S0_State_02 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #02 -$LcdVcc_On_During_S0_State_03 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #03 -$LcdVcc_On_During_S0_State_04 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #04 -$LcdVcc_On_During_S0_State_05 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #05 -$LcdVcc_On_During_S0_State_06 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #06 -$LcdVcc_On_During_S0_State_07 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #07 -$LcdVcc_On_During_S0_State_08 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #08 -$LcdVcc_On_During_S0_State_09 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #09 -$LcdVcc_On_During_S0_State_10 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #10 -$LcdVcc_On_During_S0_State_11 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #11 -$LcdVcc_On_During_S0_State_12 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #12 -$LcdVcc_On_During_S0_State_13 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #13 -$LcdVcc_On_During_S0_State_14 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #14 -$LcdVcc_On_During_S0_State_15 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #15 -$LcdVcc_On_During_S0_State_16 1 bit ; Enable flag to keep LCDVCC on during S0 state bit for panel #16 - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -$LVDS_Name_Ptr 2 bytes -$LVDS_Name_Sz 1 byte ; Skip LFP_PanelName offset and panel name length - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #02 -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #03 -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #04 -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #05 -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #06 -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #07 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #08 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #09 -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #10 -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #11 -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #12 -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #13 -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #14 -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #15 -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -; Flat Panel #16 -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height - -SKIP 34 bytes ; Skip remaining size of FP Data structure. -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -$Enable_Scaling_01 1 bit ; Scaling Enable bit for Panel #01 -$Enable_Scaling_02 1 bit ; Scaling Enable bit for Panel #02 -$Enable_Scaling_03 1 bit ; Scaling Enable bit for Panel #03 -$Enable_Scaling_04 1 bit ; Scaling Enable bit for Panel #04 -$Enable_Scaling_05 1 bit ; Scaling Enable bit for Panel #05 -$Enable_Scaling_06 1 bit ; Scaling Enable bit for Panel #06 -$Enable_Scaling_07 1 bit ; Scaling Enable bit for Panel #07 -$Enable_Scaling_08 1 bit ; Scaling Enable bit for Panel #08 -$Enable_Scaling_09 1 bit ; Scaling Enable bit for Panel #09 -$Enable_Scaling_10 1 bit ; Scaling Enable bit for Panel #10 -$Enable_Scaling_11 1 bit ; Scaling Enable bit for Panel #11 -$Enable_Scaling_12 1 bit ; Scaling Enable bit for Panel #12 -$Enable_Scaling_13 1 bit ; Scaling Enable bit for Panel #13 -$Enable_Scaling_14 1 bit ; Scaling Enable bit for Panel #14 -$Enable_Scaling_15 1 bit ; Scaling Enable bit for Panel #15 -$Enable_Scaling_16 1 bit ; Scaling Enable bit for Panel #16 - -$Seamless_DRRS_Min_RR_01 1 byte ; Seamless DRRS Min Refresh Rate for Panel #01 -$Seamless_DRRS_Min_RR_02 1 byte ; Seamless DRRS Min Refresh Rate for Panel #02 -$Seamless_DRRS_Min_RR_03 1 byte ; Seamless DRRS Min Refresh Rate for Panel #03 -$Seamless_DRRS_Min_RR_04 1 byte ; Seamless DRRS Min Refresh Rate for Panel #04 -$Seamless_DRRS_Min_RR_05 1 byte ; Seamless DRRS Min Refresh Rate for Panel #05 -$Seamless_DRRS_Min_RR_06 1 byte ; Seamless DRRS Min Refresh Rate for Panel #06 -$Seamless_DRRS_Min_RR_07 1 byte ; Seamless DRRS Min Refresh Rate for Panel #07 -$Seamless_DRRS_Min_RR_08 1 byte ; Seamless DRRS Min Refresh Rate for Panel #08 -$Seamless_DRRS_Min_RR_09 1 byte ; Seamless DRRS Min Refresh Rate for Panel #09 -$Seamless_DRRS_Min_RR_10 1 byte ; Seamless DRRS Min Refresh Rate for Panel #10 -$Seamless_DRRS_Min_RR_11 1 byte ; Seamless DRRS Min Refresh Rate for Panel #11 -$Seamless_DRRS_Min_RR_12 1 byte ; Seamless DRRS Min Refresh Rate for Panel #12 -$Seamless_DRRS_Min_RR_13 1 byte ; Seamless DRRS Min Refresh Rate for Panel #13 -$Seamless_DRRS_Min_RR_14 1 byte ; Seamless DRRS Min Refresh Rate for Panel #14 -$Seamless_DRRS_Min_RR_15 1 byte ; Seamless DRRS Min Refresh Rate for Panel #15 -$Seamless_DRRS_Min_RR_16 1 byte ; Seamless DRRS Min Refresh Rate for Panel #16 - -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - -; Flat Panel #01 -$BLC_Inv_Type_01 2 bits ; BLC inverter type -$BLC_Inv_Polarity_01 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_01 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_01 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_01 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_01 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_01 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_01 1 byte ; I2C inverter command code - -; Flat Panel #02 -$BLC_Inv_Type_02 2 bits ; BLC inverter type -$BLC_Inv_Polarity_02 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_02 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_02 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_02 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_02 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_02 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_02 1 byte ; I2C inverter command code - -; Flat Panel #03 -$BLC_Inv_Type_03 2 bits ; BLC inverter type -$BLC_Inv_Polarity_03 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_03 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_03 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_03 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_03 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_03 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_03 1 byte ; I2C inverter command code - -; Flat Panel #04 -$BLC_Inv_Type_04 2 bits ; BLC inverter type -$BLC_Inv_Polarity_04 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_04 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_04 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_04 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_04 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_04 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_04 1 byte ; I2C inverter command code - -; Flat Panel #05 -$BLC_Inv_Type_05 2 bits ; BLC inverter type -$BLC_Inv_Polarity_05 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_05 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_05 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_05 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_05 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_05 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_05 1 byte ; I2C inverter command code - -; Flat Panel #06 -$BLC_Inv_Type_06 2 bits ; BLC inverter type -$BLC_Inv_Polarity_06 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_06 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_06 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_06 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_06 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_06 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_06 1 byte ; I2C inverter command code - -; Flat Panel #07 -$BLC_Inv_Type_07 2 bits ; BLC inverter type -$BLC_Inv_Polarity_07 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_07 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_07 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_07 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_07 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_07 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_07 1 byte ; I2C inverter command code - -; Flat Panel #08 -$BLC_Inv_Type_08 2 bits ; BLC inverter type -$BLC_Inv_Polarity_08 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_08 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_08 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_08 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_08 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_08 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_08 1 byte ; I2C inverter command code - -; Flat Panel #09 -$BLC_Inv_Type_09 2 bits ; BLC inverter type -$BLC_Inv_Polarity_09 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_09 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_09 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_09 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_09 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_09 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_09 1 byte ; I2C inverter command code - -; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - -; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - -; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - -; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - -; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - -; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - -; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #01 -$POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #02 -$POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #03 -$POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #04 -$POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #05 -$POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #06 -$POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #07 -$POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #08 -$POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #09 -$POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 -$POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 -$POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 -$POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 -$POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 -$POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 -$POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - -$Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 -$Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - -$Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 -$Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - -$Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 -$Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - -$Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 -$Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - -$Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 -$Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - -$Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 -$Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - -$Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 -$Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - -$Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 -$Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - -$Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 -$Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - -$Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 -$Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - -$Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 -$Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - -$Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 -$Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - -$Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 -$Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - -$Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 -$Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - -$Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 -$Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - -$Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 -$Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 bit ; Reserved -$BIA_Aggress_Level 3 bits ; Power Conservation Preference level -SKIP 3 bits ; Reserved -SKIP 1 bit -ALIGN - -$ALS_Response_Data 20 bytes ; ALS Response Data - -;============================================================================== -; Block 46 - Chromaticity Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -; Flat Panel #01 -$Chromacity_Enable_01 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_01 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_01 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_01 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_01 1 byte ; Red x coordinate at 1Bh -$Red_y_01 1 byte ; Red y coordinate at 1Ch -$Green_x_01 1 byte ; Green x coordinate at 1Dh -$Green_y_01 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_01 1 byte ; Blue x coordinate at 1Fh -$Blue_y_01 1 byte ; Blue y coordinate at 20h -$White_x_01 1 byte ; White x coordiante at 21h -$White_y_01 1 byte ; White y coordinate at 22h - -; Flat Panel #02 -$Chromacity_Enable_02 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_02 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_02 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_02 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_02 1 byte ; Red x coordinate at 1Bh -$Red_y_02 1 byte ; Red y coordinate at 1Ch -$Green_x_02 1 byte ; Green x coordinate at 1Dh -$Green_y_02 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_02 1 byte ; Blue x coordinate at 1Fh -$Blue_y_02 1 byte ; Blue y coordinate at 20h -$White_x_02 1 byte ; White x coordiante at 21h -$White_y_02 1 byte ; White y coordinate at 22h - -; Flat Panel #03 -$Chromacity_Enable_03 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_03 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_03 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_03 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_03 1 byte ; Red x coordinate at 1Bh -$Red_y_03 1 byte ; Red y coordinate at 1Ch -$Green_x_03 1 byte ; Green x coordinate at 1Dh -$Green_y_03 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_03 1 byte ; Blue x coordinate at 1Fh -$Blue_y_03 1 byte ; Blue y coordinate at 20h -$White_x_03 1 byte ; White x coordiante at 21h -$White_y_03 1 byte ; White y coordinate at 22h - -; Flat Panel #04 -$Chromacity_Enable_04 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_04 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_04 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_04 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_04 1 byte ; Red x coordinate at 1Bh -$Red_y_04 1 byte ; Red y coordinate at 1Ch -$Green_x_04 1 byte ; Green x coordinate at 1Dh -$Green_y_04 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_04 1 byte ; Blue x coordinate at 1Fh -$Blue_y_04 1 byte ; Blue y coordinate at 20h -$White_x_04 1 byte ; White x coordiante at 21h -$White_y_04 1 byte ; White y coordinate at 22h - -; Flat Panel #05 -$Chromacity_Enable_05 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_05 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_05 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_05 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_05 1 byte ; Red x coordinate at 1Bh -$Red_y_05 1 byte ; Red y coordinate at 1Ch -$Green_x_05 1 byte ; Green x coordinate at 1Dh -$Green_y_05 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_05 1 byte ; Blue x coordinate at 1Fh -$Blue_y_05 1 byte ; Blue y coordinate at 20h -$White_x_05 1 byte ; White x coordiante at 21h -$White_y_05 1 byte ; White y coordinate at 22h - -; Flat Panel #06 -$Chromacity_Enable_06 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_06 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_06 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_06 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_06 1 byte ; Red x coordinate at 1Bh -$Red_y_06 1 byte ; Red y coordinate at 1Ch -$Green_x_06 1 byte ; Green x coordinate at 1Dh -$Green_y_06 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_06 1 byte ; Blue x coordinate at 1Fh -$Blue_y_06 1 byte ; Blue y coordinate at 20h -$White_x_06 1 byte ; White x coordiante at 21h -$White_y_06 1 byte ; White y coordinate at 22h - -; Flat Panel #07 -$Chromacity_Enable_07 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_07 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_07 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_07 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_07 1 byte ; Red x coordinate at 1Bh -$Red_y_07 1 byte ; Red y coordinate at 1Ch -$Green_x_07 1 byte ; Green x coordinate at 1Dh -$Green_y_07 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_07 1 byte ; Blue x coordinate at 1Fh -$Blue_y_07 1 byte ; Blue y coordinate at 20h -$White_x_07 1 byte ; White x coordiante at 21h -$White_y_07 1 byte ; White y coordinate at 22h - -; Flat Panel #08 -$Chromacity_Enable_08 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_08 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_08 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_08 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_08 1 byte ; Red x coordinate at 1Bh -$Red_y_08 1 byte ; Red y coordinate at 1Ch -$Green_x_08 1 byte ; Green x coordinate at 1Dh -$Green_y_08 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_08 1 byte ; Blue x coordinate at 1Fh -$Blue_y_08 1 byte ; Blue y coordinate at 20h -$White_x_08 1 byte ; White x coordiante at 21h -$White_y_08 1 byte ; White y coordinate at 22h - -; Flat Panel #09 -$Chromacity_Enable_09 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_09 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_09 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_09 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_09 1 byte ; Red x coordinate at 1Bh -$Red_y_09 1 byte ; Red y coordinate at 1Ch -$Green_x_09 1 byte ; Green x coordinate at 1Dh -$Green_y_09 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_09 1 byte ; Blue x coordinate at 1Fh -$Blue_y_09 1 byte ; Blue y coordinate at 20h -$White_x_09 1 byte ; White x coordiante at 21h -$White_y_09 1 byte ; White y coordinate at 22h - -; Flat Panel #10 -$Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_10 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_10 1 byte ; Red x coordinate at 1Bh -$Red_y_10 1 byte ; Red y coordinate at 1Ch -$Green_x_10 1 byte ; Green x coordinate at 1Dh -$Green_y_10 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_10 1 byte ; Blue x coordinate at 1Fh -$Blue_y_10 1 byte ; Blue y coordinate at 20h -$White_x_10 1 byte ; White x coordiante at 21h -$White_y_10 1 byte ; White y coordinate at 22h - -; Flat Panel #11 -$Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_11 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_11 1 byte ; Red x coordinate at 1Bh -$Red_y_11 1 byte ; Red y coordinate at 1Ch -$Green_x_11 1 byte ; Green x coordinate at 1Dh -$Green_y_11 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_11 1 byte ; Blue x coordinate at 1Fh -$Blue_y_11 1 byte ; Blue y coordinate at 20h -$White_x_11 1 byte ; White x coordiante at 21h -$White_y_11 1 byte ; White y coordinate at 22h - -; Flat Panel #12 -$Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_12 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_12 1 byte ; Red x coordinate at 1Bh -$Red_y_12 1 byte ; Red y coordinate at 1Ch -$Green_x_12 1 byte ; Green x coordinate at 1Dh -$Green_y_12 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_12 1 byte ; Blue x coordinate at 1Fh -$Blue_y_12 1 byte ; Blue y coordinate at 20h -$White_x_12 1 byte ; White x coordiante at 21h -$White_y_12 1 byte ; White y coordinate at 22h - -; Flat Panel #13 -$Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_13 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_13 1 byte ; Red x coordinate at 1Bh -$Red_y_13 1 byte ; Red y coordinate at 1Ch -$Green_x_13 1 byte ; Green x coordinate at 1Dh -$Green_y_13 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_13 1 byte ; Blue x coordinate at 1Fh -$Blue_y_13 1 byte ; Blue y coordinate at 20h -$White_x_13 1 byte ; White x coordiante at 21h -$White_y_13 1 byte ; White y coordinate at 22h - -; Flat Panel #14 -$Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_14 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_14 1 byte ; Red x coordinate at 1Bh -$Red_y_14 1 byte ; Red y coordinate at 1Ch -$Green_x_14 1 byte ; Green x coordinate at 1Dh -$Green_y_14 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_14 1 byte ; Blue x coordinate at 1Fh -$Blue_y_14 1 byte ; Blue y coordinate at 20h -$White_x_14 1 byte ; White x coordiante at 21h -$White_y_14 1 byte ; White y coordinate at 22h - -; Flat Panel #15 -$Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_15 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_15 1 byte ; Red x coordinate at 1Bh -$Red_y_15 1 byte ; Red y coordinate at 1Ch -$Green_x_15 1 byte ; Green x coordinate at 1Dh -$Green_y_15 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_15 1 byte ; Blue x coordinate at 1Fh -$Blue_y_15 1 byte ; Blue y coordinate at 20h -$White_x_15 1 byte ; White x coordiante at 21h -$White_y_15 1 byte ; White y coordinate at 22h - -; Flat Panel #16 -$Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit -$Override_EDID_Data_16 1 bit ; Override the chromaticity bit -SKIP 6 bits ; Reserved bits -$Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h -$Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah -$Red_x_16 1 byte ; Red x coordinate at 1Bh -$Red_y_16 1 byte ; Red y coordinate at 1Ch -$Green_x_16 1 byte ; Green x coordinate at 1Dh -$Green_y_16 1 byte ; Green y ccoordinate at 1Eh -$Blue_x_16 1 byte ; Blue x coordinate at 1Fh -$Blue_y_16 1 byte ; Blue y coordinate at 20h -$White_x_16 1 byte ; White x coordiante at 21h -$White_y_16 1 byte ; White y coordinate at 22h - -;============================================================================== -; Block 51 - Fixed Mode Set Block -;----------------------------------------------------------------------------- -SKIP 3 bytes ; Skip Block ID and size - -$Feature_Enable 1 byte ; Enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -;============================================================================== -; Block 52 - MIPI DSI Configuration Block -;----------------------------------------------------------------------------- - -$MIPI_DSI_CONF_BLOCKID 1 byte -$MIPI_DSI_CONF_BLOCKSIZE 2 bytes - -;MIPI DSI CONF Panel#1 -$PanelIdentifier_01 2 bytes ;PanelIdentifier - -$Dithering_01 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_01 1 bit -$MIPI_DSI_Panel_Architecture_Type_01 2 bits -$Video_Command_Mode_01 1 bit -$Packet_Sequence_Video_Mode_01 2 bits -$CABC_Support_01 1 bit -$PmicSocSelection_01 1 bit -$Colour_Format_Video_Mode_01 4 bits -$Panel_Rotation_01 2 bits -$Bta_Disable_01 1 bit -SKIP 15 bits - -$Dual_Link_01 2 bits ;PortDesc -$Number_Of_Lanes_01 2 bits -$Pixel_Overlap_Count_01 3 bits -$RgbFlip_01 1 bit -$CabcCmdsPort_01 2 bits -$PanelPwmCmdsPort_01 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_01 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_01 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_01 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_01 1 bit ;DphyFlags -$EoTpSupport_01 1 bit ;EoTpSupport -$ClockStop_01 1 bit -SKIP 13 bits - -$HsTxTimeOut_01 4 bytes ;HsTxTimeOut -$LpRxTimeOut_01 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_01 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_01 4 bytes ;DeviceResetTimer -$MasterInitTimer_01 4 bytes ;MasterInitTimer -$DbiBwTimer_01 32 bits ;DbiBwTimer - -$LpByteClkRegValue_01 32 bits ;LpByteClkRegValue -$DphyParamRegValue_01 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_01 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_01 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_01 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_01 1 byte ;TClkTrail -$TClkPrepareTClkZero_01 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_01 1 byte ;THsPrepare -$THsPrepareTHsZero_01 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_01 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_01 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_01 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_01 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_01 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_01 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_01 1 bit ;StbyRN -SKIP 7 bits - -;MIPI DSI CONF Panel#2 -$PanelIdentifier_02 2 bytes ;PanelIdentifier - -$Dithering_02 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_02 1 bit -$MIPI_DSI_Panel_Architecture_Type_02 2 bits -$Video_Command_Mode_02 1 bit -$Packet_Sequence_Video_Mode_02 2 bits -$CABC_Support_02 1 bit -$PmicSocSelection_02 1 bit -$Colour_Format_Video_Mode_02 4 bits -$Panel_Rotation_02 2 bits -$Bta_Disable_02 1 bit -SKIP 15 bits - -$Dual_Link_02 2 bits ;PortDesc -$Number_Of_Lanes_02 2 bits -$Pixel_Overlap_Count_02 3 bits -$RgbFlip_02 1 bit -$CabcCmdsPort_02 2 bits -$PanelPwmCmdsPort_02 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_02 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_02 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_02 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_02 1 bit ;DphyFlags -$EoTpSupport_02 1 bit ;EoTpSupport -$ClockStop_02 1 bit -SKIP 13 bits - -$HsTxTimeOut_02 4 bytes ;HsTxTimeOut -$LpRxTimeOut_02 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_02 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_02 4 bytes ;DeviceResetTimer -$MasterInitTimer_02 4 bytes ;MasterInitTimer -$DbiBwTimer_02 32 bits ;DbiBwTimer - -$LpByteClkRegValue_02 32 bits ;LpByteClkRegValue -$DphyParamRegValue_02 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_02 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_02 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_02 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_02 1 byte ;TClkTrail -$TClkPrepareTClkZero_02 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_02 1 byte ;THsPrepare -$THsPrepareTHsZero_02 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_02 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_02 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_02 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_02 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_02 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_02 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_02 1 bit ;StbyRN -SKIP 7 bits - -;MIPI DSI CONF Panel#3 -$PanelIdentifier_03 2 bytes ;PanelIdentifier - -$Dithering_03 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_03 1 bit -$MIPI_DSI_Panel_Architecture_Type_03 2 bits -$Video_Command_Mode_03 1 bit -$Packet_Sequence_Video_Mode_03 2 bits -$CABC_Support_03 1 bit -$PmicSocSelection_03 1 bit -$Colour_Format_Video_Mode_03 4 bits -$Panel_Rotation_03 2 bits -$Bta_Disable_03 1 bit -SKIP 15 bits - -$Dual_Link_03 2 bits ;PortDesc -$Number_Of_Lanes_03 2 bits -$Pixel_Overlap_Count_03 3 bits -$RgbFlip_03 1 bit -$CabcCmdsPort_03 2 bits -$PanelPwmCmdsPort_03 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_03 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_03 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_03 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_03 1 bit ;DphyFlags -$EoTpSupport_03 1 bit ;EoTpSupport -$ClockStop_03 1 bit -SKIP 13 bits - -$HsTxTimeOut_03 4 bytes ;HsTxTimeOut -$LpRxTimeOut_03 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_03 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_03 4 bytes ;DeviceResetTimer -$MasterInitTimer_03 4 bytes ;MasterInitTimer -$DbiBwTimer_03 32 bits ;DbiBwTimer - -$LpByteClkRegValue_03 32 bits ;LpByteClkRegValue -$DphyParamRegValue_03 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_03 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_03 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_03 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_03 1 byte ;TClkTrail -$TClkPrepareTClkZero_03 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_03 1 byte ;THsPrepare -$THsPrepareTHsZero_03 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_03 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_03 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_03 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_03 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_03 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_03 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_03 1 bit ;StbyRN -SKIP 7 bits - -;MIPI DSI CONF Panel#4 -$PanelIdentifier_04 2 bytes ;PanelIdentifier - -$Dithering_04 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_04 1 bit -$MIPI_DSI_Panel_Architecture_Type_04 2 bits -$Video_Command_Mode_04 1 bit -$Packet_Sequence_Video_Mode_04 2 bits -$CABC_Support_04 1 bit -$PmicSocSelection_04 1 bit -$Colour_Format_Video_Mode_04 4 bits -$Panel_Rotation_04 2 bits -$Bta_Disable_04 1 bit -SKIP 15 bits - -$Dual_Link_04 2 bits ;PortDesc -$Number_Of_Lanes_04 2 bits -$Pixel_Overlap_Count_04 3 bits -$RgbFlip_04 1 bit -$CabcCmdsPort_04 2 bits -$PanelPwmCmdsPort_04 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_04 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_04 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_04 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_04 1 bit ;DphyFlags -$EoTpSupport_04 1 bit ;EoTpSupport -$ClockStop_04 1 bit -SKIP 13 bits - -$HsTxTimeOut_04 4 bytes ;HsTxTimeOut -$LpRxTimeOut_04 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_04 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_04 4 bytes ;DeviceResetTimer -$MasterInitTimer_04 4 bytes ;MasterInitTimer -$DbiBwTimer_04 32 bits ;DbiBwTimer - -$LpByteClkRegValue_04 32 bits ;LpByteClkRegValue -$DphyParamRegValue_04 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_04 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_04 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_04 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_04 1 byte ;TClkTrail -$TClkPrepareTClkZero_04 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_04 1 byte ;THsPrepare -$THsPrepareTHsZero_04 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_04 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_04 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_04 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_04 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_04 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_04 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_04 1 bit ;StbyRN -SKIP 7 bits - -;MIPI DSI CONF Panel#5 -$PanelIdentifier_05 2 bytes ;PanelIdentifier - -$Dithering_05 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_05 1 bit -$MIPI_DSI_Panel_Architecture_Type_05 2 bits -$Video_Command_Mode_05 1 bit -$Packet_Sequence_Video_Mode_05 2 bits -$CABC_Support_05 1 bit -$PmicSocSelection_05 1 bit -$Colour_Format_Video_Mode_05 4 bits -$Panel_Rotation_05 2 bits -$Bta_Disable_05 1 bit -SKIP 15 bits - -$Dual_Link_05 2 bits ;PortDesc -$Number_Of_Lanes_05 2 bits -$Pixel_Overlap_Count_05 3 bits -$RgbFlip_05 1 bit -$CabcCmdsPort_05 2 bits -$PanelPwmCmdsPort_05 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_05 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_05 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_05 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_05 1 bit ;DphyFlags -$EoTpSupport_05 1 bit ;EoTpSupport -$ClockStop_05 1 bit -SKIP 13 bits - -$HsTxTimeOut_05 4 bytes ;HsTxTimeOut -$LpRxTimeOut_05 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_05 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_05 4 bytes ;DeviceResetTimer -$MasterInitTimer_05 4 bytes ;MasterInitTimer -$DbiBwTimer_05 32 bits ;DbiBwTimer - -$LpByteClkRegValue_05 32 bits ;LpByteClkRegValue -$DphyParamRegValue_05 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_05 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_05 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_05 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_05 1 byte ;TClkTrail -$TClkPrepareTClkZero_05 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_05 1 byte ;THsPrepare -$THsPrepareTHsZero_05 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_05 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_05 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_05 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_05 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_05 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_05 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_05 1 bit ;StbyRN -SKIP 7 bits - -;MIPI DSI CONF Panel#6 -$PanelIdentifier_06 2 bytes ;PanelIdentifier - -$Dithering_06 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_06 1 bit -$MIPI_DSI_Panel_Architecture_Type_06 2 bits -$Video_Command_Mode_06 1 bit -$Packet_Sequence_Video_Mode_06 2 bits -$CABC_Support_06 1 bit -$PmicSocSelection_06 1 bit -$Colour_Format_Video_Mode_06 4 bits -$Panel_Rotation_06 2 bits -$Bta_Disable_06 1 bit -SKIP 15 bits - -$Dual_Link_06 2 bits ;PortDesc -$Number_Of_Lanes_06 2 bits -$Pixel_Overlap_Count_06 3 bits -$RgbFlip_06 1 bit -$CabcCmdsPort_06 2 bits -$PanelPwmCmdsPort_06 2 bits -SKIP 4 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_06 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_06 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_06 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_06 1 bit ;DphyFlags -$EoTpSupport_06 1 bit ;EoTpSupport -$ClockStop_06 1 bit -SKIP 13 bits - -$HsTxTimeOut_06 4 bytes ;HsTxTimeOut -$LpRxTimeOut_06 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_06 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_06 4 bytes ;DeviceResetTimer -$MasterInitTimer_06 4 bytes ;MasterInitTimer -$DbiBwTimer_06 32 bits ;DbiBwTimer - -$LpByteClkRegValue_06 32 bits ;LpByteClkRegValue -$DphyParamRegValue_06 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_06 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_06 32 bits ;HighLowSwitchCount - -SKIP 24 bytes ;Reserved - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_06 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_06 1 byte ;TClkTrail -$TClkPrepareTClkZero_06 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_06 1 byte ;THsPrepare -$THsPrepareTHsZero_06 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_06 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_06 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_06 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_06 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_06 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_06 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_06 1 bit ;StbyRN -SKIP 7 bits - -; MIPI DSI PPS for Panel#1 -$PowerUpDelay_01 16 bits -$DataTurnOnToPanelBacklightEnableDelay_01 16 bits -$BacklightOffToDataTurnOffDelay_01 16 bits -$PowerDownDelay_01 16 bits -$PowerCycleDelay_01 16 bits - -; MIPI DSI PPS for Panel#2 -$PowerUpDelay_02 16 bits -$DataTurnOnToPanelBacklightEnableDelay_02 16 bits -$BacklightOffToDataTurnOffDelay_02 16 bits -$PowerDownDelay_02 16 bits -$PowerCycleDelay_02 16 bits - -; MIPI DSI PPS for Panel#3 -$PowerUpDelay_03 16 bits -$DataTurnOnToPanelBacklightEnableDelay_03 16 bits -$BacklightOffToDataTurnOffDelay_03 16 bits -$PowerDownDelay_03 16 bits -$PowerCycleDelay_03 16 bits - -; MIPI DSI PPS for Panel#4 -$PowerUpDelay_04 16 bits -$DataTurnOnToPanelBacklightEnableDelay_04 16 bits -$BacklightOffToDataTurnOffDelay_04 16 bits -$PowerDownDelay_04 16 bits -$PowerCycleDelay_04 16 bits - -; MIPI DSI PPS for Panel#5 -$PowerUpDelay_05 16 bits -$DataTurnOnToPanelBacklightEnableDelay_05 16 bits -$BacklightOffToDataTurnOffDelay_05 16 bits -$PowerDownDelay_05 16 bits -$PowerCycleDelay_05 16 bits - -; MIPI DSI PPS for Panel#6 -$PowerUpDelay_06 16 bits -$DataTurnOnToPanelBacklightEnableDelay_06 16 bits -$BacklightOffToDataTurnOffDelay_06 16 bits -$PowerDownDelay_06 16 bits -$PowerCycleDelay_06 16 bits - -$Mipi_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 -$Mipi_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 -$Mipi_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 -$Mipi_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 -$Mipi_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 -$Mipi_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 -$Mipi_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 - -$Mipi_PmicI2cBusNo_1 1 byte -$Mipi_PmicI2cBusNo_2 1 byte -$Mipi_PmicI2cBusNo_3 1 byte -$Mipi_PmicI2cBusNo_4 1 byte -$Mipi_PmicI2cBusNo_5 1 byte -$Mipi_PmicI2cBusNo_6 1 byte - -;============================================================================== -; Block 54 - RGB Palette entries -;------------------------------------------------------------------------------ - -SKIP 3 bytes ;Block ID/size -$Enable_Correction 1 bit ;Enable/Disable Gamma Correction -SKIP 7 bits ;Reserved -$Red_Table 256 bytes -$Green_Table 256 bytes -$Blue_Table 256 bytes - -;============================================================================= -; Block 55 - Compression Block -;----------------------------------------------------------------------------- - -$Compression_BlockId 1 byte ; Block ID for block 55 -$Compression_BlockSize 2 bytes ; Block size for block 55 - -$Size_Of_Compression_Struct 2 bytes ; Size of single compression structure - -; Compression Structure 1 -$C1_Minor_Dsc_Version 4 bits ; Minor DSC version -$C1_Major_Dsc_Version 4 bits ; Major DSC version -ALIGN - -$C1_Pps_Identifier 1 byte ; Application specific PPS identifier bits 7:0. -SKIP 1 byte ; Skip 8 reserved bits of PPS identifier field. - -$C1_Line_Buffer_Depth 4 bits ; Line buffer depth used to generate bit stream -$C1_Bits_Per_Component 4 bits ; Bits per component -ALIGN - -$C1_Bits_Per_Pixel_Low 2 bits ; Lower 2 bits of bits per pixel field -$C1_Vbr_Enable 1 bit ; Enable/disable VBR -$C1_422_Enable 1 bit ; Enable/disable 4:2:2 sampling instead of regular 4:4:4 sampling -$C1_Convert_Rgb 1 bit ; Color space RGB or YCoCg-R -$C1_Block_Prediction_Enable 1 bit ; Block prediction enable/disable -SKIP 2 bits ; Skip reserved bits -$C1_Bits_Per_Pixel_High 8 bits ; Higher 8 bits of bits per pixel field -ALIGN - -$C1_Picture_Height 2 bytes ; Picture height in pixels -$C1_Picture_Width 2 bytes ; Picture width in pixels -$C1_Slice_Height 2 bytes ; Slice height in pixels -$C1_Slice_Width 2 bytes ; Slice width in pixels -$C1_Chunk_Size 2 bytes ; Chunk size in bytes - -$C1_Initial_Trans_Delay_Low 2 bits ; Lower 2 bits of initial transmission delay -SKIP 6 bits ; Skip 6 reserved bits -$C1_Initial_Trans_Delay_High 8 bits ; Higher 8 bits of initial transmission delay -ALIGN - -$C1_Initial_Decoder_Delay 2 bytes ; Initial decoder delay - -SKIP 8 bits ; Reserved -$C1_Rc_Xform_Scale_Value 6 bits ; Initial scale value -SKIP 2 bits ; Reserved -ALIGN - -$C1_Scale_Incremental_Value 2 bytes ; Specifies number of group times between incrementing rcXForm scale value - -$C1_Scale_Decremental_Value_Low 4 bits ; Lower nibble for scale decremental value -SKIP 4 bits ; Reserved -$C1_Scale_Decremental_Value_High 8 bits ; Higher 8 bits of scale decremental value -ALIGN - -SKIP 8 bits ; Reserved -$C1_First_Line_Bpg_Offset 5 bits ; Number of additional bits allocated to first line of each group -SKIP 3 bits ; Reserved -ALIGN - -$C1_Nfl_Bpg_Offset 2 bytes ; Number of bits de-allocated for each group after the first line -$C1_Slice_Bpg_Offset 2 bytes ; Number of bits de-allocated for each group to enforce slice constraint -$C1_Initial_Offset 2 bytes ; Initial offset for rcXForm offset -$C1_Final_Offset 2 bytes ; Final offset for rcXForm offset - -$C1_Min_Qp 5 bits ; Minimum Qp at which flatness Qp adjustment is made. -SKIP 3 bits ; Reserved -$C1_Max_Qp 5 bits ; Maximum Qp at which flatness Qp adjustment is made. -SKIP 3 bits ; Reserved -ALIGN - -$C1_Rc_Model_Size 2 bytes ; RC model size - -$C1_Rc_Edge_Factor 4 bits ; Ratio of current vs previous activity to determine the edge -SKIP 4 bits ; Reserved -ALIGN - -$C1_Rc_Quant_Limit_0 5 bits ; Limit 0 of QP threshold used in short term RC -SKIP 3 bits ; Reserved -$C1_Rc_Quant_Limit_1 5 bits ; Limit 1 of QP threshold used in short term RC -SKIP 3 bits ; Reserved -ALIGN - -$C1_Lower_Rc_Target_Offset 4 bits ; Lower offset of RC target -$C1_Upper_Rc_Target_Offset 4 bits ; Upper offset of RC target -ALIGN - -$C1_Rc_Buffer_Threshold_00 1 byte ; RC buffer threshold 0 -$C1_Rc_Buffer_Threshold_01 1 byte ; RC buffer threshold 1 -$C1_Rc_Buffer_Threshold_02 1 byte ; RC buffer threshold 2 -$C1_Rc_Buffer_Threshold_03 1 byte ; RC buffer threshold 3 -$C1_Rc_Buffer_Threshold_04 1 byte ; RC buffer threshold 4 -$C1_Rc_Buffer_Threshold_05 1 byte ; RC buffer threshold 5 -$C1_Rc_Buffer_Threshold_06 1 byte ; RC buffer threshold 6 -$C1_Rc_Buffer_Threshold_07 1 byte ; RC buffer threshold 7 -$C1_Rc_Buffer_Threshold_08 1 byte ; RC buffer threshold 8 -$C1_Rc_Buffer_Threshold_09 1 byte ; RC buffer threshold 9 -$C1_Rc_Buffer_Threshold_10 1 byte ; RC buffer threshold 10 -$C1_Rc_Buffer_Threshold_11 1 byte ; RC buffer threshold 11 -$C1_Rc_Buffer_Threshold_12 1 byte ; RC buffer threshold 12 -$C1_Rc_Buffer_Threshold_13 1 byte ; RC buffer threshold 13 - -$C1_Rc_Range_Parameters 30 bytes ; RC Range parameters[0:14] i.e. 30 bytes total. - -SKIP 40 bytes ; Reserved for future use - -; Compression Structure 2 -$C2_Minor_Dsc_Version 4 bits ; Minor DSC version -$C2_Major_Dsc_Version 4 bits ; Major DSC version -ALIGN - -$C2_Pps_Identifier 2 bytes ; Application specific PPS identifier - -$C2_Line_Buffer_Depth 4 bits ; Line buffer depth used to generate bit stream -$C2_Bits_Per_Component 4 bits ; Bits per component -ALIGN - -$C2_Bits_Per_Pixel_Low 2 bits ; Lower 2 bits of bits per pixel field -$C2_Vbr_Enable 1 bit ; Enable/disable VBR -$C2_422_Enable 1 bit ; Enable/disable 4:2:2 sampling instead of regular 4:4:4 sampling -$C2_Convert_Rgb 1 bit ; Color space RGB or YCoCg-R -$C2_Block_Prediction_Enable 1 bit ; Block prediction enable/disable -SKIP 2 bits ; Skip reserved bits -$C2_Bits_Per_Pixel_High 8 bits ; Higher 8 bits of bits per pixel field -ALIGN - -$C2_Picture_Height 2 bytes ; Picture height in pixels -$C2_Picture_Width 2 bytes ; Picture width in pixels -$C2_Slice_Height 2 bytes ; Slice height in pixels -$C2_Slice_Width 2 bytes ; Slice width in pixels -$C2_Chunk_Size 2 bytes ; Chunk size in bytes - -$C2_Initial_Trans_Delay_Low 2 bits ; Lower 2 bits of initial transmission delay -SKIP 6 bits ; Skip 6 reserved bits -$C2_Initial_Trans_Delay_High 8 bits ; Higher 8 bits of initial transmission delay -ALIGN - -$C2_Initial_Decoder_Delay 2 bytes ; Initial decoder delay - -SKIP 8 bits ; Reserved -$C2_Rc_Xform_Scale_Value 6 bits ; Initial scale value -SKIP 2 bits ; Reserved -ALIGN - -$C2_Scale_Incremental_Value 2 bytes ; Specifies number of group times between incrementing rcXForm scale value - -$C2_Scale_Decremental_Value_Low 4 bits ; Lower nibble for scale decremental value -SKIP 4 bits ; Reserved -$C2_Scale_Decremental_Value_High 8 bits ; Higher 8 bits of scale decremental value -ALIGN - -SKIP 8 bits ; Reserved -$C2_First_Line_Bpg_Offset 5 bits ; Number of additional bits allocated to first line of each group -SKIP 3 bits ; Reserved -ALIGN - -$C2_Nfl_Bpg_Offset 2 bytes ; Number of bits de-allocated for each group after the first line -$C2_Slice_Bpg_Offset 2 bytes ; Number of bits de-allocated for each group to enforce slice constraint -$C2_Initial_Offset 2 bytes ; Initial offset for rcXForm offset -$C2_Final_Offset 2 bytes ; Final offset for rcXForm offset - -$C2_Min_Qp 5 bits ; Minimum Qp at which flatness Qp adjustment is made. -SKIP 3 bits ; Reserved -$C2_Max_Qp 5 bits ; Maximum Qp at which flatness Qp adjustment is made. -SKIP 3 bits ; Reserved -ALIGN - -$C2_Rc_Model_Size 2 bytes ; RC model size - -$C2_Rc_Edge_Factor 4 bits ; Ratio of current vs previous activity to determine the edge -SKIP 4 bits ; Reserved -ALIGN - -$C2_Rc_Quant_Limit_0 5 bits ; Limit 0 of QP threshold used in short term RC -SKIP 3 bits ; Reserved -$C2_Rc_Quant_Limit_1 5 bits ; Limit 1 of QP threshold used in short term RC -SKIP 3 bits ; Reserved -ALIGN - -$C2_Lower_Rc_Target_Offset 4 bits ; Lower offset of RC target -$C2_Upper_Rc_Target_Offset 4 bits ; Upper offset of RC target -ALIGN - -$C2_Rc_Buffer_Threshold_00 1 byte ; RC buffer threshold 0 -$C2_Rc_Buffer_Threshold_01 1 byte ; RC buffer threshold 1 -$C2_Rc_Buffer_Threshold_02 1 byte ; RC buffer threshold 2 -$C2_Rc_Buffer_Threshold_03 1 byte ; RC buffer threshold 3 -$C2_Rc_Buffer_Threshold_04 1 byte ; RC buffer threshold 4 -$C2_Rc_Buffer_Threshold_05 1 byte ; RC buffer threshold 5 -$C2_Rc_Buffer_Threshold_06 1 byte ; RC buffer threshold 6 -$C2_Rc_Buffer_Threshold_07 1 byte ; RC buffer threshold 7 -$C2_Rc_Buffer_Threshold_08 1 byte ; RC buffer threshold 8 -$C2_Rc_Buffer_Threshold_09 1 byte ; RC buffer threshold 9 -$C2_Rc_Buffer_Threshold_10 1 byte ; RC buffer threshold 10 -$C2_Rc_Buffer_Threshold_11 1 byte ; RC buffer threshold 11 -$C2_Rc_Buffer_Threshold_12 1 byte ; RC buffer threshold 12 -$C2_Rc_Buffer_Threshold_13 1 byte ; RC buffer threshold 13 - -$C2_Rc_Range_Parameters 30 bytes ; RC Range parameters[0:14] i.e. 30 bytes total. - -SKIP 40 bytes ; Reserved for future use - -EndStruct - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -; This is the list for the selection of the Device Class -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "Integrated DisplayPort Only" - Selection 0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "Integrated DisplayPort with DVI Compatible" - Selection 0x60D2, "Integrated HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" -EndList - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "HDMI-B" - Selection 0x02, "HDMI-C" - Selection 0x0A, "DisplayPort-A" - Selection 0x07, "DisplayPort-B" - Selection 0x08, "DisplayPort-C" -EndList - -List &LFP_Port_List - Selection 0x0A, "Embedded DisplayPort-A" - Selection 0x15, "MIPI Port A" - ; Selection 0x17, "MIPI Port C" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x40, "DisplayPort-A AUX Channel" - Selection 0x10, "DisplayPort-B AUX Channel" - Selection 0x20, "DisplayPort-C AUX Channel" -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x40, "DisplayPort-A AUX Channel" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x01, "Integrated HDMI-B DDC GPIO Pins" - Selection 0x02, "Integrated HDMI-C DDC GPIO Pins" -EndList - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &LFP_Config_List - Selection 0x0000, "No Local Flat Panel" - Selection 0x1806, "eDP (LFP Driven by Int-DisplayPort Encoder)" - Selection 0x1400, "MIPI" -EndList - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &OS_DriverP_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Persistence Algorithm" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" - Selection 0x03, "36-bit Color Depth" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" - Selection 0x02, "5.40 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &DP_eDP_Link_PreEmp_List - Selection 0x00, "Level-0" - Selection 0x01, "Level-1" - Selection 0x02, "Level-2" - Selection 0x03, "Level-3" -EndList - -List &DP_eDP_Link_VSwing_List - Selection 0x00, "Swing-0" - Selection 0x01, "Swing-1" - Selection 0x02, "Swing-2" - Selection 0x03, "Swing-3" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - #IF ($LFP_Device_Class != 0x1400) - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" - #ENDIF -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x0, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x1, "Default VSwing/Pre-Emphasis Table" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &Blt_Control_Type_List - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - -List &Hdmi_LS_List - - Selection 0x00, "400mV 0.0dB Level Shifter" - Selection 0x01, "400mV 3.5dB Level Shifter" - Selection 0x02, "400mV 6.0dB Level Shifter" - Selection 0x03, "400mV 9.5dB Level Shifter" - Selection 0x04, "600mV 0.0dB Level Shifter" - Selection 0x05, "600mV 3.5dB Level Shifter" - Selection 0x06, "600mV 6.0dB Level Shifter" - Selection 0x07, "800mV 0.0dB Level Shifter" - Selection 0x08, "800mV 3.5dB Level Shifter" - Selection 0x09, "1200mV 0.0dB Level Shifter" -EndList - -List &DisplayList - Selection 0x08, "LFP" - Selection 0x04, "EFP1" - Selection 0x40, "EFP2" - Selection 0x20, "EFP3" - Selection 0x00, "None" -EndList - -List &Dither_Select_Bit - Selection 0, "Dithering in Panel controller" - Selection 1, "Dithering in Display Controller" -EndList - -List &MIPI_Bridge_Ref_Clock_List - Selection 0, "19.2" - Selection 1, "26" -EndList - -List &Panel_Identifier_List - Selection 0x0, "Use Sequence Block" - Selection 0x1, "MIPI DSI Panel-1" - Selection 0x2, "MIPI DSI Panel-2" - Selection 0x3, "MIPI DSI Panel-3" - Selection 0x4, "MIPI DSI Panel-4" - Selection 0x5, "MIPI DSI Panel-5" - Selection 0x6, "MIPI DSI Panel-6" -EndList - -List &Panel_Type_List - Selection 0, "Native MIPI DSI" - Selection 1, "MIPI DSI to LVDS Bridge" -EndList - -List &MIPI_DSI_Panel_Architecture_Type_List - Selection 0x0, "Type 1" - Selection 0x1, "Type 2" - Selection 0x2, "Type 3" - Selection 0x3, "Type 4" -EndList - -List &Video_Command_Mode_List - Selection 0, "Video Mode" - Selection 1, "Command Mode" -EndList - -List &Packet_Sequence_Video_Mode_List - ;Selection 0x0, "Reserved" - Selection 0x1, "Non-burst with sync pulse" - Selection 0x2, "Non-burst with sync events" - Selection 0x3, "Burst Mode" -EndList - -List &Colour_Format_Video_Mode_List - Selection 0x1, "RGB565" - Selection 0x2, "RGB666" - Selection 0x3, "RGB 666(Loosely Packed Format)" - Selection 0x4, "RGB888" -EndList - -List &Panel_Rotation_List - Selection 0x0, "0 degree" - Selection 0x1, "90 degree" - Selection 0x2, "180 degree" - Selection 0x3, "270 degree" -EndList - -List &Enable_Disable_List - Selection 0, "Enable" - Selection 1, "Disable" -EndList - -List &EscapeClk_List - Selection 0x0, "20 MHz" - Selection 0x1, "10 MHz" - Selection 0x2, "5 MHz" - ;Selection 0x3, "Undefined" -EndList - -List &DPhyParamFlag_List - Selection 0, "Dphy Param is not valid" - Selection 1, "Dphy Param is valid" -EndList - -List &MIPI_DSI_Panel_Color_Depth_List - Selection 0x0, "18Bpp" - Selection 0x1, "24Bpp" -EndList - -List &Lane_Count_List - Selection 0x0, "1" - Selection 0x1, "2" - Selection 0x2, "3" - Selection 0x3, "4" -EndList - -List &Dual_Link_List - Selection 0x0, "Dual Link Not Supported" - Selection 0x1, "Dual Link Front Back Mode" - Selection 0x2, "Dual Link Pixel Alternative Mode" - ;Selection 0x3, "Reserved" -EndList - -List &Pixel_Overlap_Count - Selection 0x0, "Zero Pixel Overlap" - Selection 0x1, "One Pixel Overlap" - Selection 0x2, "Two Pixels Overlap" - Selection 0x3, "Three Pixels Overlap" - Selection 0x4, "Four Pixels Overlap" - Selection 0x5, "Five Pixels Overlap" - Selection 0x6, "Six Pixels Overlap" - Selection 0x7, "Seven Pixels Overlap" -EndList - -List &Mipi_Port_List - Selection 0x0, "MIPI PortA" - Selection 0x1, "MIPI PortC" - Selection 0x2, "Both MIPI PortA and PortC" - ;Selection 0x3, "Reserved" -EndList - -List &RgbFlip - Selection 0x0, "RGB Panel" - Selection 0x1, "BGR Panel" -EndList - -List &Pwm_Source_List - ; Selection 0x0, "PWM From PMIC" - ; Selection 0x1, "PWM From LPSS" - Selection 0x2, "PWM From Display Engine" - Selection 0x3, "PWM From LCD Panel" - Selection 0x4, "Panel driver interface" -EndList - -List &Pwm_Controller_List - Selection 0x0, "PWM0" - Selection 0x1, "PWM1" - ;Selection 0x2, "PWM2" - ;Selection 0x3, "PWM3" -EndList - -List &wait_line_link - Selection 0x00, "0 lines to wait" - Selection 0x01, "2 lines to wait" - Selection 0x02, "4 lines to wait" - Selection 0x03, "8 lines to wait" -EndList - -List &PmicSocSelection_List - Selection 0x0, "From PMIC" - Selection 0x1, "From SoC" -EndList - -List &Hdmi2SupportOptions - Selection 0x00, "Disabled" - Selection 0x01, "Enabled" -EndList - -List &PsrWakeupTimeOptions - Selection 0x00, "500 usec" - Selection 0x01, "100 usec" - Selection 0x02, "2.5 msec" - Selection 0x03, "0 (Skip)" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock -PPVer "3.00" -Image EOF Thru EOF At EOF -EndInfoBlock - -;============================================================================== -; Page - Revision History -;------------------------------------------------------------------------------ -Page "VBT Information" - Title "PLATFORM : Broxton" - Title "VBT version: 207" - - #IF ($LFP_Device_Class == 0x1806) - Title "Supported LFP type: eDP" - #ELSEIF ($LFP_Device_Class == 0x1400) - Title "Supported LFP type: MIPI" - #ELSE - Title "Supported LFP type: No LFP" - #ENDIF -EndPage ; Revision History - -;============================================================================== -; Page - General Platform Configuration -;------------------------------------------------------------------------------ -Page "General Platform Configuration" - - Combo $Embedded_Platform, "Embedded Platform: ", &No_Yes_List, - Help "This feature allows a selectable option to determine whether " - "the platform is embedded design or not." - - Combo $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List, - Help "Enabling this feature configures optimal CD Clock frequency at run time .\n " - - Combo $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List, - Help "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n" - "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n" - "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n" - "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default." - -EndPage ; General platform Configuration - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ -Page "UEFI GOP Driver Configuration" - - Combo $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List, - Help "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver." - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - ;============================================================================== - ; Page - Child Device List - ;------------------------------------------------------------------------------ - - Page "Child Device List" - Link "Close Table" , ".." - Title "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" - - Title "Child Device 1" - Combo $ChildDevice1Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "\tPrimary display: " , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, "\tSecondary display: " , &DisplayList, - Help "Secondary Display\r\n" - EndPage ; "Child Device List" - - ;============================================================================ - ; Page - Fixed Mode Configuration - ;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set." - "This field specifies if user wants to enable/disable the feature." - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode." - "It should be always less than or equal to the native horizontal resolution." - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode." - "It should be always less than or equal to the native vertical resolution." - - EndPage - -EndPage ; "UEFI GOP Driver Configuration" - -;============================================================================ -; Page - OS Graphics driver Configuration -;---------------------------------------------------------------------------- -Page "OS Graphics driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, " VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version number. " - "The permissible values for VBT Customization version is from 0 to 255." - - Combo $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List, - Help "This option allows windows driver to be aware that display subsystem is not needed. " - "Driver could choose not to activate any display hardware if this bit is set. " - "However this is only valid if there’s no LFP on the system or no Force projectable connector. " - "Please see driver documentation for detailed driver behaviour." - - EndPage ; General Features" - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. " - "When the option is set to Yes, the feature will be enabled and CUI will show " - "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, " - "the complete 'Maintain Aspect Ratio' feature will be disabled." - - Title "Legacy Monitor Mode Limit:" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of horizontal active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is specified by " - "a maximum number of vertical active pixels.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz.\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC available." - - Title "Rotation Configuration:" - - Combo $Rot_Enable, " Enable Rotation:", &No_Yes_List, - Help "This feature when set to yes, will allow for rotation. " - "Otherwise, when the feature is set to no, " - "the rotation functionality will be disabled within the driver." - - Title "HPD Wake:" - - Combo $HPD_Wake, " HPD wake source from S0ix/DC9", &Disabled_Enabled_List, - Help "This feature enables HPD events like Hotplug/unplug as a wake up source from S0ix/DC9" - " in supported platforms. Based on the bit configuration, h/w and f/w routes the HPD interrupt" - " to the OS/driver. The behavior (whether to wake the system from S0ix/DC9 or not)is controlled by display driver." - - EndPage ; Display features - - Page "Power Conservation" - Link "Close Table" , ".." - - Title " " - - Combo $PC_Fields_Enable, " PC Features Control Options", &Disabled_Enabled_List, - Help "This feature determines the validity of the following PC Features Control Options.\r\n\r\n" - "1. Intel® Rapid Memory Power Management (RMPM)\r\n" - "2. Intel® Smart 2D Display Technology (S2DDT)\r\n" - "3. Intel® Display Power Saving Technology (DPST) (Mobile only)\r\n" - "4. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n" - "5. Intel® Automatic Display Brightness (ADB) (Mobile only)\r\n" - "6. Intel® Display Refresh Rate Switching (DRRS) (Mobile only)\r\n" - "7. Graphics Render Standby (RS)\r\n" - "8. Intel® Turbo Boost Technology\r\n" - "9. Dynamic Frames Per Second (DFPS)\r\n" - "10. Dynamic Media Refresh Rate Switching (DMRRS)\r\n" - "11. Assertive Display Technology (ADT)\r\n\r\n" - "Note: Enable and Save the changes to display all the PC Features Control Options\r\n" - - Combo $PM_RMPM_Enable, "\tIntel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be enabled. " - - Combo $PM_S2DDT_Enable, "\tIntel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be enabled. " - - Combo $PM_DPST_Enable, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. " - "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system is running in battery mode and " - "the LFP is the only active display device." - - Combo $BIA_Aggress_Level, "\t\tDPST Aggressiveness Level (Mobile only)", &Pwr_Pref_List, - Help "This feature defines the Intel® Display Power Saving Technology aggressiveness level if and only if " - "the feature Intel® Display Power Saving Technology is enabled." - "\r\n\r\nThe following are the definitions for each level:" - "\r\n1 - Maximum Quality - shall use no DPST " - "\r\n2 - Provides the user the maximum brightness for their embedded Local Flat Panel (LFP)while DPST is in use" - "\r\n3 - This level defines maximum amount of brightness with minimal power savings" - "\r\n4 - This level defines an intermediate value for brightness amount" - "\r\n5 - This level defines an intermediate value for the brightness amount" - "\r\n6 - Maximum Battery - Provided the user with the minimum amount of " - "brightness capable for their LFP with the maximum power savings" - - Combo $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List, - Help "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. " - - Combo $PM_ADB_Enable, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Automatic Display Brightness is to be enabled. " - "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) " - "depending on the current ambient light environment. " - "When enabled, the driver and VBIOS will control the backlight brightness of the LFP " - "depending on the ambient environment if and only if the LFP is the only active display. " - "When disabled, the driver will perform no action." - - Link "ADB Response Data (Mobile only)" , "ADB Response Data (Mobile only)" - - Combo $PM_DRRS_Enable, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled." - - Combo $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List, - Help "This feature determines whether Graphics Render Standby (RS)is to be enabled." - - Combo $PM_Turbo_Enable, "\tIntel® Turbo Boost Technology", &Disabled_Enabled_List, - Help "This feature determines whether Intel® Turbo Boost Technology is to be enabled." - - Combo $Panel_Self_Refresh, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled." - - Combo $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Frames Per Second is to be enabled." - - Combo $DMRRS, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic media refresh rate switching is to be enabled." - - Combo $ADT, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List, - Help "This feature determines whether Assertive display technology is to be enabled. " - - Page "ADB Response Data (Mobile only)" - Link "Close Table" , ".." - - Table $ALS_Response_Data " ADB Response Data (Mobile only)", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation details such as sensor placement and optics. " - "Up to five points can be specified, where each point indicates a given ambient light illuminance " - "to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light illuminance (lux). " - "A minimum of two points are required (min and max)." - EndPage ; "ADB Response Data" - EndPage ; Power Conservation -EndPage ; "OS Graphics driver Configuration" - -;============================================================================== -; Page - Display Configurations -;------------------------------------------------------------------------------ -Page "Integrated Display Configuration" - Title "Integrated DP, HDMI, DVI, eDP Configuration" - - Link "LFP Configuration", "LFP Configuration" - Link "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors" - - ;============================================================================== - ; Page - LFP Configuration - ;---------------------------------------------------------------------------- - - Page "LFP Configuration" - Link "Close Table", ".." - Combo $LFP_Device_Class , "Active Local Flat Panel Configuration (Save The Configuration After Selecting This Field):", &LFP_Config_List, - Help "This feature is for configuring LFP type. Save the configuration after selecting this field to see display related settings." - "\r\n Note: For desktop platforms, eDP supported only on Port D" - - Combo $LFP_Port, "Select Output Port:", &LFP_Port_List, - Help "This feature, when enabled, will activate support for an eDP " - "Driver also uses the same data for enabling eDP on the selected port.\r\n" - "Note: Do not enable any other digital ports on the same Port as eDP." - - #IF ($LFP_Device_Class == 0x1806) - Combo $Int_LFP_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for embedded-DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - Combo $HPD1_Inversion_Enable, "HPD Inversion:", &Disabled_Enabled_List, - Help "This feature when enabled, will enable HPD inversion for Selected Port" - #ENDIF - - Title " " - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "This feature selects the Local Flat Panel (LFP) the GOP and driver is to enable.\r\n\r\n" - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LFP\r\n" - "\tPANEL #02: 800x600 LFP\r\n" - "\tPANEL #03: 1024x768 LFP\r\n" - "\tPANEL #04: 1280x1024 LFP\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n" - #IF ($LFP_Device_Class != 0x1400) - "\tPANEL #07: 1600x1200 LFP\r\n" - "\tPANEL #08: 1280x768 LFP\r\n" - "\tPANEL #09: 1680x1050 LFP\r\n" - "\tPANEL #10: 1920x1200 LFP\r\n" - "\tPANEL #11: 1440x900 LFP\r\n" - "\tPANEL #12: 1600x900 LFP\r\n" - "\tPANEL #13: 1024x768 LFP\r\n" - "\tPANEL #14: 1280x800 LFP\r\n" - "\tPANEL #15: 1920x6108 LFP\r\n" - "\tPANEL #16: 2048x1536" - #ENDIF - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP with an EDID. " - "The GOP and driver will load the EDID and " - "use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and " - "other methods will be used to set panel timing." - - Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List, - Help "This feature when set to yes, will enable 180 Degree rotation " - "otherwise, the rotation functionality will be disabled." - - #IF ($LFP_Device_Class == 0x1806) - Combo $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for Selected Port " - Combo $Enable_Correction, "Gamma/Brightness/Contrast Correction Enable:", &Disabled_Enabled_List, - Help "This option will allow users to disable/enable Gamma/Brightness/Contrast correction feature for eDP. By default it will be disabled.\r\n" - "On enabling one can find option for entering values for Red/Blue/Green Palette Table under LFP Panel configuration.\r\n" - "Each Red/Blue/Green Palette Table has 256 entries/rows of 1-byte each. Enter required values in these fields.\r\n" - #ENDIF - - Title " " - - Link "Panel #01 ", "Panel #01 " - Link "Panel #02 ", "Panel #02 " - Link "Panel #03 ", "Panel #03 " - Link "Panel #04 ", "Panel #04 " - Link "Panel #05 ", "Panel #05 " - Link "Panel #06 ", "Panel #06 " - #IF ($LFP_Device_Class != 0x1400) - Link "Panel #07 ", "Panel #07 " - Link "Panel #08 ", "Panel #08 " - Link "Panel #09 ", "Panel #09 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - #IF($Enable_Correction == 1) - Link "RGB Palette Table ", "RGB Palette Table " - #ENDIF - #ENDIF - - ;============================================================================== - ; Page - Panel #01 (640x480) Flat Panel parameters - ;------------------------------------------------------------------------------ - - Page "Panel #01 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_01, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VswingPreEmph_1, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_01, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_01, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_01, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_01, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_01, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_01, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_01, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_01, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_01, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_01, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_01, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_01, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_01, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_01, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_01, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_01, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_01, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_01, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_01, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_01, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_01, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_01, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_01, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_01, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_01, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_01, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_01, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_01, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_01, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_01, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_01, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_01, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_01, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_01, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_01, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_01, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_01, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_01, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_01, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_01, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_01, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_01, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_01, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_01, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_01, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_01, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_01, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_01, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_01, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_01, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_01, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_01, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_01, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_01, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_01, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_01, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_01, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_01, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_01, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_01, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_01, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_01, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_01, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - - EndPage - - ;============================================================================== - ; Page - Panel #02 (800x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #02 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_02, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VswingPreEmph_2, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_02, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_02, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_02, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_02, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_02, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_02, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_02, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_02, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_02, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_02, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_02, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_02, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_02, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_02, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_02, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_02, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_02, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_02, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_02, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_02, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_02, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_02, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_02, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_02, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_02, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_02, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_02, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_02, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_02, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_02, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_02, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_02, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_02, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_02, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_02, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_02, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_02, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_02, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_02, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_02, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_02, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_02, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_02, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_02, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_02, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_02, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_02, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_02, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_02, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_02, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_02, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_02, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_02, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_02, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_02, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_02, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_02, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_02, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_02, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_02, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_02, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_02, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_02, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - EndPage - - ;============================================================================== - ; Page - Panel #03 (1024x768 LFP) Flat Panel parameters - ;------------------------------------------------------------------------------ - - Page "Panel #03 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_03, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VswingPreEmph_3, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_03, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_03, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_03, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_03, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_03, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_03, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_03, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_03, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_03, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_03, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_03, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_03, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_03, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_03, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_03, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_03, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_03, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_03, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_03, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_03, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_03, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_03, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_03, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_03, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_03, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_03, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_03, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_03, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_03, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_03, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_03, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_03, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_03, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_03, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_03, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_03, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_03, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_03, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_03, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_03, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_03, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_03, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_03, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_03, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_03, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_03, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_03, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_03, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_03, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_03, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_03, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_03, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_03, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_03, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_03, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_03, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_03, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_03, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_03, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_03, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_03, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_03, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_03, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - EndPage - - ;============================================================================== - ; Page - Panel #04 (1280x1024 LFP) Flat Panel parameters - ;------------------------------------------------------------------------------ - - Page "Panel #04 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_04, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VswingPreEmph_4, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_04, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_04, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_04, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_04, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_04, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_04, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_04, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_04, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_04, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_04, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_04, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_04, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_04, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_04, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_04, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_04, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_04, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_04, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_04, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_04, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_04, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_04, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_04, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_04, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_04, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_04, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_04, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_04, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_04, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_04, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_04, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_04, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_04, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_04, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_04, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_04, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_04, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_04, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_04, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_04, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_04, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_04, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_04, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_04, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_04, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_04, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_04, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_04, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_04, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_04, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_04, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_04, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_04, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_04, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_04, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_04, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_04, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_04, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_04, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_04, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_04, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_04, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - EndPage - - ;============================================================================== - ; Page - Panel #05 (1400x1050 LFP - Reduced Blank) Flat Panel parameters - ;------------------------------------------------------------------------------ - - Page "Panel #05 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_05, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VswingPreEmph_5, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_05, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_05, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_05, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_05, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_05, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_05, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_05, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_05, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_05, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_05, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_05, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_05, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_05, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_05, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_05, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_05, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_05, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_05, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_05, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_05, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_05, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_05, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_05, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_05, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_05, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_05, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_05, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_05, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_05, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_05, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_05, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_05, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_05, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_05, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_05, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_05, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_05, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_05, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_05, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_05, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_05, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_05, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_05, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_05, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_05, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_05, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_05, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_05, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_05, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_05, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_05, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_05, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_05, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_05, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_05, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_05, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_05, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_05, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_05, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_05, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_05, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_05, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - - EndPage - - ;============================================================================== - ; Page - Panel #06 (1400x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - - Page "Panel #06 " - TitleB "Common LFP Features" - EditText $Panel_Name_06, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #IF ($LFP_Device_Class == 0x1400) - TitleB "Integrated MIPI DSI Settings" - Link "MIPI Display Settings" , "MIPI Display Settings" - #ENDIF - - #IF ($LFP_Device_Class == 0x1806) - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_6, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_06, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_06, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - #ENDIF - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_06, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_06, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_06, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_06, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_06, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_06, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_06, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_06, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_06, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_06, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_06, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_06, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - #IF ($LFP_Device_Class == 0x1400) - Page "MIPI Display Settings" - - Link "Close Table" , ".." - - TitleB "MIPI DSI Controller Configuration Settings" - - ;Combo $PanelIdentifier_06, "\tPanel Identifier:", &Panel_Identifier_List, - ;Help "This feature is used to select MIPI DSI Panel Identifier" - - Combo $Video_Command_Mode_06, "\tVideo/Command Mode:", &Video_Command_Mode_List, - Help "This feature helps in selecting Video/Command Mode." - - Combo $Packet_Sequence_Video_Mode_06, "\tPacket Sequence For Video Mode:", &Packet_Sequence_Video_Mode_List, - Help "This feature helps in selecting packet sequence for Video Mode.\n" - "Non-burst with sync pulse\n" - "Non-burst with sync events\n" - "Burst mode" - - EditNum $RequiredBurstModeRate_06, "\tRequired Burst Mode Rate (in Kbps):", DEC, - Help "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\n" - "This value is valid only if packet sequence for video mode is Burst Mode." - - Combo $Colour_Format_Video_Mode_06, "\tColour Format In Video Mode:", &Colour_Format_Video_Mode_List, - Help "This feature helps in selecting supported colour format in Video Mode." - - Combo $Dual_Link_06, "\tDual Link Support:", &Dual_Link_List, - Help "This feature allows to select type of dual link." - - Combo $Pixel_Overlap_Count_06, "\tPixel Overlap Count(Z-Inversion):", &Pixel_Overlap_Count, - Help "Select the number of Pixels to be overlapped per half of Scanline while using\n" - "MIPI Dual Link Front-Back video mode." - - Combo $CABC_Support_06, "\tCABC Support:", &Disabled_Enabled_List, - Help "This feature helps in selecting CABC_Support." - - Combo $CabcCmdsPort_06, "\tCABC On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $PanelPwmCmdsPort_06, "\tPanel PWM/BkltController On/Off Commands:", &Mipi_Port_List, - Help "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\n" - "This field is ignored in single link MIPI case" - - Combo $RgbFlip_06, "\tRGB/BGR Panel Selection", &RgbFlip, - Help "Select if the panel is RGB or BGR\n" - - Combo $Number_Of_Lanes_06, "\tNumber Of Data Lanes:", &Lane_Count_List, - Help "This feature allows to select number of data lanes going to use for MIPI DSI" - - ;Combo $Panel_Rotation_06, "\tPanel Rotation:", &Panel_Rotation_List, - ;Help "Select the degree of panel rotation" - - Combo $Bta_Disable_06, "\tSending Bus Turn Around (BTA):", &Enable_Disable_List, - Help "Enable or Disable sending Bus Turn Around to the Peripheral" - - ;EditNum $DsiDDRClock_06, "\tDSI DDR Clock:", DEC, - ;Help "This feature allows to enter MIPI DSI DDR Clock in KHz.\n" - ; "If 0, driver will calculate from panel timings." - - Combo $EscapeClk_06, "\tEscape Clock:", &EscapeClk_List, - Help "This feature helps to select frequency of Escape Clk." - - Combo $EoTpSupport_06, "\tEoT Packet Transmission:", &Enable_Disable_List, - Help "This feature helps to either enable or disable EoT packet Transmission" - - Combo $ClockStop_06, "\tClock Stop Feature:", &Disabled_Enabled_List, - Help "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode" - - ;Combo $DPhyParamFlag_06, "\tDPhyParamFlag:", &DPhyParamFlag_List, - ;Help "This feature helps to select whether DPhyParamFlag is valid or not valid" - - ;EditNum $HsTxTimeOut_06, "\tHS Transmission Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI HS Transmission Time Out Counter in ByteClocks." - - ;EditNum $LpRxTimeOut_06, "\tLP Reception Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI LP Reception Time Out Counter in TxEscClk." - - ;EditNum $TurnAroundTimeOut_06, "\tBus Turn Around Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Bus Turn Around Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0xF clock cycles and maximum value is 0x14 clock cycles" - - ;EditNum $DeviceResetTimer_06, "\tDevice Reset Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Device Reset Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x15 clock cycles and maximum value is 0xFFFF clock cycles" - - ;EditNum $MasterInitTimer_06, "\tDSI Host Controller Initialization Time Out Counter:", HEX, - ;Help "This feature allows to enter MIPI DSI Host Controller Initialization Time Out Counter in TxEscClk.\n" - ; "Minimum value is 0x7D0 clock cycles and maximum value is 0x4E20 clock cycles" - - ;EditNum $LpByteClkRegValue_06, "\tLpByteClk Register:", HEX, - ;Help "This feature allows to enter LpByteClk Register." - - ;EditNum $DphyParamRegValue_06, "\tDphyParamReg Register:", HEX, - ;Help "This feature allows to enter DphyParamReg Register." - - ;EditNum $ClkLaneSwitchingTimeCount_06, "\tClkLaneSwitchingTimeCount Register:", HEX, - ;Help "This feature allows to enter ClkLaneSwitchingTimeCount Register." - - ;EditNum $HighLowSwitchCount_06, "\tHighLowSwitchCount Register:", HEX, - ;Help "This feature allows to enter HighLowSwitchCount Register." - - EditNum $TClkPrepare_06, "\tTClkPrepare:", DEC, - Help "This feature allows to enter TClkPrepare in ns." - - EditNum $TClkTrail_06, "\tTClkTrail:", DEC, - Help "This feature allows to enter TClkTrail in ns." - - EditNum $TClkPrepareTClkZero_06, "\tTClkPrepare + TClkZero:", DEC, - Help "This feature allows to enter TClkPrepare + TClkZero in ns." - - EditNum $THsPrepare_06, "\tTHsPrepare:", DEC, - Help "This feature allows to enter THsPrepare in ns." - - EditNum $THsTrail_06, "\tTHsTrail:", DEC, - Help "This feature allows to enter THsTrail in ns." - - EditNum $THsPrepareTHsZero_06, "\tTHsPrepare + THsZero:", DEC, - Help "This feature allows to enter THsPrepare + THsZero in ns." - - ;Combo $PanelEnable_06, "\tPanel_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Panel_Enable GPIO" - - ;Combo $BkltEnable_06, "\tBacklight_Enable GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable Backlight_Enable GPIO" - - ;Combo $PWMEnable_06, "\tPWM_Enable GPIO", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable PWM_Enable GPIO" - - ;Combo $RstRN_06, "\tRstRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable RESET_R_N GPIO" - - ;Combo $PwrDownR_06, "\tPwrDownR GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable POWER_DOWN_R GPIO" - - ;Combo $StbyRN_06, "\tStbyRN GPIO:", &Disabled_Enabled_List, - ;Help "This feature allows to either disable or enable STBY_R_N GPIO" - - TitleB "MIPI DSI Panel Power On/Off Sequence(delays)\n" - - EditNum $PowerUpDelay_06, "\tPower-Up Delay:", DEC, - Help "Delay to be given after panel power up in 100uS\n" - "\r\n" - - EditNum $DataTurnOnToPanelBacklightEnableDelay_06, "\tData Turn-On To Panel Backlight Enable Delay:", DEC, - Help "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS\n" - "\r\n" - - EditNum $Mipi_PwmOn_To_Bklt_Enable_Delay_06, "\tPwm-On To Backlight Enable Delay:", DEC, - Help "Delay to be given after PWM-On and before Backlight Enable in 100uS\n" - "Delay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.\r\n" - - EditNum $Mipi_Bklt_Disable_To_PwmOff_Delay_06, "\tBacklight Disable To Pwm-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.\r\n" - - EditNum $BacklightOffToDataTurnOffDelay_06, "\tBacklight Disable To Data Turn-Off Delay:", DEC, - Help "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS\n" - "\r\n" - - EditNum $PowerDownDelay_06, "\tPower-Down Delay:", DEC, - Help "Delay to be given before panel power down in 100uS\n" - "\r\n" - - EditNum $PowerCycleDelay_06, "\tPower-Cycle Delay:", DEC, - Help "Delay to be given before panel power up and after panel power down in 100uS\n" - "\r\n" - - ;TitleB "MIPI DSI Board Configuration Settings" - - ;Combo $PmicSocSelection_06, "\tSelect PMIC or SoC:", &PmicSocSelection_List, - ;Help "This feature allows to select the PANEL_EN, BACKLIGHT_EN, PWM lines are coming either from PMIC or SoC" - - EndPage - #ENDIF - - EndPage - - ; - ; Panel#7 to Panel#16 are not shown in BMP UI for MIPI panels - ; - #IF ($LFP_Device_Class != 0x1400) - ;============================================================================== - ; Page - Panel #07 (1600x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #07 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_07, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - TitleB " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_7, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_07, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_07, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_07, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_07, " Red_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_07, " Blue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_07, " Red_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_07, " Red_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_07, " Green_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_07, " Green_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_07, " Blue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_07, " Blue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_07, " White_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_07, " White_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_07, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - - Combo $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_07, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #08 (1280x768) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #08 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_08, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_8, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_08, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_08, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_08, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_08, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_08, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #09 (1680x1050) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #09 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_09, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_9, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_09, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_09, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_09, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_09, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_09, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #10 (1920x1200) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #10 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_10, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_10, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_10, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_10, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_10, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_10, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #11 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #11 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_11, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_11, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_11, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_11, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_11, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_11, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_11, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #12 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #12 " - TitleB "Common LFP Features" - - EditText $Panel_Name_12, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_12, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_12, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_12, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_12, "Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_12, "Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, "Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_12, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_12, " TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_12, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #13 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #13 " - TitleB "Common LFP Features" - - EditText $Panel_Name_13, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_13, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_13, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_13, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_13, "Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_13, "Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, "Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_13, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_13, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #14 (1280x800) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #14 " - TitleB "Common LFP Features" - - EditText $Panel_Name_14, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features" - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_14, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_14, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_14, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_14, "Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_14, "Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, "Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_14, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_14, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #15 (1280x600) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #15 " - TitleB "Common LFP Features" - - EditText $Panel_Name_15, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_15, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_15, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_15, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_15, "Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_15, "Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, "Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_15, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_15, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage - - ;============================================================================== - ; Page - Panel #16 (Reserved) Flat Panel parameters - ;------------------------------------------------------------------------------ - Page "Panel #16 " - TitleB "Common LFP Features" - - EditText $Panel_Name_16, "\tLFP Panel Name:", - Help "This feature defines the LFP panel name, used by driver only. " - "Panel name can be only of 13 characters maximum and rest of the characters will be truncated." - - Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature " - "by taking the Horizontal and Vertical resolution from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolution for this panel." - - TitleB "\tDPS Panel Type Features " - Combo $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n" - "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n" - "SDRRS:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience.\r\n" - "Seamless:- Allows power savings when on battery mode and " - "when a lower refresh rate will not adversely impact the user experience." - "Implements seamless refresh rate switching, which eliminates the screen blink that occurred " - "during the refresh rate transitions" - - EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - TitleB "\tBackLight Technology Type Features " - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "DTD Timings Table" , "DTD Timings" - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - TitleB "Integrated eDP Settings" - Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters" - Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing" - Link "PSR feature" ,"PSR feature" - Link "Apical Feature" , "Apical Feature" - - Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used." - - Combo $eDP_VswingPreEmph_16, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For Broxton, based on the selection respective table will be used.\r\n" - "Tables for Broxton: \r\n" - "Low Power VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\n" - "Voltage \t\t Level-0/200mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 4db \t\t 200mV, 6db \n" - "Swing \t\t Level-1/250mV \t\t 250mV, 0db \t\t 250mV, 1.5db \t\t 250mV, 4db \t\t N/A\n" - "(mV) \t\t Level-2/300mV \t\t 300mV, 0db \t\t 300mV, 1.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/350mV \t\t 350mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - "\r\n\r\n" - - "Default VSwing Pre-Emphasis Setting Table:\n" - "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n" - " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n" - "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n" - "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n" - "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n" - "\t\t Level-3/1200mV \t\t 1200mV, 0db \t\t N/A \t\t\t N/A \t\t\t N/A\n" - - Combo $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Page "Panel Power Sequencing" - Link "Close Table", ".." - - ;Combo $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List, - ;Help "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n" - ; "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n" - ; "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n" - ; "Note: This option is only applicable for Windows Graphics driver." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - EndPage - - Page "DTD Timings" - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters related to the LFP. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage - - Page "LFP PnP ID" - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor/Product ID " - "starting at offset 08h to be used as a PnP ID.\r\n\r\n" - " Table Definition:\r\n" - " \tWord: ID Manufacturer Name\r\n" - " \tWord: ID Product Code\r\n" - " \tDWord: ID Serial Number\r\n" - " \tByte: Week of Manufacture\r\n" - " \tByte: Year of Manufacture" - EndPage - - Page "Backlight Control Parameters" - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the Backlight Inverter type " - "that is to be used to control the backlight brightness of the LFP. \r\n" - "When PWM is selected, the driver and VBIOS will control the backlight brightness " - "via the integrated PWM solution for the applicable chipsets. \r\n" - "When None/External is selected, the system BIOS will control the backlight brightness " - "via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $Lfp_Pwm_Controller_Selection_16, " Pwm Controller Selection:", &Pwm_Controller_List, - Help "This field allows to select the PWM Controller to be used " - "for the selected Local Flat Panel.\r\n" - - Combo $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity to be specified.\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, "Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum backlight brightness setting. " - "The graphics driver will never decrease the backlight less than this value. " - "The value must be specified using normal polarity semantics." - - EditNum $POST_BL_Brightness_16, "POST Brightness:", DEC, - Help "This feature is used only by video BIOS to set initial brightness level at POST.\r\n" - "This is configurable field of 0-255. " - "Value of 0 indicates Zero brightness, 255 indicates maximum brightness." - - EditNum $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n" - "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - - EditNum $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - - EditNum $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - - EditNum $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX, - Help " Bits 9:2 of red color x coordinate" - - EditNum $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX, - Help " Bits 9:2 of red color y coordinate" - - EditNum $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX, - Help " Bits 9:2 of Green color x coordinate" - - EditNum $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX, - Help " Bits 9:2 of Green color y coordinate" - - EditNum $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX, - Help " Bits 9:2 of Blue color x coordinate" - - EditNum $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX, - Help " Bits 9:2 of Blue color y coordinate" - - EditNum $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX, - Help " Bits 9:2 of White color x coordinate" - - EditNum $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX, - Help " Bits 9:2 of White color y coordinate" - EndPage ; Chromaticity Control - - Page "eDP Fast Link Training Configuration Parameters" - Link "Close Table" , ".." - - Combo $eDP_Fast_Link_Training_Supported_16, "Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled." - - Combo $eDP_Link_DataRate_16, "Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the Data Rate for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, "Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, " Pre-Emphasis:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_Vswing_16, " Voltage Swing:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of the Voltage Swing value for the embedded DP link. " - "It will be used if the sink indicates that no aux handshake is required during link training." - EndPage - - Page "PSR feature" - Link "Close Table" , ".." - - Combo $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List, - Help "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state." - - Combo $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List, - Help "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used." - - Combo $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link, - Help "This field determines Lines to wait before link standby \n" - " 0 lines to wait (Default)\r\n" - " 2 lines to wait\r\n" - " 4 lines to wait\r\n" - " 8 lines to wait\r\n" - " Others Reserved" - - EditNum $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC, - Help "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0." - - Combo $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n" - - Combo $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions, - Help "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n" - EndPage ; PSR feature - - Page "Apical Feature" - Link "Close Table" , ".." - Combo $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List, - Help "This field enables/disables the Apical Assertive Display IP for this panel." - - EditNum $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX, - Help "This field specifies the Apical IP specific Panel OUI field." - - EditNum $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX, - Help "This field specifies the Apical IP specific DPCD base address field." - - EditNum $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX, - Help "This field specifies the Apical IP specific DPCD Irdidix control 0 field." - - EditNum $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX, - Help "This field specifies the Apical IP specific DPCD option select field." - - EditNum $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX, - Help "This field specifies the Apical IP specific backlight value." - - EditNum $eDP_Ambient_Light_16, "\tAmbient Light", EHEX, - Help "This field specifies the Apical IP specific Ambient light value." - - EditNum $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX, - Help "This field specifies the Apical IP specific backlight scale field." - EndPage ; Apical Feature - EndPage ; "Panel #16 " - #ENDIF - - ;============================================================================== - ; Page - RGB Palette Table - ;------------------------------------------------------------------------------ - #if($Enable_Correction == 1) - Page "RGB Palette Table" - Link "Red Palette Table" , "Red Palette Table" - Link "Green Palette Table", "Green Palette Table" - Link "Blue Palette Table", "Blue Palette Table" - - Page "Red Palette Table" - Link "Close Table" , ".." - Table $Red_Table "Red Palette Table", - Column "Red", 1 byte, EHEX, - Help "Enter values for Red Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." - EndPage - - Page "Green Palette Table" - Link "Close Table" , ".." - Table $Green_Table "Green Palette Table", - Column "Green", 1 byte, EHEX, - Help "Enter values for Green Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." - EndPage - - Page "Blue Palette Table" - Link "Close Table" , ".." - Table $Blue_Table "Blue Palette Table", - Column "Blue", 1 byte, EHEX, - Help "Enter values for Blue Palette. Allowed range for entering values in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." - EndPage - EndPage - #endif - -EndPage ; "Integrated LFP Features" - - ;============================================================================== - ; Page - Integrated DisplayPort/HDMI Configuration - ;------------------------------------------------------------------------------ - - Page "Integrated DisplayPort/HDMI Configuration with External Connectors" - Title "Configurations for DisplayPort/HDMI Solution (External Connectors):" - Link "Close Window" , ".." - - Title "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC." - - Combo $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC" - - Title "DisplayPort Device Configuration " - Link "Device 1 Configuration" , "Device 1 (EFP1)" - Link "Device 2 Configuration" , "Device 2 (EFP2)" - Link "Device 3 Configuration" , "Device 3 (EFP3)" - - ;============================================================================== - ; Page - Device 1 (EFP1) - ;------------------------------------------------------------------------------ - Page "Device 1 (EFP1)" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $HPD2_Inversion_Enable, "HPD Inversion:", &Disabled_Enabled_List, - Help "This feature when enabled, will enable HPD inversion for Selected Port" - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - #IF ($Embedded_Platform == 1) ; Embedded platform - Title " " - - Combo $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - - Title " " - - Combo $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP1_Port_Dockable, "Dockable Port: ", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - #IF ($Embedded_Platform == 1) ; Embedded platform - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP1_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - EndPage ; "Device 1 (EFP1)" - - ;============================================================================== - ; Page - Device 2 (EFP2) - ;------------------------------------------------------------------------------ - Page "Device 2 (EFP2)" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $HPD3_Inversion_Enable, "HPD Inversion:", &Disabled_Enabled_List, - Help "This feature when enabled, will enable HPD inversion for Selected Port" - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - #IF ($Embedded_Platform == 1) ; Embedded platform - Title " " - - Combo $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - - Title " " - - Combo $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP2_Port_Dockable, "Dockable Port: ", &No_Yes_List, - Help "This feature will describe if this port is dockable or not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - - Combo $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link." - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - #IF ($Embedded_Platform == 1) ; Embedded platform - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP2_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - EndPage ; "Device 2" (EFP2) - - ;============================================================================== - ; Page - Device 3 (EFP3) - ;------------------------------------------------------------------------------ - Page "Device 3 (EFP3)" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List, - Help "This feature specifies the Device Type for this add-in device." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port the device is configured." - - Combo $EFP3_HPD_Inversion_Enable, "HPD Inversion:", &Disabled_Enabled_List, - Help "This feature when enabled, will enable HPD inversion for Selected Port" - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair used as DDC bus by this device. " - "If this device doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - #IF ($Embedded_Platform == 1) ; Embedded platform - Title " " - - Combo $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List, - Help "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority." - - Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - - Title " " - - Combo $EFP3_LSPcon_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions, - Help "This option is used to enable or disable the OnBoard LSPCON chip." - - Combo $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will set lane reversal bit for selected Port " - - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - - Combo $Int_EFP3_Port_Dockable, "Dockable Port: ", &No_Yes_List, - Help "This feature will describe if this Port is Dockable or Not." - - Title "Select DisplayPort Redriver " - Link "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - - Page "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" - Combo $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List, - Help "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not." - - Combo $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - - Title " " - Combo $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not." - - Combo $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List, - Help "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n" - "Level 0 (0 dB)\n" - "Level 1 (3.5 dB)\n" - "Level 2 (6.0 dB)\n" - "Level 3 (9.5 dB)" - - Combo $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_eDP_Link_VSwing_List, - Help "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n" - "Swing-0 (0.4 V)\n" - "Swing-1 (0.6 V)\n" - "Swing-2 (0.8 V)\n" - ; "Swing-3 (1.2 V)" - EndPage ; "DisplayPort Redriver Configuration" - - #IF ($Embedded_Platform == 1) ; Embedded platform - Page "EDID-less EFP Panel DTD Timings" - Link "Close Table" , ".." - - Table $EFP3_DTD " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD timings parameters. " - "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; "EDID-less EFP Panel DTD Timings" - #ENDIF ; Embedded platform - EndPage ; "Device 3 (EFP3)" - - EndPage ; "Integrated DisplayPort/HDMI Configuration with External Connectors" -EndPage ; Display configuration - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ -Page "Display Device Toggle Lists (Mobile only)" - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tRsvd\tEFP2.3\tEFP1.3\tRsvd\tRsvd\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - EndPage ; Display Toggle List 1 - - Page "Display Toggle List 2" - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tRsvd\tEFP2.3\tEFP1.3\tRsvd\tRsvd\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - EndPage ; Display Toggle List 2 - - Page "Display Toggle List 3" - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tRsvd\tEFP2.3\tEFP1.3\tRsvd\tRsvd\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - EndPage ; Display Toggle List 3 - - Page "Display Toggle List 4" - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and Graphics drivers " - "to help support the system BIOS with switch display device Hot Keys. " - "The basic algorithm is that the current display is found on the list and " - "the next settable display combination is set. " - "If no settable display combinations are found the function returns fail.\r\n\r\n" - "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tRsvd\tEFP2.3\tEFP1.3\tRsvd\tRsvd\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - EndPage ; Display Toggle List 4 -EndPage ; Display Device Toggle Lists - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - - Help "This feature allows removing support for selected modes resolutions.\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tRRate(Hz) Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n" - "\tBit \t 7 \t 6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n" - "\tComponent Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tVBIOS \r\n\r\n" - "Note: \t1) In order to remove mode from both Windows and DOS, " - "both bits 1 and Bit 0 must be set to 1.\r\n" - "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, " - "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n" - " Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n" - "\tBit \t15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "Note: Default is to remove a mode resolution from all panel types." -EndPage - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ -Page "Display Configuration Removal Table " - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Display Configuration" , 2 bytes , EHEX, - Help "This feature allows blocking selected display configurations by the video BIOS and driver.\r\n" - "Display Devices are specified in the following bit patterns:\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tRsvd\tEFP2.3\tEFP1.3\tRsvd\tRsvd\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "Examples:\r\n" - "\tDisplay Config\r\n" - "\t00000000 00001100b ; EFP & LFP combination to be removed\r\n" -EndPage - -;============================================================================== -; Page - OEM Customizable Modes -;------------------------------------------------------------------------------ -Page "OEM Customizable Modes" - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tVBIOS" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - Title "Mode Characteristics" - EditNum $OEM_Mode_X1, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #1 - - Page "OEM Mode #2" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tVBIOS" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X2, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate2, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x. " - "This is used by VBIOS only.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #2 - - Page "OEM Mode #3" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X3, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate3, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #3 - - Page "OEM Mode #4" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X4, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate4, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #4 - - Page "OEM Mode #5" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X5, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate5, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #5 - - Page "OEM Mode #6" - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tRsvd" - - TitleB "Mode Characteristics" - - EditNum $OEM_Mode_X6, "\tX Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, "\tY Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, "\tColor Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary).\r\n\r\n" - "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t Bit 0\r\n" - "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP" - - EditNum $OEM_Mode_RRate6, "\tRefresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings Descriptor) structure " - "as defined in the VESA EDID version 1.x.\r\n\r\n" - "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n" - "\tByte2 \t: High Byte of DClk in 10 KHz\r\n" - "\tByte3 \t: Horizontal Active in pixels, LSB\r\n" - "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n" - "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tByte6 \t: Vertical Active in lines, LSB\r\n" - "\tByte7 \t: Vertical Blanking in lines, LSB\r\n" - "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n" - "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tByte13 \t: Horizontal Image Size, LSB\r\n" - "\tByte14 \t: Vertical Image Size, LSB\r\n" - "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tByte16 \t: Horizontal Border in pixels\r\n" - "\tByte17 \t: Vertical Border in lines\r\n" - "\tByte18 \t: Flags:\r\n" - "\t \t: Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t: Bit 6-5: 00 = Reserved\r\n" - "\t \t: Bit 4-3: 11 = Digital Separate\r\n" - "\t \t: Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t: Bit 0: 0 = Reserved" - EndPage ; DTD - EndPage ; OEM Mode #6 -EndPage ; OEM Customizable Modes -;============================================================================ -; End of File -;---------------------------------------------------------------------------- diff --git a/BraswellFspBinPkg/Docs/Braswell_FSP_Integration_Guide.pdf b/BraswellFspBinPkg/Docs/Braswell_FSP_Integration_Guide.pdf deleted file mode 100644 index 2d28928e27fa723cd894c05f967da9153eb1c0a7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 389964 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