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Commits on Jul 4, 2024

• ClockGate: use VERILATOR_LEGACY for verilator version < 5 (OpenXiangShan#3133)

  Tang-Haojin

  authored
  8f9f96d

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• top: implement XSNoCTop and standalone devices (OpenXiangShan#3136)

  Tang-Haojin

  authored
  720dd62

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• CoupledL2: fix bug in RequestBuffer rdy update condition (OpenXiangShan#3146)

  linjuanZ

  authored
  0938652

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• RenameTable: fix width of rename table addr ports (OpenXiangShan#3128)

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  Squareless-XD

  authored
  ad5c9e6

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• csr: convert csrr vlenb instruction to a addi instruction (OpenXiangShan#3143)

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  Ziyue-Zhang

  authored
  63cb375

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• backend: remove vector wakeup for fix timing (OpenXiangShan#3145)

  xiaofeibao-xjtu

  authored
  9994e74

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• VsetModule: fix vlIsVlmax, checking tail should use max(VLMAX, VLEN/SEW) (OpenXiangShan#3135)

  sinsanction

  authored
  7994c93

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• StoreQueue: Change timeout to an existing API(TimeOutAssert) implementation.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
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• VLSU: fix the problem caused by the 'segmentUnit' not connecting with 'sbufferVecDifftestInfo'.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  6edb148

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• Parameters: Use uniform parameterized maximum values in VirtualLoadQueueSize and StoreQueueSize.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  be867eb

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• Dispatch2Iq: fix timing problem caused by bit width in 'Dispatch2iq'.

  

  Anzooooo

  authored and

  Tang-Haojin

  committed
  7a9ea6c

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• Vfalu: add fflagsEn default value and fix vfredmin/max (OpenXiangShan#3137)

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  lewislzh

  authored
  ae44e2b

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• Backend: fix ready timing from dispatch to frontend (OpenXiangShan#3127)

  xiaofeibao-xjtu

  authored
  f5c1705

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Commits on Jul 3, 2024

• rv64v: fix vwsll's imm read and illegal vsew check (OpenXiangShan#3131)

  Ziyue-Zhang

  authored
  4c8a449

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• Configs: use DefaultConfig as KunminghuV2Config

  linjuanZ

  committed
  182b7ec

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• CoupledL2: don't wait for PCredit if PCredit is already received

  linjuanZ

  committed
  5d15e43

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• workflows: add CI job for CHI version

  linjuanZ

  committed
  70a669a

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• SoC, Top: use Option for SoC widgets concerning L3

  linjuanZ

  committed
  1bf9a05

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• workflows: add linux-hello-opensbi test case for CHI version

  linjuanZ

  committed
  02999db

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• OpenLLC: add support for ReadNoSnp and WriteNoSnp

  linjuanZ

  committed
  81292e5

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• SoC: an initial version of DummyLLC

  linjuanZ

  committed
  78a8cd2

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Commits on Jul 2, 2024

• Makefile: prepend XSTOP_PREFIX to TOP (OpenXiangShan#3130)

  Tang-Haojin

  authored
  18179bb

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• RVH, CSR: remove htimedelta for openSBI (OpenXiangShan#3125)

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  cebarobot

  authored
  a13f171

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• IssueQueue: change othersTransPolicy when allComp or allSimp for fix timing (OpenXiangShan#3120)

  xiaofeibao-xjtu

  authored
  b9631a8

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• sim: use xs_assert_v2

  Tang-Haojin

  committed
  d4119b5

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• make: generate seperated sv instead of aggregated verilog

  Tang-Haojin

  committed
  05b9cfb

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• Top: use VerilogAXI4Record instead of sed to handle amba signal names

  Tang-Haojin

  committed
  2993c5e

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Commits on Jul 1, 2024

• vsetvl: fix flush and block signal modified by vstart check (OpenXiangShan#3124)

  Ziyue-Zhang

  authored
  136b9ac

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• IPrefetch: MSHR should update IPrefetch s1 waymask (OpenXiangShan#3122)

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  ngc7331

  authored
  b4f1e5b

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• Vfalu: fix ffagsEn logic for vfredunction (OpenXiangShan#3116)

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  lewislzh

  authored
  ecc992c

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• L2TLB, RVH: change ppnlen from 24 to 29 for the first stage translation in two stage translation (OpenXiangShan#3121)

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  pxk27

  authored
  4c0e018

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• StoreQueue: fix exception entry mistakenly written to sbuffer (OpenXiangShan#3119)

  good-circle

  authored
  065828e

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Commits on Jun 28, 2024

• build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (OpenXiangShan#3118)

  Tang-Haojin

  authored
  195ef4a

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• refactor: change exception encoding from one-hot to label (OpenXiangShan#3104)

  Yan-Muzi

  authored
  6b46af8

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• ICache: implement new ICache (OpenXiangShan#3051)

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  ssszwic

  and

  ngc7331

  authored
  b92f844

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