kernmulc_20.ptx

//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19856038
// Cuda compilation tools, release 7.5, V7.5.17
// Based on LLVM 3.4svn
//

.version 4.3
.target sm_20
.address_size 64

	// .globl	kernmulC

.visible .entry kernmulC(
	.param .u64 kernmulC_param_0,
	.param .u64 kernmulC_param_1,
	.param .u32 kernmulC_param_2,
	.param .u32 kernmulC_param_3
)
{
	.reg .pred 	%p<4>;
	.reg .f32 	%f<10>;
	.reg .b32 	%r<13>;
	.reg .b64 	%rd<8>;


	ld.param.u64 	%rd1, [kernmulC_param_0];
	ld.param.u64 	%rd2, [kernmulC_param_1];
	ld.param.u32 	%r3, [kernmulC_param_2];
	ld.param.u32 	%r4, [kernmulC_param_3];
	mov.u32 	%r5, %ntid.x;
	mov.u32 	%r6, %ctaid.x;
	mov.u32 	%r7, %tid.x;
	mad.lo.s32 	%r1, %r5, %r6, %r7;
	mov.u32 	%r8, %ntid.y;
	mov.u32 	%r9, %ctaid.y;
	mov.u32 	%r10, %tid.y;
	mad.lo.s32 	%r2, %r8, %r9, %r10;
	setp.ge.s32	%p1, %r2, %r4;
	setp.ge.s32	%p2, %r1, %r3;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	BB0_2;

	cvta.to.global.u64 	%rd3, %rd2;
	cvta.to.global.u64 	%rd4, %rd1;
	mad.lo.s32 	%r11, %r2, %r3, %r1;
	shl.b32 	%r12, %r11, 1;
	mul.wide.s32 	%rd5, %r12, 4;
	add.s64 	%rd6, %rd4, %rd5;
	add.s64 	%rd7, %rd3, %rd5;
	ld.global.f32 	%f1, [%rd7];
	ld.global.f32 	%f2, [%rd6];
	mul.f32 	%f3, %f2, %f1;
	ld.global.f32 	%f4, [%rd7+4];
	ld.global.f32 	%f5, [%rd6+4];
	mul.f32 	%f6, %f5, %f4;
	sub.f32 	%f7, %f3, %f6;
	st.global.f32 	[%rd6], %f7;
	mul.f32 	%f8, %f2, %f4;
	fma.rn.f32 	%f9, %f5, %f1, %f8;
	st.global.f32 	[%rd6+4], %f9;

BB0_2:
	ret;
}