From ea9d58905e6fd27cb33cdc95398c7216ac00e0db Mon Sep 17 00:00:00 2001 From: khkim6040 Date: Sun, 12 May 2024 20:30:51 +0900 Subject: [PATCH] Format indentation --- lab4-2/ALU.v | 2 +- lab4-2/ALUControlUnit.v | 2 +- lab4-2/Adder.v | 8 ++- lab4-2/ControlUnit.v | 21 +++---- lab4-2/DataMemory.v | 17 +++--- lab4-2/ForwardingUnit.v | 3 +- lab4-2/GShare.v | 15 ++--- lab4-2/HaltDetector.v | 5 +- lab4-2/HazardDetector.v | 38 ++++++------ lab4-2/ImmediateGenerator.v | 2 +- lab4-2/InstMemory.v | 11 ++-- lab4-2/Mux_2_to_1.v | 3 +- lab4-2/Mux_4_to_1.v | 14 +++-- lab4-2/PC.v | 2 +- lab4-2/RegisterFile.v | 23 ++++---- lab4-2/cpu.v | 114 ++++++++++++++++++------------------ 16 files changed, 150 insertions(+), 130 deletions(-) diff --git a/lab4-2/ALU.v b/lab4-2/ALU.v index 584fd51..262e732 100644 --- a/lab4-2/ALU.v +++ b/lab4-2/ALU.v @@ -7,7 +7,7 @@ module ALU ( input [1:0] jump_signal, output reg [31:0] alu_result, output reg [1:0] alu_bcond -); + ); always @(*) begin alu_result = 32'b0; diff --git a/lab4-2/ALUControlUnit.v b/lab4-2/ALUControlUnit.v index e0d8eff..5dca66a 100644 --- a/lab4-2/ALUControlUnit.v +++ b/lab4-2/ALUControlUnit.v @@ -5,7 +5,7 @@ module ALUControlUnit ( input [2:0] funct3, input [1:0] alu_op, output reg [3:0] alu_ctrl_out -); + ); always @(*) begin case(alu_op) diff --git a/lab4-2/Adder.v b/lab4-2/Adder.v index 27f7d8b..50a1485 100644 --- a/lab4-2/Adder.v +++ b/lab4-2/Adder.v @@ -1,6 +1,8 @@ -module Adder(input [31:0] x0, - input [31:0] x1, - output reg [31:0] sum); +module Adder( + input [31:0] x0, + input [31:0] x1, + output reg [31:0] sum + ); always@(*) begin sum = x0 + x1; diff --git a/lab4-2/ControlUnit.v b/lab4-2/ControlUnit.v index b6f41f5..adff5fb 100644 --- a/lab4-2/ControlUnit.v +++ b/lab4-2/ControlUnit.v @@ -1,15 +1,16 @@ `include "opcodes.v" -module ControlUnit (input [6:0] part_of_inst, - output reg mem_read, - output reg [1:0] mem_to_reg, - output reg mem_write, - output reg alu_src, - output reg reg_write, - output reg [1:0] alu_op, - output reg is_ecall, - output reg [1:0] jump_signal - ); +module ControlUnit ( + input [6:0] part_of_inst, + output reg mem_read, + output reg [1:0] mem_to_reg, + output reg mem_write, + output reg alu_src, + output reg reg_write, + output reg [1:0] alu_op, + output reg is_ecall, + output reg [1:0] jump_signal + ); always @(*) begin diff --git a/lab4-2/DataMemory.v b/lab4-2/DataMemory.v index d3def1c..a1af2e8 100644 --- a/lab4-2/DataMemory.v +++ b/lab4-2/DataMemory.v @@ -1,10 +1,13 @@ -module DataMemory #(parameter MEM_DEPTH = 16384) (input reset, - input clk, - input [31:0] addr, // address of the data memory - input [31:0] din, // data to be written - input mem_read, // is read signal driven? - input mem_write, // is write signal driven? - output [31:0] dout); // output of the data memory at addr +module DataMemory #(parameter MEM_DEPTH = 16384) ( + input reset, + input clk, + input [31:0] addr, // address of the data memory + input [31:0] din, // data to be written + input mem_read, // is read signal driven? + input mem_write, // is write signal driven? + output [31:0] dout // output of the data memory at addr + ); + integer i; // Data memory reg [31:0] mem[0: MEM_DEPTH - 1]; diff --git a/lab4-2/ForwardingUnit.v b/lab4-2/ForwardingUnit.v index 924cda3..b948a5d 100644 --- a/lab4-2/ForwardingUnit.v +++ b/lab4-2/ForwardingUnit.v @@ -8,7 +8,8 @@ module ForwardingUnit( input alu_src, output reg [1:0] forwardA, output reg [1:0] forwardB, - output reg [1:0] forwardC); + output reg [1:0] forwardC + ); always @(*) begin if ((EX_rs1_index != 0) && (EX_rs1_index == MEM_reg_rd) && MEM_reg_write) diff --git a/lab4-2/GShare.v b/lab4-2/GShare.v index 85fbe10..6731563 100644 --- a/lab4-2/GShare.v +++ b/lab4-2/GShare.v @@ -1,13 +1,14 @@ `include "opcodes.v" module GShare( - input clk, - input reset, - input [31:0] pc, - input [1:0] bcond, - input [31:0] EX_correct_next_pc, - input [31:0] EX_pc, - output reg [31:0] next_pc); + input clk, + input reset, + input [31:0] pc, + input [1:0] bcond, + input [31:0] EX_correct_next_pc, + input [31:0] EX_pc, + output reg [31:0] next_pc + ); reg [56:0] BTB [31:0]; reg [4:0] BHSR; diff --git a/lab4-2/HaltDetector.v b/lab4-2/HaltDetector.v index 87a77de..8b14c32 100644 --- a/lab4-2/HaltDetector.v +++ b/lab4-2/HaltDetector.v @@ -1,7 +1,8 @@ module HaltDetector( input is_ecall, - input[31:0] rs1_data, - output reg is_halted); + input [31:0] rs1_data, + output reg is_halted + ); always @(*) begin is_halted = is_ecall && (rs1_data == 10); diff --git a/lab4-2/HazardDetector.v b/lab4-2/HazardDetector.v index 64a4dc0..34ad7fb 100644 --- a/lab4-2/HazardDetector.v +++ b/lab4-2/HazardDetector.v @@ -1,23 +1,25 @@ `include "opcodes.v" -module HazardDetector (input clk, - input reset, - input [31:0] instruction, - input [4:0] rs1, - input [4:0] EX_rd, - input [4:0] MEM_rd, - input mem_read, - input is_ecall, - input [1:0] bcond, - input [31:0] ID_PC, - input [31:0] EX_PC, - input [31:0] target_pc, - output reg PC_write, - output reg IF_ID_write, - output reg ID_EX_nop_signal, - output reg IF_ID_nop_signal, - output reg [31:0] EX_correct_next_pc, - output reg EX_PCSrc); +module HazardDetector ( + input clk, + input reset, + input [31:0] instruction, + input [4:0] rs1, + input [4:0] EX_rd, + input [4:0] MEM_rd, + input mem_read, + input is_ecall, + input [1:0] bcond, + input [31:0] ID_PC, + input [31:0] EX_PC, + input [31:0] target_pc, + output reg PC_write, + output reg IF_ID_write, + output reg ID_EX_nop_signal, + output reg IF_ID_nop_signal, + output reg [31:0] EX_correct_next_pc, + output reg EX_PCSrc + ); reg [4:0] rs2; reg [6:0] opcode; diff --git a/lab4-2/ImmediateGenerator.v b/lab4-2/ImmediateGenerator.v index c1cae23..8e6d231 100644 --- a/lab4-2/ImmediateGenerator.v +++ b/lab4-2/ImmediateGenerator.v @@ -3,7 +3,7 @@ module ImmediateGenerator ( input [31:0] part_of_inst, output reg [31:0] imm_gen_out -); + ); wire [6:0] opcode; wire [2:0] funct3; diff --git a/lab4-2/InstMemory.v b/lab4-2/InstMemory.v index 7b9eca3..46a33c4 100644 --- a/lab4-2/InstMemory.v +++ b/lab4-2/InstMemory.v @@ -1,7 +1,10 @@ -module InstMemory #(parameter MEM_DEPTH = 1024) (input reset, - input clk, - input [31:0] addr, // address of the instruction memory - output [31:0] dout); // instruction at addr +module InstMemory #(parameter MEM_DEPTH = 1024) ( + input reset, + input clk, + input [31:0] addr, // address of the instruction memory + output [31:0] dout // instruction at addr + ); + integer i; // Instruction memory reg [31:0] mem[0:MEM_DEPTH - 1]; diff --git a/lab4-2/Mux_2_to_1.v b/lab4-2/Mux_2_to_1.v index 157f07a..56a8f59 100644 --- a/lab4-2/Mux_2_to_1.v +++ b/lab4-2/Mux_2_to_1.v @@ -2,7 +2,8 @@ module Mux_2_to_1 #(parameter WIDTH = 32) ( input [WIDTH-1:0] x0, input [WIDTH-1:0] x1, input swch, - output reg [WIDTH-1:0] out); + output reg [WIDTH-1:0] out + ); always @(*) begin if (swch == 1'b0) begin diff --git a/lab4-2/Mux_4_to_1.v b/lab4-2/Mux_4_to_1.v index 3ffbb18..18affb1 100644 --- a/lab4-2/Mux_4_to_1.v +++ b/lab4-2/Mux_4_to_1.v @@ -1,9 +1,11 @@ -module Mux_4_to_1 (input [31:0] x0, - input [31:0] x1, - input [31:0] x2, - input [31:0] x3, - input [1:0] swch, - output reg [31:0] out); +module Mux_4_to_1 ( + input [31:0] x0, + input [31:0] x1, + input [31:0] x2, + input [31:0] x3, + input [1:0] swch, + output reg [31:0] out + ); always @(*) begin case (swch) diff --git a/lab4-2/PC.v b/lab4-2/PC.v index 4b7e825..ef89cf0 100644 --- a/lab4-2/PC.v +++ b/lab4-2/PC.v @@ -4,7 +4,7 @@ module PC( input [31:0] next_pc, input pc_write_signal, output reg [31:0] current_pc -); + ); always @(posedge clk) begin if (reset) begin diff --git a/lab4-2/RegisterFile.v b/lab4-2/RegisterFile.v index 09de133..14591bb 100644 --- a/lab4-2/RegisterFile.v +++ b/lab4-2/RegisterFile.v @@ -1,13 +1,16 @@ -module RegisterFile(input reset, - input clk, - input [4:0] rs1, // source register 1 - input [4:0] rs2, // source register 2 - input [4:0] rd, // destination register - input [31:0] rd_din, // input data for rd - input write_enable, // RegWrite signal - output [31:0] rs1_dout, // output of rs 1 - output [31:0] rs2_dout, - output [31:0] print_reg[0:31]); // output of rs 2 +module RegisterFile( + input reset, + input clk, + input [4:0] rs1, // source register 1 + input [4:0] rs2, // source register 2 + input [4:0] rd, // destination register + input [31:0] rd_din, // input data for rd + input write_enable, // RegWrite signal + output [31:0] rs1_dout, // output of rs 1 + output [31:0] rs2_dout, + output [31:0] print_reg[0:31] // output of rs 2 + ); + integer i; // Register file reg [31:0] rf[0:31]; diff --git a/lab4-2/cpu.v b/lab4-2/cpu.v index 171c490..b0cd584 100644 --- a/lab4-2/cpu.v +++ b/lab4-2/cpu.v @@ -24,34 +24,34 @@ module cpu(input reset, // positive reset signal wire ID_EX_nop_signal; // output of HazardDetector module. Flush ID/EX pipeline register // IF stage wires - wire[31:0] IF_PC; // output of PC module - wire[31:0] IF_imem_out; // output of InstMemory module - wire[31:0] IF_pc_4_adder_out; // output of Adder module - wire[31:0] IF_next_pc_mux_out; // output of Mux_2_to_1 module - wire[31:0] IF_GShare_out; // output of GShare module + wire [31:0] IF_PC; // output of PC module + wire [31:0] IF_imem_out; // output of InstMemory module + wire [31:0] IF_pc_4_adder_out; // output of Adder module + wire [31:0] IF_next_pc_mux_out; // output of Mux_2_to_1 module + wire [31:0] IF_GShare_out; // output of GShare module // ID stage wires - wire[31:0] ID_rs1_dout; // output of RegisterFile module - wire[31:0] ID_rs2_dout; // output of RegisterFile module - wire[31:0] ID_imm_gen_out; // output of ImmediateGenerator module + wire [31:0] ID_rs1_dout; // output of RegisterFile module + wire [31:0] ID_rs2_dout; // output of RegisterFile module + wire [31:0] ID_imm_gen_out; // output of ImmediateGenerator module wire ID_is_ecall; // output of ControlUnit module wire ID_is_halted; // output of HaltDetector module wire ID_reg_write; // output of ControlUnit module - wire[1:0] ID_mem_to_reg; // output of ControlUnit module + wire [1:0] ID_mem_to_reg; // output of ControlUnit module wire ID_mem_read; // output of ControlUnit module wire ID_mem_write; // output of ControlUnit module - wire[1:0] ID_alu_op; // output of ControlUnit module + wire [1:0] ID_alu_op; // output of ControlUnit module wire ID_alu_src; // output of ControlUnit module - wire[31:0] ID_full_inst; // input ID stage modules - wire[6:0] ID_opcode; // input ID stage modules - wire[2:0] ID_funct3; // input ID stage modules + wire [31:0] ID_full_inst; // input ID stage modules + wire [6:0] ID_opcode; // input ID stage modules + wire [2:0] ID_funct3; // input ID stage modules wire ID_funct7; // input ID stage modules - wire[4:0] ID_reg_rs1; // input ID stage modules - wire[4:0] ID_reg_rs2; // input ID stage modules - wire[4:0] ID_reg_rd; // input ID stage modules - wire[4:0] ID_reg_rs1_mux_out; // Output of Mux_2_to_1 module - wire[31:0] ID_PC; // input of HazardDetector module - wire[1:0] ID_jump_signal; // output of ControlUnit module + wire [4:0] ID_reg_rs1; // input ID stage modules + wire [4:0] ID_reg_rs2; // input ID stage modules + wire [4:0] ID_reg_rd; // input ID stage modules + wire [4:0] ID_reg_rs1_mux_out; // Output of Mux_2_to_1 module + wire [31:0] ID_PC; // input of HazardDetector module + wire [1:0] ID_jump_signal; // output of ControlUnit module // Input Wires Initialization assign ID_full_inst = reg_IF_ID_inst; assign ID_opcode = reg_IF_ID_inst[6:0]; @@ -63,24 +63,24 @@ module cpu(input reset, // positive reset signal assign ID_PC = reg_IF_ID_PC; // EX stage wires - wire[3:0] EX_alu_ctrl_out; // output of ALUControlUnit module - wire[31:0] EX_alu_src2_mux_out; // output of Mux_2_to_1 module - wire[31:0] EX_alu_result; // output of ALU module + wire [3:0] EX_alu_ctrl_out; // output of ALUControlUnit module + wire [31:0] EX_alu_src2_mux_out; // output of Mux_2_to_1 module + wire [31:0] EX_alu_result; // output of ALU module wire [1:0] forwardA; // input of forwarding_src1_mux wire [1:0] forwardB; // input of forwarding_src2_mux wire [1:0] forwardC; // input of dmem_din_mux wire [31:0] forwardA_mux_out; // input of ALU A src wire [31:0] forwardB_mux_out; // input of ALU B src wire [31:0] dmem_din_mux_out; // input of DataMemory module - wire[31:0] EX_imm; // input of Mux_2_to_1 module - wire[31:0] EX_rs1_data; // input of ALU module - wire[31:0] EX_rs2_data; // input of Mux_2_to_1 module + wire [31:0] EX_imm; // input of Mux_2_to_1 module + wire [31:0] EX_rs1_data; // input of ALU module + wire [31:0] EX_rs2_data; // input of Mux_2_to_1 module wire EX_alu_src; // input of ALU module - wire[1:0] EX_alu_op; // input of ALUControlUnit module + wire [1:0] EX_alu_op; // input of ALUControlUnit module wire EX_funct7; // input of ALUControlUnit module wire [2:0] EX_funct3; // input of ALUControlUnit module wire EX_mem_read; // input of EX_MEM pipeline register - wire[1:0] EX_mem_to_reg; // input of EX_MEM pipeline register + wire [1:0] EX_mem_to_reg; // input of EX_MEM pipeline register wire EX_mem_write; // input of EX_MEM pipeline register wire [4:0] EX_reg_rd; // input of EX_MEM pipeline register wire EX_is_halted; // input of EX_MEM pipeline register @@ -92,8 +92,8 @@ module cpu(input reset, // positive reset signal wire [31:0] EX_correct_next_pc; // output of hazard detector wire EX_PCSrc; // output of hazard detector wire [31:0] EX_target_pc_adder_out; // output of target address Adder module - wire[1:0] EX_jump_signal; // output of ControlUnit module - wire[31:0] EX_target_pc_x0_mux_out; // output of Mux_2_to_1 module + wire [1:0] EX_jump_signal; // output of ControlUnit module + wire [31:0] EX_target_pc_x0_mux_out; // output of Mux_2_to_1 module // Input Wires Initialization assign EX_imm = reg_ID_EX_imm; assign EX_rs1_data = reg_ID_EX_rs1_data; @@ -115,16 +115,16 @@ module cpu(input reset, // positive reset signal // MEM stage wires - wire[31:0] MEM_dmem_dout; // output of DataMemory module - wire[31:0] MEM_alu_out; // input of DataMemory module - wire[31:0] MEM_dmem_din; // input of DataMemory module + wire [31:0] MEM_dmem_dout; // output of DataMemory module + wire [31:0] MEM_alu_out; // input of DataMemory module + wire [31:0] MEM_dmem_din; // input of DataMemory module wire MEM_mem_write; // input of DataMemory module wire MEM_mem_read; // input of DataMemory module - wire[1:0] MEM_mem_to_reg; // input of MEM_WB pipeline register + wire [1:0] MEM_mem_to_reg; // input of MEM_WB pipeline register wire MEM_reg_write; // input of MEM_WB pipeline register wire MEM_is_halted; // input of MEM_WB pipeline register - wire[4:0] MEM_reg_rd; // input of MEM_WB pipeline register - wire[31:0] MEM_PC; + wire [4:0] MEM_reg_rd; // input of MEM_WB pipeline register + wire [31:0] MEM_PC; // Input Wires Initialization assign MEM_alu_out = reg_EX_MEM_alu_out; assign MEM_dmem_din = reg_EX_MEM_dmem_din; @@ -137,13 +137,13 @@ module cpu(input reset, // positive reset signal assign MEM_PC = reg_EX_MEM_PC; // WB stage wires - wire[31:0] WB_reg_write_mux_out; // output of Mux_2_to_1 module - wire[31:0] WB_mem_to_reg_src_1; // input of Mux_2_to_1 module - wire[31:0] WB_mem_to_reg_src_2; // input of Mux_2_to_1 module - wire[1:0] WB_mem_to_reg; // input of Mux_2_to_1 module + wire [31:0] WB_reg_write_mux_out; // output of Mux_2_to_1 module + wire [31:0] WB_mem_to_reg_src_1; // input of Mux_2_to_1 module + wire [31:0] WB_mem_to_reg_src_2; // input of Mux_2_to_1 module + wire [1:0] WB_mem_to_reg; // input of Mux_2_to_1 module wire WB_reg_write; // input of MEM_WB pipeline register wire [4:0] WB_reg_rd; - wire[31:0] WB_PC; + wire [31:0] WB_PC; // Input Wires Initialization assign WB_mem_to_reg_src_1 = reg_MEM_WB_mem_to_reg_src_1; assign WB_mem_to_reg_src_2 = reg_MEM_WB_mem_to_reg_src_2; @@ -162,19 +162,19 @@ module cpu(input reset, // positive reset signal reg [31:0] reg_IF_ID_PC; /***** ID/EX pipeline registers *****/ // From the control unit - reg[1:0] reg_ID_EX_alu_op; // will be used in EX stage + reg [1:0] reg_ID_EX_alu_op; // will be used in EX stage reg reg_ID_EX_alu_src; // will be used in EX stage reg reg_ID_EX_mem_write; // will be used in MEM stage reg reg_ID_EX_mem_read; // will be used in MEM stage - reg[1:0] reg_ID_EX_mem_to_reg; // will be used in WB stage + reg [1:0] reg_ID_EX_mem_to_reg; // will be used in WB stage reg reg_ID_EX_reg_write; // will be used in WB stage reg reg_ID_EX_is_halted; // will be used in WB stage - reg[1:0] reg_ID_EX_jump_signal; // will be used in EX stage + reg [1:0] reg_ID_EX_jump_signal; // will be used in EX stage // From others - reg[31:0] reg_ID_EX_rs1_data; - reg[31:0] reg_ID_EX_rs2_data; - reg[31:0] reg_ID_EX_imm; - reg[4:0] reg_ID_EX_rd; + reg [31:0] reg_ID_EX_rs1_data; + reg [31:0] reg_ID_EX_rs2_data; + reg [31:0] reg_ID_EX_imm; + reg [4:0] reg_ID_EX_rd; reg reg_ID_EX_funct7; reg [2:0] reg_ID_EX_funct3; reg [4:0] reg_ID_EX_rs1_index; @@ -185,25 +185,25 @@ module cpu(input reset, // positive reset signal // From the control unit reg reg_EX_MEM_mem_write; // will be used in MEM stage reg reg_EX_MEM_mem_read; // will be used in MEM stage - reg[1:0] reg_EX_MEM_mem_to_reg; // will be used in WB stage + reg [1:0] reg_EX_MEM_mem_to_reg; // will be used in WB stage reg reg_EX_MEM_reg_write; // will be used in WB stage reg reg_EX_MEM_is_halted; // will be used in WB stage // From others - reg[31:0] reg_EX_MEM_alu_out; - reg[31:0] reg_EX_MEM_dmem_din; - reg[4:0] reg_EX_MEM_rd; - reg[31:0] reg_EX_MEM_PC; + reg [31:0] reg_EX_MEM_alu_out; + reg [31:0] reg_EX_MEM_dmem_din; + reg [4:0] reg_EX_MEM_rd; + reg [31:0] reg_EX_MEM_PC; /***** MEM/WB pipeline registers *****/ // From the control unit - reg[1:0] reg_MEM_WB_mem_to_reg; // will be used in WB stage + reg [1:0] reg_MEM_WB_mem_to_reg; // will be used in WB stage reg reg_MEM_WB_reg_write; // will be used in WB stage reg reg_MEM_WB_is_halted; // will be used in WB stage // From others - reg[31:0] reg_MEM_WB_mem_to_reg_src_1; - reg[31:0] reg_MEM_WB_mem_to_reg_src_2; - reg[4:0] reg_MEM_WB_rd; - reg[31:0] reg_MEM_WB_PC; + reg [31:0] reg_MEM_WB_mem_to_reg_src_1; + reg [31:0] reg_MEM_WB_mem_to_reg_src_2; + reg [4:0] reg_MEM_WB_rd; + reg [31:0] reg_MEM_WB_PC;