A Linux-capable RISC-V multicore for and by the world

Project F brings FPGAs to life with exciting open-source designs you can build on.

100 Days of RTL

Test suite designed to check compliance with the SystemVerilog standard.

Public repository for Litefury & Nitefury

Reference examples and short projects using UVM Methodology

Code used in

UVM agents

Generate UVM testbench framework template files with Python 3

Generate verilog register file from systemRDL description

training labs and examples