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hsx_uc.py
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# HSX hsxuc_events.v1.00p hsxuc_derived.v1.00p
# aliases
aliases = {
"QPIRxMatch1": "Q_Py_PCI_RX_PMON_BOX_MATCH1",
"QPIRxMask1": "Q_Py_PCI_RX_PMON_BOX_MASK1",
"IRPFilter": "IRP_PCI_PMON_BOX_FILTER",
"PCUFilter": "PCU_MSR_PMON_BOX_FILTER",
"QPIRxMask0": "Q_Py_PCI_RX_PMON_BOX_MASK0",
"CBoFilter0": "Cn_MSR_PMON_BOX_FILTER",
"HA_AddrMatch0": "HAn_PCI_PMON_BOX_ADDRMATCH0",
"QPITxMatch0": "Q_Py_PCI_TX_PMON_BOX_MATCH0",
"HA_AddrMatch1": "HAn_PCI_PMON_BOX_ADDRMATCH1",
"QPITxMask0": "Q_Py_PCI_TX_PMON_BOX_MASK0",
"QPITxMask1": "Q_Py_PCI_TX_PMON_BOX_MASK1",
"QPITxMatch1": "Q_Py_PCI_TX_PMON_BOX_MATCH1",
"HA_OpcodeMatch": "HAn_PCI_PMON_BOX_OPCODEMATCH",
"QPIRxMatch0": "Q_Py_PCI_RX_PMON_BOX_MATCH0",
"CBoFilter1": "Cn_MSR_PMON_BOX_FILTER1",
"UBoxFilter": "U_MSR_PMON_BOX_FILTER",
}
events = {
# iMC:
"iMC.ACT_COUNT": {
"Box": "iMC",
"Category": "iMC ACT Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"Desc": "DRAM Activate Count",
"EvSel": 1,
"ExtSel": "",
},
"iMC.ACT_COUNT.BYP": {
"Box": "iMC",
"Category": "iMC ACT Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"Desc": "DRAM Activate Count",
"EvSel": 1,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.ACT_COUNT.RD": {
"Box": "iMC",
"Category": "iMC ACT Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"Desc": "DRAM Activate Count",
"EvSel": 1,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.ACT_COUNT.WR": {
"Box": "iMC",
"Category": "iMC ACT Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"Desc": "DRAM Activate Count",
"EvSel": 1,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.BYP_CMDS": {
"Box": "iMC",
"Category": "iMC BYPASS Command Events",
"Counters": "0-3",
"EvSel": 161,
"ExtSel": "",
},
"iMC.BYP_CMDS.PRE": {
"Box": "iMC",
"Category": "iMC BYPASS Command Events",
"Counters": "0-3",
"EvSel": 161,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.BYP_CMDS.CAS": {
"Box": "iMC",
"Category": "iMC BYPASS Command Events",
"Counters": "0-3",
"EvSel": 161,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.BYP_CMDS.ACT": {
"Box": "iMC",
"Category": "iMC BYPASS Command Events",
"Counters": "0-3",
"EvSel": 161,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.CAS_COUNT": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
},
"iMC.CAS_COUNT.RD_UNDERFILL": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.CAS_COUNT.RD_RMM": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxx1xxxxx",
},
"iMC.CAS_COUNT.RD_REG": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.CAS_COUNT.WR": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "b00001100",
},
"iMC.CAS_COUNT.RD": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "b00000011",
},
"iMC.CAS_COUNT.WR_RMM": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.CAS_COUNT.WR_WMM": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.CAS_COUNT.ALL": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "b00001111",
},
"iMC.CAS_COUNT.RD_WMM": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "DRAM RD_CAS and WR_CAS Commands",
"Desc": "DRAM RD_CAS and WR_CAS Commands.",
"EvSel": 4,
"ExtSel": "",
"Umask": "bxxx1xxxx",
},
"iMC.DCLOCKTICKS": {
"Box": "iMC",
"Category": "iMC DCLK Events",
"Counters": "0-3",
"Desc": "DRAM Clockticks",
"EvSel": 0,
"ExtSel": "",
},
"iMC.DRAM_PRE_ALL": {
"Box": "iMC",
"Category": "iMC DRAM_PRE_ALL Events",
"Counters": "0-3",
"Defn": "Counts the number of times that the precharge all command was sent.",
"Desc": "DRAM Precharge All Commands",
"EvSel": 6,
"ExtSel": "",
},
"iMC.DRAM_REFRESH": {
"Box": "iMC",
"Category": "iMC DRAM_REFRESH Events",
"Counters": "0-3",
"Defn": "Counts the number of refreshes issued.",
"Desc": "Number of DRAM Refreshes Issued",
"EvSel": 5,
"ExtSel": "",
},
"iMC.DRAM_REFRESH.HIGH": {
"Box": "iMC",
"Category": "iMC DRAM_REFRESH Events",
"Counters": "0-3",
"Defn": "Counts the number of refreshes issued.",
"Desc": "Number of DRAM Refreshes Issued",
"EvSel": 5,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.DRAM_REFRESH.PANIC": {
"Box": "iMC",
"Category": "iMC DRAM_REFRESH Events",
"Counters": "0-3",
"Defn": "Counts the number of refreshes issued.",
"Desc": "Number of DRAM Refreshes Issued",
"EvSel": 5,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.ECC_CORRECTABLE_ERRORS": {
"Box": "iMC",
"Category": "iMC ECC Events",
"Counters": "0-3",
"Defn": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
"Desc": "ECC Correctable Errors",
"EvSel": 9,
"ExtSel": "",
},
"iMC.MAJOR_MODES": {
"Box": "iMC",
"Category": "iMC MAJOR_MODES Events",
"Counters": "0-3",
"Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
"Desc": "Cycles in a Major Mode",
"EvSel": 7,
"ExtSel": "",
},
"iMC.MAJOR_MODES.ISOCH": {
"Box": "iMC",
"Category": "iMC MAJOR_MODES Events",
"Counters": "0-3",
"Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
"Desc": "Cycles in a Major Mode",
"EvSel": 7,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.MAJOR_MODES.PARTIAL": {
"Box": "iMC",
"Category": "iMC MAJOR_MODES Events",
"Counters": "0-3",
"Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
"Desc": "Cycles in a Major Mode",
"EvSel": 7,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.MAJOR_MODES.WRITE": {
"Box": "iMC",
"Category": "iMC MAJOR_MODES Events",
"Counters": "0-3",
"Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
"Desc": "Cycles in a Major Mode",
"EvSel": 7,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.MAJOR_MODES.READ": {
"Box": "iMC",
"Category": "iMC MAJOR_MODES Events",
"Counters": "0-3",
"Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
"Desc": "Cycles in a Major Mode",
"EvSel": 7,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.POWER_CHANNEL_DLLOFF": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
"Desc": "Channel DLLOFF Cycles",
"EvSel": 132,
"ExtSel": "",
"Notes": "IBT = Input Buffer Termination = Off",
},
"iMC.POWER_CHANNEL_PPD": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Desc": "Channel PPD Cycles",
"EvSel": 133,
"ExtSel": "",
"MaxIncCyc": 4,
"Notes": "IBT = Input Buffer Termination = On. ALL Ranks must be populated in order to measure",
},
"iMC.POWER_CKE_CYCLES": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
},
"iMC.POWER_CKE_CYCLES.RANK0": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00000001",
},
"iMC.POWER_CKE_CYCLES.RANK6": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b01000000",
},
"iMC.POWER_CKE_CYCLES.RANK5": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00100000",
},
"iMC.POWER_CKE_CYCLES.RANK2": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00000100",
},
"iMC.POWER_CKE_CYCLES.RANK3": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00001000",
},
"iMC.POWER_CKE_CYCLES.RANK4": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00010000",
},
"iMC.POWER_CKE_CYCLES.RANK1": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b00000010",
},
"iMC.POWER_CKE_CYCLES.RANK7": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"Desc": "CKE_ON_CYCLES by Rank",
"EvSel": 131,
"ExtSel": "",
"MaxIncCyc": 16,
"Umask": "b10000000",
},
"iMC.POWER_CRITICAL_THROTTLE_CYCLES": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Desc": "Critical Throttle Cycles",
"EvSel": 134,
"ExtSel": "",
},
"iMC.POWER_PCU_THROTTLING": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"EvSel": 66,
"ExtSel": "",
},
"iMC.POWER_SELF_REFRESH": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Desc": "Clock-Enabled Self-Refresh",
"EvSel": 67,
"ExtSel": "",
},
"iMC.POWER_THROTTLE_CYCLES": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
},
"iMC.POWER_THROTTLE_CYCLES.RANK7": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "b1xxxxxxx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK1": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.POWER_THROTTLE_CYCLES.RANK4": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxxx1xxxx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK3": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK6": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bx1xxxxxx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK2": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK5": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxx1xxxxx",
},
"iMC.POWER_THROTTLE_CYCLES.RANK0": {
"Box": "iMC",
"Category": "iMC POWER Events",
"Counters": "0-3",
"Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"Desc": "Throttle Cycles for Rank 0",
"EvSel": 65,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.PREEMPTION": {
"Box": "iMC",
"Category": "iMC PREEMPTION Events",
"Counters": "0-3",
"Defn": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
"Desc": "Read Preemption Count",
"EvSel": 8,
"ExtSel": "",
},
"iMC.PREEMPTION.RD_PREEMPT_WR": {
"Box": "iMC",
"Category": "iMC PREEMPTION Events",
"Counters": "0-3",
"Defn": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
"Desc": "Read Preemption Count",
"EvSel": 8,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.PREEMPTION.RD_PREEMPT_RD": {
"Box": "iMC",
"Category": "iMC PREEMPTION Events",
"Counters": "0-3",
"Defn": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
"Desc": "Read Preemption Count",
"EvSel": 8,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.PRE_COUNT": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
},
"iMC.PRE_COUNT.BYP": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
"Umask": "bxxx1xxxx",
},
"iMC.PRE_COUNT.PAGE_MISS": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.PRE_COUNT.RD": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.PRE_COUNT.PAGE_CLOSE": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.PRE_COUNT.WR": {
"Box": "iMC",
"Category": "iMC PRE Events",
"Counters": "0-3",
"Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
"Desc": "DRAM Precharge commands.",
"EvSel": 2,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.RD_CAS_PRIO": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"EvSel": 160,
"ExtSel": "",
},
"iMC.RD_CAS_PRIO.HIGH": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"EvSel": 160,
"ExtSel": "",
"Umask": "bxxxxx1xx",
},
"iMC.RD_CAS_PRIO.PANIC": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"EvSel": 160,
"ExtSel": "",
"Umask": "bxxxx1xxx",
},
"iMC.RD_CAS_PRIO.MED": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"EvSel": 160,
"ExtSel": "",
"Umask": "bxxxxxx1x",
},
"iMC.RD_CAS_PRIO.LOW": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"EvSel": 160,
"ExtSel": "",
"Umask": "bxxxxxxx1",
},
"iMC.RD_CAS_RANK0": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
},
"iMC.RD_CAS_RANK0.BANK14": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001110",
},
"iMC.RD_CAS_RANK0.BANK0": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000000",
},
"iMC.RD_CAS_RANK0.BANK13": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001101",
},
"iMC.RD_CAS_RANK0.BANKG2": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00010011",
},
"iMC.RD_CAS_RANK0.BANK5": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000101",
},
"iMC.RD_CAS_RANK0.ALLBANKS": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00010000",
},
"iMC.RD_CAS_RANK0.BANK2": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000010",
},
"iMC.RD_CAS_RANK0.BANK9": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001001",
},
"iMC.RD_CAS_RANK0.BANK8": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001000",
},
"iMC.RD_CAS_RANK0.BANK3": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000011",
},
"iMC.RD_CAS_RANK0.BANK4": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000100",
},
"iMC.RD_CAS_RANK0.BANK10": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001010",
},
"iMC.RD_CAS_RANK0.BANK1": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000001",
},
"iMC.RD_CAS_RANK0.BANKG0": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00010001",
},
"iMC.RD_CAS_RANK0.BANK6": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000110",
},
"iMC.RD_CAS_RANK0.BANKG3": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00010100",
},
"iMC.RD_CAS_RANK0.BANK15": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001111",
},
"iMC.RD_CAS_RANK0.BANK7": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00000111",
},
"iMC.RD_CAS_RANK0.BANK12": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001100",
},
"iMC.RD_CAS_RANK0.BANK11": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00001011",
},
"iMC.RD_CAS_RANK0.BANKG1": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 0",
"EvSel": 176,
"ExtSel": "",
"Umask": "b00010010",
},
"iMC.RD_CAS_RANK1": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
},
"iMC.RD_CAS_RANK1.BANK2": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00000010",
},
"iMC.RD_CAS_RANK1.ALLBANKS": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00010000",
},
"iMC.RD_CAS_RANK1.BANK13": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00001101",
},
"iMC.RD_CAS_RANK1.BANKG2": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00010011",
},
"iMC.RD_CAS_RANK1.BANK5": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00000101",
},
"iMC.RD_CAS_RANK1.BANK0": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00000000",
},
"iMC.RD_CAS_RANK1.BANK14": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00001110",
},
"iMC.RD_CAS_RANK1.BANK11": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00001011",
},
"iMC.RD_CAS_RANK1.BANKG1": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00010010",
},
"iMC.RD_CAS_RANK1.BANK12": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
"Umask": "b00001100",
},
"iMC.RD_CAS_RANK1.BANK7": {
"Box": "iMC",
"Category": "iMC CAS Events",
"Counters": "0-3",
"Desc": "RD_CAS Access to Rank 1",
"EvSel": 177,
"ExtSel": "",
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