A small C compiler

Samples for CUDA Developers which demonstrates features in CUDA Toolkit

GNU toolchain for RISC-V, including GCC

Spike, a RISC-V ISA Simulator

GPGPU microprocessor architecture

Vitis In-Depth Tutorials

Documentation of NVIDIA chip/hardware interfaces

The official SuiteSparse library: a suite of sparse matrix algorithms authored or co-authored by Tim Davis, Texas A&M University.

METIS - Serial Graph Partitioning and Fill-reducing Matrix Ordering

Parallel solvers for sparse linear systems featuring multigrid methods.

RISC-V Proxy Kernel

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISC-V SystemC-TLM simulator

Supernodal sparse direct solver. https://portal.nersc.gov/project/sparse/superlu/

Dynamic Memory Management for Serving LLMs without PagedAttention

Distributed memory, MPI based SuperLU

PanguLU: A Scalable Regular Two-Dimensional Block-Cyclic Sparse Direct Solver on Distributed Heterogeneous Systems