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example5.ok
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example5.ok
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Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Corner: ss
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ in1 (in)
0.00 0.00 ^ r1/D (DFF_X1)
0.00 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ r1/CK (DFF_X1)
0.01 0.01 library hold time
0.01 data required time
---------------------------------------------------------
0.01 data required time
-0.00 data arrival time
---------------------------------------------------------
-0.01 slack (VIOLATED)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Corner: ss
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ r2/CK (DFF_X1)
0.26 0.26 v r2/Q (DFF_X1)
0.09 0.35 v u1/Z (BUF_X1)
0.11 0.46 v u2/ZN (AND2_X1)
0.00 0.46 v r3/D (DFF_X1)
0.46 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ r3/CK (DFF_X1)
-0.16 9.84 library setup time
9.84 data required time
---------------------------------------------------------
9.84 data required time
-0.46 data arrival time
---------------------------------------------------------
9.38 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Corner: tt
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ r2/CK (DFF_X1)
0.09 0.09 v r2/Q (DFF_X1)
0.03 0.11 v u1/Z (BUF_X1)
0.03 0.14 v u2/ZN (AND2_X1)
0.00 0.14 v r3/D (DFF_X1)
0.14 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ r3/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-0.14 data arrival time
---------------------------------------------------------
9.82 slack (MET)