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2 stars written in SystemVerilog
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A Verilog synthesis flow for Minecraft redstone circuits

SystemVerilog 1,157 26 Updated Nov 25, 2020

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

SystemVerilog 368 75 Updated Sep 14, 2023