forked from zephyrproject-rtos/zephyr
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathusb_dc_dw.c
1221 lines (985 loc) · 27.9 KB
/
usb_dc_dw.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* usb_dc_dw.c - USB DesignWare device controller driver */
#define DT_DRV_COMPAT snps_designware_usb
/*
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB DesignWare device controller driver
*
* USB DesignWare device controller driver. The driver implements the low
* level control routines to deal directly with the hardware.
*/
#include <string.h>
#include <stdio.h>
#include <sys/byteorder.h>
#include <usb/usb_device.h>
#include "usb_dw_registers.h"
#include <soc.h>
#define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(usb_dc_dw);
/* convert from endpoint address to hardware endpoint index */
#define USB_DW_EP_ADDR2IDX(ep) ((ep) & ~USB_EP_DIR_MASK)
/* get direction from endpoint address */
#define USB_DW_EP_ADDR2DIR(ep) ((ep) & USB_EP_DIR_MASK)
/* convert from hardware endpoint index and direction to endpoint address */
#define USB_DW_EP_IDX2ADDR(idx, dir) ((idx) | ((dir) & USB_EP_DIR_MASK))
/* Number of SETUP back-to-back packets */
#define USB_DW_SUP_CNT (1)
/*
* USB endpoint private structure.
*/
struct usb_ep_ctrl_prv {
u8_t ep_ena;
u8_t fifo_num;
u32_t fifo_size;
u16_t mps; /* Max ep pkt size */
usb_dc_ep_callback cb;/* Endpoint callback function */
u32_t data_len;
};
/*
* USB controller private structure.
*/
struct usb_dw_ctrl_prv {
usb_dc_status_callback status_cb;
struct usb_ep_ctrl_prv in_ep_ctrl[USB_DW_IN_EP_NUM];
struct usb_ep_ctrl_prv out_ep_ctrl[USB_DW_OUT_EP_NUM];
int n_tx_fifos;
u8_t attached;
};
static struct usb_dw_ctrl_prv usb_dw_ctrl;
static void usb_dw_reg_dump(void)
{
u8_t i;
LOG_DBG("USB registers: GOTGCTL : 0x%x GOTGINT : 0x%x GAHBCFG : "
"0x%x", USB_DW->gotgctl, USB_DW->gotgint, USB_DW->gahbcfg);
LOG_DBG(" GUSBCFG : 0x%x GINTSTS : 0x%x GINTMSK : 0x%x",
USB_DW->gusbcfg, USB_DW->gintsts, USB_DW->gintmsk);
LOG_DBG(" DCFG : 0x%x DCTL : 0x%x DSTS : 0x%x",
USB_DW->dcfg, USB_DW->dctl, USB_DW->dsts);
LOG_DBG(" DIEPMSK : 0x%x DOEPMSK : 0x%x DAINT : 0x%x",
USB_DW->diepmsk, USB_DW->doepmsk, USB_DW->daint);
LOG_DBG(" DAINTMSK: 0x%x GHWCFG1 : 0x%x GHWCFG2 : 0x%x",
USB_DW->daintmsk, USB_DW->ghwcfg1, USB_DW->ghwcfg2);
LOG_DBG(" GHWCFG3 : 0x%x GHWCFG4 : 0x%x",
USB_DW->ghwcfg3, USB_DW->ghwcfg4);
for (i = 0U; i < USB_DW_OUT_EP_NUM; i++) {
LOG_DBG("\n EP %d registers: DIEPCTL : 0x%x DIEPINT : "
"0x%x", i, USB_DW->in_ep_reg[i].diepctl,
USB_DW->in_ep_reg[i].diepint);
LOG_DBG(" DIEPTSIZ: 0x%x DIEPDMA : 0x%x DOEPCTL : "
"0x%x", USB_DW->in_ep_reg[i].dieptsiz,
USB_DW->in_ep_reg[i].diepdma,
USB_DW->out_ep_reg[i].doepctl);
LOG_DBG(" DOEPINT : 0x%x DOEPTSIZ: 0x%x DOEPDMA : "
"0x%x", USB_DW->out_ep_reg[i].doepint,
USB_DW->out_ep_reg[i].doeptsiz,
USB_DW->out_ep_reg[i].doepdma);
}
}
static u8_t usb_dw_ep_is_valid(u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
/* Check if ep enabled */
if ((USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) &&
ep_idx < USB_DW_OUT_EP_NUM) {
return 1;
} else if ((USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_IN) &&
ep_idx < USB_DW_IN_EP_NUM) {
return 1;
}
return 0;
}
static u8_t usb_dw_ep_is_enabled(u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
/* Check if ep enabled */
if ((USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) &&
usb_dw_ctrl.out_ep_ctrl[ep_idx].ep_ena) {
return 1;
} else if ((USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_IN) &&
usb_dw_ctrl.in_ep_ctrl[ep_idx].ep_ena) {
return 1;
}
return 0;
}
static inline void usb_dw_udelay(u32_t us)
{
k_busy_wait(us);
}
static int usb_dw_reset(void)
{
u32_t cnt = 0U;
/* Wait for AHB master idle state. */
while (!(USB_DW->grstctl & USB_DW_GRSTCTL_AHB_IDLE)) {
usb_dw_udelay(1);
if (++cnt > USB_DW_CORE_RST_TIMEOUT_US) {
LOG_ERR("USB reset HANG! AHB Idle GRSTCTL=0x%08x",
USB_DW->grstctl);
return -EIO;
}
}
/* Core Soft Reset */
cnt = 0U;
USB_DW->grstctl |= USB_DW_GRSTCTL_C_SFT_RST;
do {
if (++cnt > USB_DW_CORE_RST_TIMEOUT_US) {
LOG_DBG("USB reset HANG! Soft Reset GRSTCTL=0x%08x",
USB_DW->grstctl);
return -EIO;
}
usb_dw_udelay(1);
} while (USB_DW->grstctl & USB_DW_GRSTCTL_C_SFT_RST);
/* Wait for 3 PHY Clocks */
usb_dw_udelay(100);
return 0;
}
static int usb_dw_num_dev_eps(void)
{
return (USB_DW->ghwcfg2 >> 10) & 0xf;
}
static void usb_dw_flush_tx_fifo(int ep)
{
int fnum = usb_dw_ctrl.in_ep_ctrl[ep].fifo_num;
USB_DW->grstctl = (fnum << 6) | (1<<5);
while (USB_DW->grstctl & (1<<5)) {
}
}
static int usb_dw_tx_fifo_avail(int ep)
{
return USB_DW->in_ep_reg[ep].dtxfsts &
USB_DW_DTXFSTS_TXF_SPC_AVAIL_MASK;
}
/* Choose a FIFO number for an IN endpoint */
static int usb_dw_set_fifo(u8_t ep)
{
int ep_idx = USB_DW_EP_ADDR2IDX(ep);
volatile u32_t *reg = &USB_DW->in_ep_reg[ep_idx].diepctl;
u32_t val;
int fifo = 0;
int ded_fifo = !!(USB_DW->ghwcfg4 & USB_DW_HWCFG4_DEDFIFOMODE);
if (!ded_fifo) {
/* No support for shared-FIFO mode yet, existing
* Zephyr hardware doesn't use it
*/
return -ENOTSUP;
}
/* In dedicated-FIFO mode, all IN endpoints must have a unique
* FIFO number associated with them in the TXFNUM field of
* DIEPCTLx, with EP0 always being assigned to FIFO zero (the
* reset default, so we don't touch it).
*
* FIXME: would be better (c.f. the dwc2 driver in Linux) to
* choose a FIFO based on the hardware depth: we want the
* smallest one that fits our configured maximum packet size
* for the endpoint. This just picks the next available one.
*/
if (ep_idx != 0) {
fifo = ++usb_dw_ctrl.n_tx_fifos;
if (fifo >= usb_dw_num_dev_eps()) {
return -EINVAL;
}
reg = &USB_DW->in_ep_reg[ep_idx].diepctl;
val = *reg & ~USB_DW_DEPCTL_TXFNUM_MASK;
val |= fifo << USB_DW_DEPCTL_TXFNUM_OFFSET;
*reg = val;
}
usb_dw_ctrl.in_ep_ctrl[ep_idx].fifo_num = fifo;
usb_dw_flush_tx_fifo(ep_idx);
val = usb_dw_tx_fifo_avail(ep_idx);
usb_dw_ctrl.in_ep_ctrl[ep_idx].fifo_size = val;
return 0;
}
static int usb_dw_ep_set(u8_t ep,
u32_t ep_mps, enum usb_dc_ep_type ep_type)
{
volatile u32_t *p_depctl;
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
LOG_DBG("%s ep %x, mps %d, type %d", __func__, ep, ep_mps, ep_type);
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
p_depctl = &USB_DW->out_ep_reg[ep_idx].doepctl;
usb_dw_ctrl.out_ep_ctrl[ep_idx].mps = ep_mps;
} else {
p_depctl = &USB_DW->in_ep_reg[ep_idx].diepctl;
usb_dw_ctrl.in_ep_ctrl[ep_idx].mps = ep_mps;
}
if (!ep_idx) {
/* Set max packet size for EP0 */
*p_depctl &= ~USB_DW_DEPCTL0_MSP_MASK;
switch (ep_mps) {
case 8:
*p_depctl |= USB_DW_DEPCTL0_MSP_8 <<
USB_DW_DEPCTL_MSP_OFFSET;
break;
case 16:
*p_depctl |= USB_DW_DEPCTL0_MSP_16 <<
USB_DW_DEPCTL_MSP_OFFSET;
break;
case 32:
*p_depctl |= USB_DW_DEPCTL0_MSP_32 <<
USB_DW_DEPCTL_MSP_OFFSET;
break;
case 64:
*p_depctl |= USB_DW_DEPCTL0_MSP_64 <<
USB_DW_DEPCTL_MSP_OFFSET;
break;
default:
return -EINVAL;
}
/* No need to set EP0 type */
} else {
/* Set max packet size for EP */
if (ep_mps > (USB_DW_DEPCTLn_MSP_MASK >>
USB_DW_DEPCTL_MSP_OFFSET)) {
return -EINVAL;
}
*p_depctl &= ~USB_DW_DEPCTLn_MSP_MASK;
*p_depctl |= ep_mps << USB_DW_DEPCTL_MSP_OFFSET;
/* Set endpoint type */
*p_depctl &= ~USB_DW_DEPCTL_EP_TYPE_MASK;
switch (ep_type) {
case USB_DC_EP_CONTROL:
*p_depctl |= USB_DW_DEPCTL_EP_TYPE_CONTROL <<
USB_DW_DEPCTL_EP_TYPE_OFFSET;
break;
case USB_DC_EP_BULK:
*p_depctl |= USB_DW_DEPCTL_EP_TYPE_BULK <<
USB_DW_DEPCTL_EP_TYPE_OFFSET;
break;
case USB_DC_EP_INTERRUPT:
*p_depctl |= USB_DW_DEPCTL_EP_TYPE_INTERRUPT <<
USB_DW_DEPCTL_EP_TYPE_OFFSET;
break;
default:
return -EINVAL;
}
/* sets the Endpoint Data PID to DATA0 */
*p_depctl |= USB_DW_DEPCTL_SETDOPID;
}
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_IN) {
int ret = usb_dw_set_fifo(ep);
if (ret) {
return ret;
}
}
return 0;
}
static void usb_dw_prep_rx(const u8_t ep, u8_t setup)
{
enum usb_dw_out_ep_idx ep_idx = USB_DW_EP_ADDR2IDX(ep);
u32_t ep_mps = usb_dw_ctrl.out_ep_ctrl[ep_idx].mps;
/* Set max RX size to EP mps so we get an interrupt
* each time a packet is received
*/
USB_DW->out_ep_reg[ep_idx].doeptsiz =
(USB_DW_SUP_CNT << USB_DW_DOEPTSIZ_SUP_CNT_OFFSET) |
(1 << USB_DW_DEPTSIZ_PKT_CNT_OFFSET) | ep_mps;
/* Clear NAK and enable ep */
if (!setup) {
USB_DW->out_ep_reg[ep_idx].doepctl |= USB_DW_DEPCTL_CNAK;
}
USB_DW->out_ep_reg[ep_idx].doepctl |= USB_DW_DEPCTL_EP_ENA;
LOG_DBG("USB OUT EP%d armed", ep_idx);
}
static int usb_dw_tx(u8_t ep, const u8_t *const data,
u32_t data_len)
{
enum usb_dw_in_ep_idx ep_idx = USB_DW_EP_ADDR2IDX(ep);
u32_t max_xfer_size, max_pkt_cnt, pkt_cnt, avail_space;
u32_t ep_mps = usb_dw_ctrl.in_ep_ctrl[ep_idx].mps;
unsigned int key;
u32_t i;
/* Wait for FIFO space available */
do {
avail_space = usb_dw_tx_fifo_avail(ep_idx);
if (avail_space == usb_dw_ctrl.in_ep_ctrl[ep_idx].fifo_size) {
break;
}
/* Make sure we don't hog the CPU */
k_yield();
} while (1);
key = irq_lock();
avail_space *= 4U;
if (!avail_space) {
LOG_ERR("USB IN EP%d no space available, DTXFSTS %x", ep_idx,
USB_DW->in_ep_reg[ep_idx].dtxfsts);
irq_unlock(key);
return -EAGAIN;
}
/* For now tx-fifo sizes are not configured (cf usb_dw_set_fifo). Here
* we force available fifo size to be a multiple of ep mps in order to
* prevent splitting data incorrectly.
*/
avail_space -= avail_space % ep_mps;
if (data_len > avail_space) {
data_len = avail_space;
}
if (data_len != 0U) {
/* Get max packet size and packet count for ep */
if (ep_idx == USB_DW_IN_EP_0) {
max_pkt_cnt =
USB_DW_DIEPTSIZ0_PKT_CNT_MASK >>
USB_DW_DEPTSIZ_PKT_CNT_OFFSET;
max_xfer_size =
USB_DW_DEPTSIZ0_XFER_SIZE_MASK >>
USB_DW_DEPTSIZ_XFER_SIZE_OFFSET;
} else {
max_pkt_cnt =
USB_DW_DIEPTSIZn_PKT_CNT_MASK >>
USB_DW_DEPTSIZ_PKT_CNT_OFFSET;
max_xfer_size =
USB_DW_DEPTSIZn_XFER_SIZE_MASK >>
USB_DW_DEPTSIZ_XFER_SIZE_OFFSET;
}
/* Check if transfer len is too big */
if (data_len > max_xfer_size) {
LOG_WRN("USB IN EP%d len too big (%d->%d)", ep_idx,
data_len, max_xfer_size);
data_len = max_xfer_size;
}
/*
* Program the transfer size and packet count as follows:
*
* transfer size = N * ep_maxpacket + short_packet
* pktcnt = N + (short_packet exist ? 1 : 0)
*/
pkt_cnt = (data_len + ep_mps - 1) / ep_mps;
if (pkt_cnt > max_pkt_cnt) {
LOG_WRN("USB IN EP%d pkt count too big (%d->%d)",
ep_idx, pkt_cnt, pkt_cnt);
pkt_cnt = max_pkt_cnt;
data_len = pkt_cnt * ep_mps;
}
} else {
/* Zero length packet */
pkt_cnt = 1U;
}
/* Set number of packets and transfer size */
USB_DW->in_ep_reg[ep_idx].dieptsiz =
(pkt_cnt << USB_DW_DEPTSIZ_PKT_CNT_OFFSET) | data_len;
/* Clear NAK and enable ep */
USB_DW->in_ep_reg[ep_idx].diepctl |= (USB_DW_DEPCTL_EP_ENA |
USB_DW_DEPCTL_CNAK);
/*
* Write data to FIFO, make sure that we are protected against
* other USB register accesses. According to "DesignWare Cores
* USB 1.1/2.0 Device Subsystem-AHB/VCI Databook": "During FIFO
* access, the application must not access the UDC/Subsystem
* registers or vendor registers (for ULPI mode). After starting
* to access a FIFO, the application must complete the transaction
* before accessing the register."
*/
for (i = 0U; i < data_len; i += 4U) {
u32_t val = data[i];
if (i + 1 < data_len) {
val |= ((u32_t)data[i+1]) << 8;
}
if (i + 2 < data_len) {
val |= ((u32_t)data[i+2]) << 16;
}
if (i + 3 < data_len) {
val |= ((u32_t)data[i+3]) << 24;
}
USB_DW_EP_FIFO(ep_idx) = val;
}
irq_unlock(key);
LOG_DBG("USB IN EP%d write %u bytes", ep_idx, data_len);
return data_len;
}
static int usb_dw_init(void)
{
u8_t ep;
int ret;
ret = usb_dw_reset();
if (ret) {
return ret;
}
#ifdef CONFIG_USB_DW_USB_2_0
/* set the PHY interface to be 16-bit UTMI */
USB_DW->gusbcfg = (USB_DW->gusbcfg & ~USB_DW_GUSBCFG_PHY_IF_MASK) |
USB_DW_GUSBCFG_PHY_IF_16_BIT;
/* Set USB2.0 High Speed */
USB_DW->dcfg |= USB_DW_DCFG_DEV_SPD_USB2_HS;
#else
/* Set device speed to Full Speed */
USB_DW->dcfg |= USB_DW_DCFG_DEV_SPD_FS;
#endif
/* Set NAK for all OUT EPs */
for (ep = 0U; ep < USB_DW_OUT_EP_NUM; ep++) {
USB_DW->out_ep_reg[ep].doepctl = USB_DW_DEPCTL_SNAK;
}
/* Enable global interrupts */
USB_DW->gintmsk = USB_DW_GINTSTS_OEP_INT |
USB_DW_GINTSTS_IEP_INT |
USB_DW_GINTSTS_ENUM_DONE |
USB_DW_GINTSTS_USB_RST |
USB_DW_GINTSTS_WK_UP_INT |
USB_DW_GINTSTS_USB_SUSP;
/* Enable global interrupt */
USB_DW->gahbcfg |= USB_DW_GAHBCFG_GLB_INTR_MASK;
/* Disable soft disconnect */
USB_DW->dctl &= ~USB_DW_DCTL_SFT_DISCON;
usb_dw_reg_dump();
return 0;
}
static void usb_dw_handle_reset(void)
{
LOG_DBG("USB RESET event");
/* Inform upper layers */
if (usb_dw_ctrl.status_cb) {
usb_dw_ctrl.status_cb(USB_DC_RESET, NULL);
}
/* Clear device address during reset. */
USB_DW->dcfg &= ~USB_DW_DCFG_DEV_ADDR_MASK;
/* enable global EP interrupts */
USB_DW->doepmsk = 0U;
USB_DW->gintmsk |= USB_DW_GINTSTS_RX_FLVL;
USB_DW->diepmsk |= USB_DW_DIEPINT_XFER_COMPL;
}
static void usb_dw_handle_enum_done(void)
{
u32_t speed;
speed = (USB_DW->dsts & ~USB_DW_DSTS_ENUM_SPD_MASK) >>
USB_DW_DSTS_ENUM_SPD_OFFSET;
LOG_DBG("USB ENUM DONE event, %s speed detected",
speed == USB_DW_DSTS_ENUM_LS ? "Low" : "Full");
/* Inform upper layers */
if (usb_dw_ctrl.status_cb) {
usb_dw_ctrl.status_cb(USB_DC_CONNECTED, NULL);
}
}
/* USB ISR handler */
static inline void usb_dw_int_rx_flvl_handler(void)
{
u32_t grxstsp = USB_DW->grxstsp;
u32_t status, xfer_size;
u8_t ep_idx;
usb_dc_ep_callback ep_cb;
/* Packet in RX FIFO */
ep_idx = grxstsp & USB_DW_GRXSTSR_EP_NUM_MASK;
status = (grxstsp & USB_DW_GRXSTSR_PKT_STS_MASK) >>
USB_DW_GRXSTSR_PKT_STS_OFFSET;
xfer_size = (grxstsp & USB_DW_GRXSTSR_PKT_CNT_MASK) >>
USB_DW_GRXSTSR_PKT_CNT_OFFSET;
LOG_DBG("USB OUT EP%u: RX_FLVL status %u, size %u",
ep_idx, status, xfer_size);
usb_dw_ctrl.out_ep_ctrl[ep_idx].data_len = xfer_size;
ep_cb = usb_dw_ctrl.out_ep_ctrl[ep_idx].cb;
switch (status) {
case USB_DW_GRXSTSR_PKT_STS_SETUP:
/* Call the registered callback if any */
if (ep_cb) {
ep_cb(USB_DW_EP_IDX2ADDR(ep_idx, USB_EP_DIR_OUT),
USB_DC_EP_SETUP);
}
break;
case USB_DW_GRXSTSR_PKT_STS_OUT_DATA:
if (ep_cb) {
ep_cb(USB_DW_EP_IDX2ADDR(ep_idx, USB_EP_DIR_OUT),
USB_DC_EP_DATA_OUT);
}
break;
case USB_DW_GRXSTSR_PKT_STS_OUT_DATA_DONE:
case USB_DW_GRXSTSR_PKT_STS_SETUP_DONE:
break;
default:
break;
}
}
static inline void usb_dw_int_iep_handler(void)
{
u32_t ep_int_status;
u8_t ep_idx;
usb_dc_ep_callback ep_cb;
for (ep_idx = 0U; ep_idx < USB_DW_IN_EP_NUM; ep_idx++) {
if (USB_DW->daint & USB_DW_DAINT_IN_EP_INT(ep_idx)) {
/* Read IN EP interrupt status */
ep_int_status = USB_DW->in_ep_reg[ep_idx].diepint &
USB_DW->diepmsk;
/* Clear IN EP interrupts */
USB_DW->in_ep_reg[ep_idx].diepint = ep_int_status;
LOG_DBG("USB IN EP%u interrupt status: 0x%x",
ep_idx, ep_int_status);
ep_cb = usb_dw_ctrl.in_ep_ctrl[ep_idx].cb;
if (ep_cb &&
(ep_int_status & USB_DW_DIEPINT_XFER_COMPL)) {
/* Call the registered callback */
ep_cb(USB_DW_EP_IDX2ADDR(ep_idx, USB_EP_DIR_IN),
USB_DC_EP_DATA_IN);
}
}
}
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_IEP_INT;
}
static inline void usb_dw_int_oep_handler(void)
{
u32_t ep_int_status;
u8_t ep_idx;
for (ep_idx = 0U; ep_idx < USB_DW_OUT_EP_NUM; ep_idx++) {
if (USB_DW->daint & USB_DW_DAINT_OUT_EP_INT(ep_idx)) {
/* Read OUT EP interrupt status */
ep_int_status = USB_DW->out_ep_reg[ep_idx].doepint &
USB_DW->doepmsk;
/* Clear OUT EP interrupts */
USB_DW->out_ep_reg[ep_idx].doepint = ep_int_status;
LOG_DBG("USB OUT EP%u interrupt status: 0x%x\n",
ep_idx, ep_int_status);
}
}
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_OEP_INT;
}
static void usb_dw_isr_handler(void *unused)
{
u32_t int_status;
ARG_UNUSED(unused);
/* Read interrupt status */
while ((int_status = (USB_DW->gintsts & USB_DW->gintmsk))) {
LOG_DBG("USB GINTSTS 0x%x", int_status);
if (int_status & USB_DW_GINTSTS_USB_RST) {
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_USB_RST;
/* Reset detected */
usb_dw_handle_reset();
}
if (int_status & USB_DW_GINTSTS_ENUM_DONE) {
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_ENUM_DONE;
/* Enumeration done detected */
usb_dw_handle_enum_done();
}
if (int_status & USB_DW_GINTSTS_USB_SUSP) {
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_USB_SUSP;
if (usb_dw_ctrl.status_cb) {
usb_dw_ctrl.status_cb(USB_DC_SUSPEND, NULL);
}
}
if (int_status & USB_DW_GINTSTS_WK_UP_INT) {
/* Clear interrupt. */
USB_DW->gintsts = USB_DW_GINTSTS_WK_UP_INT;
if (usb_dw_ctrl.status_cb) {
usb_dw_ctrl.status_cb(USB_DC_RESUME, NULL);
}
}
if (int_status & USB_DW_GINTSTS_RX_FLVL) {
/* Packet in RX FIFO */
usb_dw_int_rx_flvl_handler();
}
if (int_status & USB_DW_GINTSTS_IEP_INT) {
/* IN EP interrupt */
usb_dw_int_iep_handler();
}
if (int_status & USB_DW_GINTSTS_OEP_INT) {
/* No OUT interrupt expected in FIFO mode,
* just clear interruot
*/
usb_dw_int_oep_handler();
}
}
}
int usb_dc_attach(void)
{
int ret;
if (usb_dw_ctrl.attached) {
return 0;
}
ret = usb_dw_init();
if (ret) {
return ret;
}
/* Connect and enable USB interrupt */
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
usb_dw_isr_handler, 0,
DT_INST_IRQ(0, sense));
irq_enable(DT_INST_IRQN(0));
usb_dw_ctrl.attached = 1U;
return 0;
}
int usb_dc_detach(void)
{
if (!usb_dw_ctrl.attached) {
return 0;
}
irq_disable(DT_INST_IRQN(0));
/* Enable soft disconnect */
USB_DW->dctl |= USB_DW_DCTL_SFT_DISCON;
usb_dw_ctrl.attached = 0U;
return 0;
}
int usb_dc_reset(void)
{
int ret;
ret = usb_dw_reset();
/* Clear private data */
(void)memset(&usb_dw_ctrl, 0, sizeof(usb_dw_ctrl));
return ret;
}
int usb_dc_set_address(const u8_t addr)
{
if (addr > (USB_DW_DCFG_DEV_ADDR_MASK >> USB_DW_DCFG_DEV_ADDR_OFFSET)) {
return -EINVAL;
}
USB_DW->dcfg &= ~USB_DW_DCFG_DEV_ADDR_MASK;
USB_DW->dcfg |= addr << USB_DW_DCFG_DEV_ADDR_OFFSET;
return 0;
}
int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(cfg->ep_addr);
LOG_DBG("ep %x, mps %d, type %d", cfg->ep_addr, cfg->ep_mps,
cfg->ep_type);
if ((cfg->ep_type == USB_DC_EP_CONTROL) && ep_idx) {
LOG_ERR("invalid endpoint configuration");
return -1;
}
if (cfg->ep_mps > DW_USB_MAX_PACKET_SIZE) {
LOG_WRN("unsupported packet size");
return -1;
}
if ((USB_DW_EP_ADDR2DIR(cfg->ep_addr) == USB_EP_DIR_OUT) &&
(ep_idx >= DW_USB_OUT_EP_NUM)) {
LOG_WRN("OUT endpoint address out of range");
return -1;
}
if ((USB_DW_EP_ADDR2DIR(cfg->ep_addr) == USB_EP_DIR_IN) &&
(ep_idx >= DW_USB_IN_EP_NUM)) {
LOG_WRN("IN endpoint address out of range");
return -1;
}
return 0;
}
int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)
{
u8_t ep;
if (!ep_cfg) {
return -EINVAL;
}
ep = ep_cfg->ep_addr;
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
usb_dw_ep_set(ep, ep_cfg->ep_mps, ep_cfg->ep_type);
return 0;
}
int usb_dc_ep_set_stall(const u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->out_ep_reg[ep_idx].doepctl |= USB_DW_DEPCTL_STALL;
} else {
USB_DW->in_ep_reg[ep_idx].diepctl |= USB_DW_DEPCTL_STALL;
}
return 0;
}
int usb_dc_ep_clear_stall(const u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
if (!ep_idx) {
/* Not possible to clear stall for EP0 */
return -EINVAL;
}
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->out_ep_reg[ep_idx].doepctl &= ~USB_DW_DEPCTL_STALL;
} else {
USB_DW->in_ep_reg[ep_idx].diepctl &= ~USB_DW_DEPCTL_STALL;
}
return 0;
}
int usb_dc_ep_halt(const u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
volatile u32_t *p_depctl;
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
if (!ep_idx) {
/* Cannot disable EP0, just set stall */
usb_dc_ep_set_stall(ep);
} else {
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
p_depctl = &USB_DW->out_ep_reg[ep_idx].doepctl;
} else {
p_depctl = &USB_DW->in_ep_reg[ep_idx].diepctl;
}
/* Set STALL and disable endpoint if enabled */
if (*p_depctl & USB_DW_DEPCTL_EP_ENA) {
*p_depctl |= USB_DW_DEPCTL_EP_DIS | USB_DW_DEPCTL_STALL;
} else {
*p_depctl |= USB_DW_DEPCTL_STALL;
}
}
return 0;
}
int usb_dc_ep_is_stalled(const u8_t ep, u8_t *const stalled)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
if (!stalled) {
return -EINVAL;
}
*stalled = 0U;
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
if (USB_DW->out_ep_reg[ep_idx].doepctl & USB_DW_DEPCTL_STALL) {
*stalled = 1U;
}
} else {
if (USB_DW->in_ep_reg[ep_idx].diepctl & USB_DW_DEPCTL_STALL) {
*stalled = 1U;
}
}
return 0;
}
int usb_dc_ep_enable(const u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
/* enable EP interrupts */
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->daintmsk |= USB_DW_DAINT_OUT_EP_INT(ep_idx);
} else {
USB_DW->daintmsk |= USB_DW_DAINT_IN_EP_INT(ep_idx);
}
/* Activate Ep */
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->out_ep_reg[ep_idx].doepctl |= USB_DW_DEPCTL_USB_ACT_EP;
usb_dw_ctrl.out_ep_ctrl[ep_idx].ep_ena = 1U;
} else {
USB_DW->in_ep_reg[ep_idx].diepctl |= USB_DW_DEPCTL_USB_ACT_EP;
usb_dw_ctrl.in_ep_ctrl[ep_idx].ep_ena = 1U;
}
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT &&
usb_dw_ctrl.out_ep_ctrl[ep_idx].cb != usb_transfer_ep_callback) {
/* Start reading now, except for transfer managed eps */
usb_dw_prep_rx(ep, 0);
}
return 0;
}
int usb_dc_ep_disable(const u8_t ep)
{
u8_t ep_idx = USB_DW_EP_ADDR2IDX(ep);
if (!usb_dw_ctrl.attached || !usb_dw_ep_is_valid(ep)) {
LOG_ERR("Not attached / Invalid endpoint: EP 0x%x", ep);
return -EINVAL;
}
/* Disable EP interrupts */
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->daintmsk &= ~USB_DW_DAINT_OUT_EP_INT(ep_idx);
USB_DW->doepmsk &= ~USB_DW_DOEPINT_SET_UP;
} else {
USB_DW->daintmsk &= ~USB_DW_DAINT_IN_EP_INT(ep_idx);
USB_DW->diepmsk &= ~USB_DW_DIEPINT_XFER_COMPL;
USB_DW->gintmsk &= ~USB_DW_GINTSTS_RX_FLVL;
}
/* De-activate, disable and set NAK for Ep */
if (USB_DW_EP_ADDR2DIR(ep) == USB_EP_DIR_OUT) {
USB_DW->out_ep_reg[ep_idx].doepctl &=
~(USB_DW_DEPCTL_USB_ACT_EP |
USB_DW_DEPCTL_EP_ENA |
USB_DW_DEPCTL_SNAK);
usb_dw_ctrl.out_ep_ctrl[ep_idx].ep_ena = 0U;
} else {
USB_DW->in_ep_reg[ep_idx].diepctl &=
~(USB_DW_DEPCTL_USB_ACT_EP |
USB_DW_DEPCTL_EP_ENA |
USB_DW_DEPCTL_SNAK);
usb_dw_ctrl.in_ep_ctrl[ep_idx].ep_ena = 0U;
}
return 0;
}