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Commits on Sep 25, 2017

• Merge pull request VerticalResearchGroup#20 from cousteaulecommandant/patch-1

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  zwabbit

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Commits on Sep 20, 2017

• fpga_make.sh: /bin/sh -> /bin/bash

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  cousteaulecommandant

  authored
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Commits on Apr 25, 2016

• Merge pull request VerticalResearchGroup#12 from d1duarte/patch-4

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  vinaygangadhar

  committed
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• Corrected the 'v_RCP_F32' instruction so it produces the correct results.

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  d1duarte

  committed
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Commits on Apr 19, 2016

• A variety of data width fixes. Use more wildcards in sensitivity lists to shut up warnings in Vivado.

  zwabbit

  committed
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• Add a bunch of logic to the AXI interface that was accidentally left out.

  zwabbit

  committed
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• Fix inferred latch of VGPR address in LSU opcode decoder. Just use wildcard for sensitivity list in decode flag generator.

  zwabbit

  committed
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Commits on Apr 18, 2016

• More syntax error fixes and a logic bug with the mb to mem interface.

  zwabbit

  committed
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• Switch over the axi peripheral code to the passthrough version.

  zwabbit

  committed
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• Fix syntax errors.

  zwabbit

  committed
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• Use a tab for the Makefile.

  zwabbit

  committed
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• Add baseline compute_unit module into FPGA build.

  zwabbit

  committed
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• Fix up a couple of net names.

  zwabbit

  committed
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Commits on Apr 15, 2016

• Massively overhaul the top level modules for MIAOW and NEKO. Still in progress.

  zwabbit

  committed
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Commits on Apr 13, 2016

• Synchronize the LSU changes to the FPGA specific modules.

  zwabbit

  committed
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Commits on Apr 4, 2016

• Merge pull request VerticalResearchGroup#10 from d1duarte/patch-3

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  zwabbit

  committed
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Commits on Mar 24, 2016

• Added the missing ports for the programmable reset

  d1duarte

  committed
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Commits on Mar 23, 2016

• Properly decode immediate offset value of vector instructions.

  zwabbit

  committed
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• Fix up address calculations for buffered operations.

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  committed
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Commits on Mar 22, 2016

• Deal with multi-word vector instructions.

  zwabbit

  committed
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• Fix typo that was resulting in the wrong register address being used for vector operations in the LSU. Overhaul tracemon to properly deal with vector load operations. Vector stores still pending.

  zwabbit

  committed
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Commits on Mar 21, 2016

• Add 'support' for buffered scalar memory operations. We now pass all scalar memory ops.

  zwabbit

  committed
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• Blocking assignments are evil. Use nonblocking assignment in address incrementing.

  zwabbit

  committed
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• Modify the testbench to start to be able to deal with the new style of memory operations. Minor fixes to the LSU to get it to properly calculate SGPR addresses.

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  committed
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Commits on Mar 17, 2016

• First pass in fixing tracemon to properly monitor memory operations again. Not working yet due to slight mismatch in pipeline sequences tracemon is expecting relative to what the current LSU is doi…

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  zwabbit

  committed
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Commits on Mar 16, 2016

• Remap how data read from memory is put into the register write bus. Since we are reading the lowest word first we have to make sure the lowest word is in the lowest bits of the bus, which is not st…

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  zwabbit

  committed
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Commits on Mar 15, 2016

• Significantly overhaul the LSU. It now responds properly to memory requests and is considerably easier to debug. Unit tests still fail but that is likely more due to the framework's issues than the…

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  zwabbit

  committed
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Commits on Mar 11, 2016

• Properly added support to test branches and conditionals in siagen.

  collielimabean

  committed
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• Merge pull request VerticalResearchGroup#8 from d1duarte/patch-1

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  zwabbit

  committed
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• Added vector reset and mask set register

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  d1duarte

  committed
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Commits on Mar 9, 2016

• Added vector register writes command register

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  d1duarte

  committed
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Commits on Mar 8, 2016

• Create axi_slave_interconnect_external_ports_creation.tcl

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  d1duarte

  committed
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• Added vector register access from microblaze

  d1duarte

  committed
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• Added memory mapped vector register access

  d1duarte

  committed
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• Added vector register interface ports

  d1duarte

  committed
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