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phy.c
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <[email protected]>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <[email protected]>
*
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
#include "../ps.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "rf.h"
#include "dm.h"
#include "table.h"
#include "trx.h"
static u32 _rtl8723be_phy_rf_serial_read(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 offset);
static void _rtl8723be_phy_rf_serial_write(struct ieee80211_hw *hw,
enum radio_path rfpath,
u32 offset, u32 data);
static u32 _rtl8723be_phy_calculate_bit_shift(u32 bitmask);
static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw);
static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
u8 configtype);
static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
u8 configtype);
static void _rtl8723be_phy_init_bb_rf_register_definition(
struct ieee80211_hw *hw);
static bool _rtl8723be_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
u32 cmdtableidx,
u32 cmdtablesz,
enum swchnlcmd_id cmdid,
u32 para1, u32 para2,
u32 msdelay);
static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
u8 channel, u8 *stage,
u8 *step, u32 *delay);
static long _rtl8723be_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
enum wireless_mode wirelessmode,
u8 txpwridx);
static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw);
static void rtl8723be_phy_set_io(struct ieee80211_hw *hw);
u32 rtl8723be_phy_query_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 returnvalue, originalvalue, bitshift;
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask));
originalvalue = rtl_read_dword(rtlpriv, regaddr);
bitshift = _rtl8723be_phy_calculate_bit_shift(bitmask);
returnvalue = (originalvalue & bitmask) >> bitshift;
RT_TRACE(COMP_RF, DBG_TRACE,
("BBR MASK=0x%x Addr[0x%x]=0x%x\n",
bitmask, regaddr, originalvalue));
return returnvalue;
}
void rtl8723be_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
u32 bitmask, u32 data)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 originalvalue, bitshift;
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), bitmask(%#x), data(%#x)\n",
regaddr, bitmask, data));
if (bitmask != MASKDWORD) {
originalvalue = rtl_read_dword(rtlpriv, regaddr);
bitshift = _rtl8723be_phy_calculate_bit_shift(bitmask);
data = ((originalvalue & (~bitmask)) | (data << bitshift));
}
rtl_write_dword(rtlpriv, regaddr, data);
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), bitmask(%#x), data(%#x)\n",
regaddr, bitmask, data));
}
u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
u32 regaddr, u32 bitmask)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 original_value, readback_value, bitshift;
unsigned long flags;
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
regaddr, rfpath, bitmask));
spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
original_value = _rtl8723be_phy_rf_serial_read(hw, rfpath, regaddr);
bitshift = _rtl8723be_phy_calculate_bit_shift(bitmask);
readback_value = (original_value & bitmask) >> bitshift;
spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), rfpath(%#x), "
"bitmask(%#x), original_value(%#x)\n",
regaddr, rfpath, bitmask, original_value));
return readback_value;
}
void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path path,
u32 regaddr, u32 bitmask, u32 data)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 original_value, bitshift;
unsigned long flags;
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
regaddr, bitmask, data, path));
spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
if (bitmask != RFREG_OFFSET_MASK) {
original_value = _rtl8723be_phy_rf_serial_read(hw, path,
regaddr);
bitshift = _rtl8723be_phy_calculate_bit_shift(bitmask);
data = ((original_value & (~bitmask)) |
(data << bitshift));
}
_rtl8723be_phy_rf_serial_write(hw, path, regaddr, data);
spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
RT_TRACE(COMP_RF, DBG_TRACE,
("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
regaddr, bitmask, data, path));
}
static u32 _rtl8723be_phy_rf_serial_read(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 offset)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
u32 newoffset;
u32 tmplong, tmplong2;
u8 rfpi_enable = 0;
u32 retvalue;
offset &= 0xff;
newoffset = offset;
if (RT_CANNOT_IO(hw)) {
RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
return 0xFFFFFFFF;
}
tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
if (rfpath == RF90_PATH_A)
tmplong2 = tmplong;
else
tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
(newoffset << 23) | BLSSIREADEDGE;
rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
tmplong & (~BLSSIREADEDGE));
mdelay(1);
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
mdelay(1);
/*rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
tmplong | BLSSIREADEDGE);*/
mdelay(1);
if (rfpath == RF90_PATH_A)
rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
BIT(8));
else if (rfpath == RF90_PATH_B)
rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
BIT(8));
if (rfpi_enable)
retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
BLSSIREADBACKDATA);
else
retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
BLSSIREADBACKDATA);
RT_TRACE(COMP_RF, DBG_TRACE,
("RFR-%d Addr[0x%x]=0x%x\n",
rfpath, pphyreg->rflssi_readback, retvalue));
return retvalue;
}
static void _rtl8723be_phy_rf_serial_write(struct ieee80211_hw *hw,
enum radio_path rfpath,
u32 offset, u32 data)
{
u32 data_and_addr;
u32 newoffset;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
if (RT_CANNOT_IO(hw)) {
RT_TRACE(COMP_ERR, DBG_EMERG, ("stop\n"));
return;
}
offset &= 0xff;
newoffset = offset;
data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
RT_TRACE(COMP_RF, DBG_TRACE,
("RFW-%d Addr[0x%x]=0x%x\n", rfpath,
pphyreg->rf3wire_offset, data_and_addr));
}
static u32 _rtl8723be_phy_calculate_bit_shift(u32 bitmask)
{
u32 i;
for (i = 0; i <= 31; i++) {
if (((bitmask >> i) & 0x1) == 1)
break;
}
return i;
}
bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
bool rtstatus = _rtl8723be_phy_config_mac_with_headerfile(hw);
rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
return rtstatus;
}
bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw)
{
bool rtstatus = true;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u16 regval;
u8 b_reg_hwparafile = 1;
u32 tmp;
u8 crystalcap = rtlpriv->efuse.crystalcap;
_rtl8723be_phy_init_bb_rf_register_definition(hw);
regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
regval | BIT(13) | BIT(0) | BIT(1));
rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
FEN_BB_GLB_RSTn | FEN_BBRSTB);
tmp = rtl_read_dword(rtlpriv, 0x4c);
rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
if (b_reg_hwparafile == 1)
rtstatus = _rtl8723be_phy_bb8723b_config_parafile(hw);
crystalcap = crystalcap & 0x3F;
rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
(crystalcap | crystalcap << 6));
return rtstatus;
}
bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw)
{
return rtl8723be_phy_rf6052_config(hw);
}
static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
const u32 condition)
{
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u32 _board = rtlefuse->board_type; /*need efuse define*/
u32 _interface = rtlhal->interface;
u32 _platform = 0x08;/*SupportPlatform */
u32 cond = condition;
if (condition == 0xCDCDCDCD)
return true;
cond = condition & 0xFF;
if ((_board & cond) == 0 && cond != 0x1F)
return false;
cond = condition & 0xFF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = condition & 0xFF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
static void _rtl8723be_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
u32 data, enum radio_path rfpath,
u32 regaddr)
{
if (addr == 0xfe || addr == 0xffe) {
/* In order not to disturb BT music
when wifi init.(1ant NIC only) */
/*mdelay(50);*/
/* In order not to disturb BT music
when wifi init.(1ant NIC only) */
mdelay(50);
} else {
rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
udelay(1);
}
}
static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw,
u32 addr, u32 data)
{
u32 content = 0x1000; /*RF Content: radio_a_txt*/
u32 maskforphyset = (u32)(content & 0xE000);
_rtl8723be_config_rf_reg(hw, addr, data, RF90_PATH_A,
addr | maskforphyset);
}
static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 band, path, txnum, section;
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
for (path = 0; path < TX_PWR_BY_RATE_NUM_RF; ++path)
for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
for (section = 0;
section < TX_PWR_BY_RATE_NUM_SECTION;
++section)
rtlphy->tx_power_by_rate_offset[band][path][txnum][section] = 0;
}
static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
u32 addr, u32 data)
{
if (addr == 0xfe) {
mdelay(50);
} else if (addr == 0xfd) {
mdelay(5);
} else if (addr == 0xfc) {
mdelay(1);
} else if (addr == 0xfb) {
udelay(50);
} else if (addr == 0xfa) {
udelay(5);
} else if (addr == 0xf9) {
udelay(1);
} else {
rtl_set_bbreg(hw, addr, MASKDWORD, data);
udelay(1);
}
}
void _rtl8723be_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, u8 band,
u8 path, u8 rate_section,
u8 txnum, u8 value)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (path > RF90_PATH_D) {
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n",
path));
return;
}
if (band == BAND_ON_2_4G) {
switch (rate_section) {
case CCK:
rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
break;
case OFDM:
rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
break;
case HT_MCS0_MCS7:
rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
break;
case HT_MCS8_MCS15:
rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
break;
default:
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid RateSection %d in Band 2.4G, Rf Path"
" %d, %dTx in PHY_SetTxPowerByRateBase()\n",
rate_section, path, txnum));
break;
};
} else {
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid Band %d in PHY_SetTxPowerByRateBase()\n",
band));
}
}
u8 _rtl8723be_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, u8 band,
u8 path, u8 txnum, u8 rate_section)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 value = 0;
if (path > RF90_PATH_D) {
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
path));
return 0;
}
if (band == BAND_ON_2_4G) {
switch (rate_section) {
case CCK:
value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
break;
case OFDM:
value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
break;
case HT_MCS0_MCS7:
value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
break;
case HT_MCS8_MCS15:
value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
break;
default:
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid RateSection %d in Band 2.4G, Rf Path"
" %d, %dTx in PHY_GetTxPowerByRateBase()\n",
rate_section, path, txnum));
break;
};
} else {
RT_TRACE(COMP_INIT, DBG_LOUD,
("Invalid Band %d in PHY_GetTxPowerByRateBase()\n",
band));
}
return value;
}
void _rtl8723be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u16 rawValue = 0;
u8 base = 0, path = 0;
for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
if (path == RF90_PATH_A) {
rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF;
base = (rawValue >> 4) * 10 + (rawValue & 0xF);
_rtl8723be_phy_set_txpower_by_rate_base(hw,
BAND_ON_2_4G, path, CCK, RF_1TX, base);
} else if (path == RF90_PATH_B) {
rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF;
base = (rawValue >> 4) * 10 + (rawValue & 0xF);
_rtl8723be_phy_set_txpower_by_rate_base(hw,
BAND_ON_2_4G,
path, CCK,
RF_1TX, base);
}
rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
base = (rawValue >> 4) * 10 + (rawValue & 0xF);
_rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
path, OFDM, RF_1TX,
base);
rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
base = (rawValue >> 4) * 10 + (rawValue & 0xF);
_rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
path, HT_MCS0_MCS7,
RF_1TX, base);
rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
base = (rawValue >> 4) * 10 + (rawValue & 0xF);
_rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
path, HT_MCS8_MCS15,
RF_2TX, base);
}
}
void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
u8 end, u8 base_val)
{
char i = 0;
u8 temp_value = 0;
u32 temp_data = 0;
for (i = 3; i >= 0; --i) {
if (i >= start && i <= end) {
/* Get the exact value */
temp_value = (u8) (*data >> (i * 8)) & 0xF;
temp_value += ((u8) ((*data >> (i*8 + 4)) & 0xF)) * 10;
/* Change the value to a relative value */
temp_value = (temp_value > base_val) ?
temp_value - base_val :
base_val - temp_value;
} else {
temp_value = (u8) (*data >> (i * 8)) & 0xFF;
}
temp_data <<= 8;
temp_data |= temp_value;
}
*data = temp_data;
}
void _rtl8723be_phy_convert_txpower_dbm_to_relative_value(
struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 base = 0, rfPath = RF90_PATH_A;
base = _rtl8723be_phy_get_txpower_by_rate_base(hw,
BAND_ON_2_4G, rfPath, RF_1TX, CCK);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][2]),
1, 1, base);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][3]),
1, 3, base);
base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath,
RF_1TX, OFDM);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][0]),
0, 3, base);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][1]),
0, 3, base);
base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
rfPath, RF_1TX, HT_MCS0_MCS7);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][4]),
0, 3, base);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][5]),
0, 3, base);
base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
rfPath, RF_2TX, HT_MCS8_MCS15);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][6]),
0, 3, base);
_phy_convert_txpower_dbm_to_relative_value(
&(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][7]),
0, 3, base);
RT_TRACE(COMP_POWER, DBG_TRACE,
("<===_rtl8723be_phy_convert_txpower_dbm_to_relative_value()\n"));
}
static void _rtl8723be_phy_txpower_by_rate_configuration(
struct ieee80211_hw *hw)
{
_rtl8723be_phy_store_txpower_by_rate_base(hw);
_rtl8723be_phy_convert_txpower_dbm_to_relative_value(hw);
}
static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
bool rtstatus;
rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw,
BASEBAND_CONFIG_PHY_REG);
if (rtstatus != true) {
RT_TRACE(COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
return false;
}
_rtl8723be_phy_init_tx_power_by_rate(hw);
if (rtlefuse->autoload_failflag == false) {
rtlphy->pwrgroup_cnt = 0;
rtstatus = _rtl8723be_phy_config_bb_with_pgheaderfile(hw,
BASEBAND_CONFIG_PHY_REG);
}
_rtl8723be_phy_txpower_by_rate_configuration(hw);
if (rtstatus != true) {
RT_TRACE(COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
return false;
}
rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw,
BASEBAND_CONFIG_AGC_TAB);
if (rtstatus != true) {
RT_TRACE(COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
return false;
}
rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
RFPGA0_XA_HSSIPARAMETER2,
0x200));
return true;
}
static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 i;
u32 arraylength;
u32 *ptrarray;
RT_TRACE(COMP_INIT, DBG_TRACE, ("Read rtl8723beMACPHY_Array\n"));
arraylength = RTL8723BEMAC_1T_ARRAYLEN;
ptrarray = RTL8723BEMAC_1T_ARRAY;
RT_TRACE(COMP_INIT, DBG_LOUD,
("Img:RTL8723bEMAC_1T_ARRAY LEN %d\n", arraylength));
for (i = 0; i < arraylength; i = i + 2)
rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
return true;
}
static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
u8 configtype)
{
#define READ_NEXT_PAIR(v1, v2, i) \
do { \
i += 2; \
v1 = array_table[i];\
v2 = array_table[i+1]; \
} while (0)
int i;
u32 *array_table;
u16 arraylen;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 v1 = 0, v2 = 0;
if (configtype == BASEBAND_CONFIG_PHY_REG) {
arraylen = RTL8723BEPHY_REG_1TARRAYLEN;
array_table = RTL8723BEPHY_REG_1TARRAY;
for (i = 0; i < arraylen; i = i + 2) {
v1 = array_table[i];
v2 = array_table[i+1];
if (v1 < 0xcdcdcdcd) {
_rtl8723be_config_bb_reg(hw, v1, v2);
} else {/*This line is the start line of branch.*/
/* to protect READ_NEXT_PAIR not overrun */
if (i >= arraylen - 2)
break;
if (!_rtl8723be_check_condition(hw,
array_table[i])) {
/*Discard the following
(offset, data) pairs*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < arraylen - 2) {
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2*/
/*Configure matched pairs and
*skip to end of if-else.*/
} else {
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < arraylen - 2) {
_rtl8723be_config_bb_reg(hw,
v1, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
arraylen = RTL8723BEAGCTAB_1TARRAYLEN;
array_table = RTL8723BEAGCTAB_1TARRAY;
for (i = 0; i < arraylen; i = i + 2) {
v1 = array_table[i];
v2 = array_table[i+1];
if (v1 < 0xCDCDCDCD) {
rtl_set_bbreg(hw, array_table[i],
MASKDWORD,
array_table[i + 1]);
udelay(1);
continue;
} else {/*This line is the start line of branch.*/
/* to protect READ_NEXT_PAIR not overrun */
if (i >= arraylen - 2)
break;
if (!_rtl8723be_check_condition(hw,
array_table[i])) {
/*Discard the following
*(offset, data) pairs*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < arraylen - 2) {
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2*/
/*Configure matched pairs and
*skip to end of if-else.*/
} else {
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < arraylen - 2) {
rtl_set_bbreg(hw, array_table[i],
MASKDWORD,
array_table[i + 1]);
udelay(1);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
RT_TRACE(COMP_INIT, DBG_TRACE,
("The agctab_array_table[0] is "
"%x Rtl818EEPHY_REGArray[1] is %x\n",
array_table[i], array_table[i + 1]));
}
}
return true;
}
static u8 _rtl8723be_get_rate_section_index(u32 regaddr)
{
u8 index = 0;
switch (regaddr) {
case RTXAGC_A_RATE18_06:
index = 0;
break;
case RTXAGC_A_RATE54_24:
index = 1;
break;
case RTXAGC_A_CCK1_MCS32:
index = 2;
break;
case RTXAGC_B_CCK11_A_CCK2_11:
index = 3;
break;
case RTXAGC_A_MCS03_MCS00:
index = 4;
break;
case RTXAGC_A_MCS07_MCS04:
index = 5;
break;
case RTXAGC_A_MCS11_MCS08:
index = 6;
break;
case RTXAGC_A_MCS15_MCS12:
index = 7;
break;
case RTXAGC_B_RATE18_06:
index = 0;
break;
case RTXAGC_B_RATE54_24:
index = 1;
break;
case RTXAGC_B_CCK1_55_MCS32:
index = 2;
break;
case RTXAGC_B_MCS03_MCS00:
index = 4;
break;
case RTXAGC_B_MCS07_MCS04:
index = 5;
break;
case RTXAGC_B_MCS11_MCS08:
index = 6;
break;
case RTXAGC_B_MCS15_MCS12:
index = 7;
break;
default:
regaddr &= 0xFFF;
if (regaddr >= 0xC20 && regaddr <= 0xC4C)
index = (u8) ((regaddr - 0xC20) / 4);
else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
index = (u8) ((regaddr - 0xE20) / 4);
break;
};
return index;
}
static void _rtl8723be_store_tx_power_by_rate(struct ieee80211_hw *hw,
u32 band, u32 rfpath,
u32 txnum, u32 regaddr,
u32 bitmask, u32 data)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 rate_section = _rtl8723be_get_rate_section_index(regaddr);
if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
RT_TRACE(FPHY, PHY_TXPWR, ("Invalid Band %d\n", band));
return;
}
if (rfpath > MAX_RF_PATH - 1) {
RT_TRACE(FPHY, PHY_TXPWR, ("Invalid RfPath %d\n", rfpath));
return;
}
if (txnum > MAX_RF_PATH - 1) {
RT_TRACE(FPHY, PHY_TXPWR, ("Invalid TxNum %d\n", txnum));
return;
}
rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] =
data;
}
static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
u8 configtype)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i;
u32 *phy_regarray_table_pg;
u16 phy_regarray_pg_len;
u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
phy_regarray_pg_len = RTL8723BEPHY_REG_ARRAY_PGLEN;
phy_regarray_table_pg = RTL8723BEPHY_REG_ARRAY_PG;
if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
v1 = phy_regarray_table_pg[i];
v2 = phy_regarray_table_pg[i+1];
v3 = phy_regarray_table_pg[i+2];
v4 = phy_regarray_table_pg[i+3];
v5 = phy_regarray_table_pg[i+4];
v6 = phy_regarray_table_pg[i+5];
if (v1 < 0xcdcdcdcd) {
if (phy_regarray_table_pg[i] == 0xfe ||
phy_regarray_table_pg[i] == 0xffe)
mdelay(50);
else
_rtl8723be_store_tx_power_by_rate(hw,
v1, v2, v3, v4, v5, v6);
continue;
}
}
} else {
RT_TRACE(COMP_SEND, DBG_TRACE,
("configtype != BaseBand_Config_PHY_REG\n"));
}
return true;
}
bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath)
{
#define READ_NEXT_RF_PAIR(v1, v2, i) \
do { \
i += 2; \
v1 = radioa_array_table[i]; \
v2 = radioa_array_table[i+1]; \
} while (0)
int i;
bool rtstatus = true;
u32 *radioa_array_table;
u16 radioa_arraylen;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u32 v1 = 0, v2 = 0;
radioa_arraylen = RTL8723BE_RADIOA_1TARRAYLEN;
radioa_array_table = RTL8723BE_RADIOA_1TARRAY;
RT_TRACE(COMP_INIT, DBG_LOUD,
("Radio_A:RTL8723BE_RADIOA_1TARRAY %d\n", radioa_arraylen));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
rtstatus = true;
switch (rfpath) {
case RF90_PATH_A:
for (i = 0; i < radioa_arraylen; i = i + 2) {
v1 = radioa_array_table[i];
v2 = radioa_array_table[i+1];
if (v1 < 0xcdcdcdcd) {
_rtl8723be_config_rf_radio_a(hw, v1, v2);
} else {/*This line is the start line of branch.*/
/* to protect READ_NEXT_PAIR not overrun */
if (i >= radioa_arraylen - 2)
break;
if (!_rtl8723be_check_condition(hw,
radioa_array_table[i])) {
/*Discard the following
*(offset, data) pairs*/
READ_NEXT_RF_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < radioa_arraylen - 2) {
READ_NEXT_RF_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2*/
} else {
/*Configure matched pairs
*and skip to end of if-else.*/
READ_NEXT_RF_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD &&
i < radioa_arraylen - 2) {
_rtl8723be_config_rf_radio_a(hw,
v1, v2);
READ_NEXT_RF_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD &&
i < radioa_arraylen - 2) {
READ_NEXT_RF_PAIR(v1, v2, i);
}
}
}
}
if (rtlhal->oem_id == RT_CID_819x_HP)
_rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD);
break;
case RF90_PATH_B:
RT_TRACE(COMP_ERR, DBG_EMERG,
("switch case not process\n"));
break;
case RF90_PATH_C:
RT_TRACE(COMP_ERR, DBG_EMERG,
("switch case not process\n"));
break;
case RF90_PATH_D:
RT_TRACE(COMP_ERR, DBG_EMERG,
("switch case not process\n"));
break;
}
return true;
}
void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);