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Commits on Feb 15, 2022

• Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH

  alexforencich

  committed
  c62df81

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• Update default SEG_ADDR_WIDTH parameter value for DMA RAM

  alexforencich

  committed
  a65b256

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Commits on Feb 2, 2022

• Implement USE_AXI_ID for dma_if_axi_rd

  alexforencich

  committed
  c473324

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• Refactor to use existing variable

  alexforencich

  committed
  27f9093

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• Add missing resets

  alexforencich

  committed
  a0a7732

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Commits on Feb 1, 2022

• Implement USE_AXI_ID for dma_if_axi_wr

  alexforencich

  committed
  2f6ad1e

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• Update parameters

  alexforencich

  committed
  d9c4b17

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Commits on Jan 18, 2022

• Fix bug in example design core logic

  alexforencich

  committed
  74e4322

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Commits on Dec 28, 2021

• Lock package versions

  alexforencich

  committed
  625f3c9

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• Specify min tox and venv versions

  alexforencich

  committed
  7ab512b

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Commits on Dec 27, 2021

• Use available python 3

  alexforencich

  committed
  4ce150e

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Commits on Dec 16, 2021

• Fix alignment

  alexforencich

  committed
  25f6dcb

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• Fix reg to wire declaration

  Show description for 01b9732
  

  andreasbraun90

  authored and

  alexforencich

  committed
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Commits on Dec 11, 2021

• Use start_soon instead of fork

  alexforencich

  committed
  bac4e40

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Commits on Dec 10, 2021

• Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0

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  Basseuph

  committed
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Commits on Dec 3, 2021

• Indexing updates

  alexforencich

  committed
  17d7353

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• Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0

  alexforencich

  committed
  3a12483

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Commits on Nov 19, 2021

• Update readme

  alexforencich

  committed
  a2e2919

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• Add example design for ZCU106

  alexforencich

  committed
  d1210d0

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• Add example design for VCU1525

  alexforencich

  committed
  0830ca6

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• Add example design for VCU118

  alexforencich

  committed
  fb4b32f

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• Add example design for VCU108

  alexforencich

  committed
  cef69d1

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• Add example design for ExaNIC X25

  alexforencich

  committed
  6740dda

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• Add example design for Alveo U50

  alexforencich

  committed
  0cbe489

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• Add example design for Alveo U280

  alexforencich

  committed
  068ea6e

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• Add example design for Alveo U250

  alexforencich

  committed
  12fea95

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• Add example design for Alveo U200

  alexforencich

  committed
  6e5f9f3

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• Add example design for ADM-PCIE-9V3

  alexforencich

  committed
  057edeb

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Commits on Nov 18, 2021

• Parameter cleanup

  alexforencich

  committed
  9632a40

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• Testbench cleanup

  alexforencich

  committed
  667076e

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• Testbench cleanup

  alexforencich

  committed
  a330c6e

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• Fix instance name

  alexforencich

  committed
  419ee05

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• Update example design testbenches

  alexforencich

  committed
  6920845

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• Update testbenches

  alexforencich

  committed
  2c3a5f4

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• Fix makefile

  alexforencich

  committed
  63e7df0

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