Skip to content

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

License

Notifications You must be signed in to change notification settings

mvg-internship/OpenLane

 
 

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

1. How to process a bench file from the ABCD set for its being compatible with OpenLane?

If abc is accessible via sh, try the following commands (an example is given for aes_orig.bench):

abc
abc 01> read aes_orig.bench
abc 02> strash
abc 03> write_aiger aes_orig.aig
  1. How to prepare a design for running OpenLane?

First, copy the existing design folder:

  • use techmappedNet as a donor, if one needs to process the Verilog file resulted of Utopia techmappers;
  • use aes_comb as a donor, if one needs to process benches from ABCD set.

Second, update the config.json file in the newly copied folder accordingly. Take into account the following params:

  • DESIGN_NAME (top level name);
  • VERILOG_FILES (if necessary, write down Verilog files here);
  • AIGER_FILES (if necessary, write down aig files here);
  • NO_LINTER (if AIGER_FILES is used NO_LINTER should be activated);
  • DIE_AREA and FP_SIZING (should be updated if the design is much bigger than 30K logic elements).
  1. How to run OpenLane on the selected design?

It can be done by means of Docker image (aes_comb here is the folder name):

sudo make
sudo make mount
./flow.sh -design aes_comb

OpenLane

Open in Colab License: Apache 2.0 GitHub Actions Status Badge Documentation Build Status Badge Invite to the Open Source Silicon Slack Python Code Style: black

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII.

You can check out the documentation, including in-depth guides and reference manuals at ReadTheDocs.

Banner promoting OpenLane 2

Quick-start Guide

If you just want to try OpenLane out, try this Colaboratory by our friends at Google and ChipsAlliance. It's an online Python-based utility, and the best part is, you don't need to install anything.

Installation, the short version

The short version is, to install the OpenLane environment...

On Windows, install and launch the Windows Subsystem for Linux before doing anything. We recommend and provide instructions for Ubuntu 20.04.

On macOS, get brew.

  1. Get Docker (or a compatible container engine)
  2. Get Python 3.6 or higher (macOS | Ubuntu)
    • On Ubuntu, you may also need to install venv: apt-get install python3-venv
  3. Get git (macOS | Ubuntu)
  4. Get GNU Make (macOS | Ubuntu)

Run the following commands in your command-line prompt:

cd $HOME
git clone https://github.com/The-OpenROAD-Project/OpenLane
cd OpenLane
make
make test

If everything's gone smoothly, that's it. OpenLane is set up on your computer. To enter the OpenLane environment, cd $HOME/OpenLane and then make mount.

Installation, the long version

See the installation docs at https://openlane.readthedocs.io/en/latest/getting_started/installation/index.html.

Usage

After entering the OpenLane environment, you can start hardening chips: the following command, for example, runs the included spm design.

./flow.tcl -design spm

Need more help?

You can join the Open Source Silicon Slack, where you can ask thousands of other open source hardware enthusiasts for help with setting up or running OpenLane.

Publication

If you use OpenLane in your research, please cite the following paper.

  • M. Shalan and T. Edwards, “Building OpenLANE: A 130nm OpenROAD-based Tapeout-Proven Flow: Invited Paper,” 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6. Paper
@INPROCEEDINGS{9256623,
  author={Shalan, Mohamed and Edwards, Tim},
  booktitle={2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, 
  title={Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper}, 
  year={2020},
  volume={},
  number={},
  pages={1-6},
  doi={}}

License

The Apache License, version 2.0.

Docker images distributed by Efabless Corporation under the same license.

Binaries in OpenLane distributions may fall under stricter open source licenses.

About

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages

  • Python 56.5%
  • Tcl 36.4%
  • Verilog 2.6%
  • Dockerfile 1.9%
  • Makefile 1.2%
  • JavaScript 0.4%
  • Other 1.0%