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Commits on Mar 2, 2021

• ifu: remove if1_can_go

  Lingrui98

  committed
  79e9a2e

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• ifu: opt timing of redirect ghist

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  Lingrui98

  committed
  6273bc4

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• Merge branch 'opt-dcache-timing' into dev-dcache-rearrange

  linjuanZ

  committed
  5ca23d3

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• MissQueue: replace roundRobin Arb with lowestIndexFirst for timing opt

  linjuanZ

  committed
  eb606df

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• Merge branch 'master' into dev-dcache-lru

  linjuanZ

  committed
  4a41643

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• DCache: add pseudo LRU replacement policy for dcache

  linjuanZ

  committed
  411c28b

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• Optimize ctrlblock timing (OpenXiangShan#620)

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  ljwljwljwljw

  and

  poemonsense

  authored
  c1b37c8

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• ftq: only when corresponding write back port is valid can cfiIndex_vec be updated (OpenXiangShan#621)

  Lingrui98

  authored
  ec1d4bb

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Commits on Mar 1, 2021

• DataArray: change sram bank width to 144

  linjuanZ

  committed
  1fad9af

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• LoadUnit: set TLB hit when the load has an exception (OpenXiangShan#619)

  poemonsense

  authored
  3f65d79

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• Merge pull request OpenXiangShan#615 from RISCVERS/l1plus-sram-cut

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  ljwljwljwljw

  authored
  03b7157

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• MainPipe: remove bubble by setting read priority higher than write in MainPipe

  linjuanZ

  committed
  2ef0ec6

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• Sbuffer: remove old version sbuffer (OpenXiangShan#617)

  ljwljwljwljw

  authored
  e46a148

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• Merge pull request OpenXiangShan#614 from RISCVERS/ubtb-alloc-on-write

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  jinyue110

  authored
  8a538cf

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• optimize L1 DCache timing (OpenXiangShan#616)

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  njuallen

  authored
  27d2b88

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• Merge branch 'master' into dev-dcache-rearrange

  linjuanZ

  committed
  0310013

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• Merge pull request OpenXiangShan#608 from RISCVERS/bpu-perf

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  Lingrui98

  authored
  76988cb

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Commits on Feb 28, 2021

• TLB: add more tlb and ptw's performance counters (OpenXiangShan#610)

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  Lemover

  authored
  127956c

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• DCacheWrapper: set read priority of ldu higher than that of mainPipe

  linjuanZ

  committed
  e04fa4a

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• ram: don't set aw.valid or w.valid when dram cannot accept the request (OpenXiangShan#613)

  poemonsense

  authored
  4b3ee0b

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• Merge branch 'master' into bpu-perf

  zoujr

  authored
  0ba0847

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• Merge branch 'master' into l1plus-sram-cut

  jinyue110

  committed
  94bf6b8

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• L1plusCache: separate ECC code from Data SRAM

  jinyue110

  committed
  ac58405

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• Merge remote-tracking branch 'origin/master' into ubtb-alloc-on-write

  Lingrui98

  committed
  51b6fda

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• Ftq: bypass 'commit state' to fix dequeue bug (OpenXiangShan#612)

  ljwljwljwljw

  authored
  39ae280

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• MetaArray: write ready should be set when both arrays are ready

  linjuanZ

  committed
  6c071a1

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• wb: fix wb.valid when neither rfwen nor fpwen is set (OpenXiangShan#611)

  poemonsense

  authored
  f08008b

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• Ftq: use regfile instead of 4r_sram (OpenXiangShan#609)

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  ljwljwljwljw

  authored
  dfde261

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• Merge remote-tracking branch 'origin/master' into ubtb-alloc-on-write

  Lingrui98

  committed
  1647000

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• ubtb: fix a connect bug

  Lingrui98

  committed
  d5edd25

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• ubtb: alloc ways on write

  Lingrui98

  committed
  72da94f

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• L1plusCache: cut 576 width SRAM into two 288

  jinyue110

  committed
  0c99ac5

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• MainPipe: fix bug in incorrect assert

  linjuanZ

  committed
  db39e90

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• perf: Remove unused code

  zoujr

  committed
  bbd2263

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• perf: Fix compile error

  zoujr

  committed
  47c2acc

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