运动陪练系统开发（科创）

Fly through your shell history. Great Scott!

Run sing-box/mihomo as client in shell

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Ultimate auto-completion system for Vim.

Syntax highlighting for generic log files in VIM

A vim-perforce integration plugin

UVM and System Verilog Manuals

搜集、整理、维护 Surge / Quantumult (X) / Shadowrocket / Surfboard / clash (Premium) 实用规则。

小巧精悍、准确、实用 GeoIP2 数据库

SystemRDL 2.0 language compiler front-end

VeeR EH1 core

SystemVerilog、Verilog、UVM

👌 Support for --remote and friends.

The C-based Firmware Patching Framework for Broadcom/Cypress WiFi Chips that enables Monitor Mode, Frame Injection and much more

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Hardware Viterbi Decoder in verilog

Open-source high-performance RISC-V processor

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

HDL libraries and projects

lists of most popular repositories for most favoured programming languages (according to StackOverflow)

Shadowsocks/SS一键脚本、ShadowsocksR/SSR一键脚本、V2Ray一键脚本、trojan一键脚本、VPS教程

This is Max's blog, something interesting in it.

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Notebooks for "Python for Signal Processing" book

The Ultra-Low Power RISC-V Core