VeeR EH1 core

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

AMBA AHB 2.0 VIP in SystemVerilog UVM

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

system verilog course labs

Computer Design and Prototyping

A repository for course ECE337: ASIC Design Laboratory(Spring2016).