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Commits on Sep 1, 2022

• cva6.yml: Add timeout to 1h30 for FPGA build job

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• Update to synthesis and simulation gate flow (#947)

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Commits on Aug 31, 2022

• .gitlab-ci/cva6.yml: Update synthesis and smoke-gate jobs

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• [CI]: cva6.yml: fix on wb_dcache

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Commits on Aug 16, 2022

• cvxif_fu.sv: add register to hold illegal instruction information (#939)

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• decoder: add missing default case for BITMANIP (#938)

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Commits on Aug 5, 2022

• Update vcs-gate iss

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Commits on Aug 4, 2022

• cva6.yaml: add timeout to benchmarks + fix in wb_dcache job

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Commits on Jul 21, 2022

• .gitlab-ci/cva6.yml: add always for fpga boot artifact

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Commits on Jul 20, 2022

• decoder.sv: fix sfence.vma when rs1 != 0 (#933)

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• [HOTFIX] verilator_log_to_trace_csv.py: put continue in else statement

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Commits on Jul 19, 2022

• verilator_log_to_trace_csv.py: set end_trampoline back to 80000000. Still process 1st instruction

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Commits on Jun 30, 2022

• Enable CVXIF for target cv32a60X and add renaming for cvxif when using 3 operands (#925)

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Commits on Jun 29, 2022

• cva6.yml: remove linux job in simulation

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• Add 64b Linux boot and 32b FPGA build. Add report scripts for dashboard

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Commits on Jun 28, 2022

• Makefile: fix VERDI option

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• FPGA: Add scripts to boot linux fpga (#924)

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Commits on Jun 24, 2022

• cva6.py: save cva6/sim path to go back to it after generating config

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Commits on May 30, 2022

• Fix tc_srams paths (#892)

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Commits on May 12, 2022

• CI Generated configuration

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• cva6.sv: change RVFI exception signal (#873)

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Commits on May 11, 2022

• cva6.yml, benchmark.sh: add benchmark job from riscv-tests and wb job

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Commits on Apr 29, 2022

• wt_dcache_wbuffer.sv: remove init for user (#870)

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Commits on Apr 22, 2022

• Add script to generate custom configuration (#862)

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Commits on Apr 21, 2022

• ariane_pkg.sv: Fix LOG2_INSTR_PER_FETCH when RVC is disable (#860)

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Commits on Mar 10, 2022

• Typo + veri-testharness as default simulator

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Commits on Feb 17, 2022

• cva6_synth.tcl: add missing hierarchy for I/O memory delays and timing reports (#826)

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Commits on Feb 16, 2022

• Makefile: Add register_interface/include directory to vcs compile option (#825)

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Commits on Feb 8, 2022

• Add axi-master-connect to tb_components because it no longer exist in cva6 repo

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Commits on Jan 25, 2022

• Rename Mem_init.txt to expected name for vcs_core and vcs_gate target

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Commits on Jan 19, 2022

• Add custom_test_template test with custom BSP to smoke-tests

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• rename spike_log_to_trace_csv file to independant from riscv-dv

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• Update riscv-dv and spike hash

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• Fix spike regex and move it to sim repositories

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• Update flists to match commit#791 (#795)

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