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Commits on Feb 19, 2025

• Add parameter type to define which coprocessor is instantiated on CVXIF (#2772)

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  Gchauvon

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  JeanRochCoulon

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Commits on Feb 3, 2025

• Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756)

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  Gchauvon

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Commits on Jan 23, 2025

• Spyglass clean up: multiple change to remove Spyglass warnings (#2727)

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  Gchauvon

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  JeanRochCoulon

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  3ce44b1

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Commits on Jan 22, 2025

• Fix decoding of CLRI, BINVI, BSETI, BEXTI and RORI where bit 25 is reserved in RV32 (#2728)

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  Gchauvon

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Commits on Jan 21, 2025

• Docs: define values for CVXIF in 60x and 65x configuration (#2721)

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  Gchauvon

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  JeanRochCoulon

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  24c6a89

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• csr_regfile: SEIP is read only 0 (fix #2056) (#2716)

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  Gchauvon

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  JeanRochCoulon

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  98604b5

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Commits on Jan 17, 2025

• Modify MSUB, NMADD, NMSUB behaviour to differs from other instructions. (#2712)

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Commits on Jan 16, 2025

• Add parameter to disable software interrupt. Fix issue #2500 (#2711)

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  Gchauvon

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Commits on Jan 15, 2025

• CI: copy seeds in artifacts for generated tests (#2708)

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Commits on Dec 20, 2024

• Various fixes for CVXIF following verification. (#2678)

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Commits on Nov 27, 2024

• Fix gate simulation: Update hpdcache_sram black box (#2632)

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Commits on Nov 7, 2024

• Dev/hpdcache fpga (#2586)

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Commits on Oct 9, 2024

• [HOTFIX] Fix Handling of CVXIF instruction being interrupted (#2537)

  Gchauvon

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Commits on Aug 13, 2024

• Add ariane_peripherals and testharness to fpga_filter (#2445)

  Gchauvon

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Commits on Aug 1, 2024

• Fixes and Update CVXIF non regression tests, regression and TB (#2424)

  Gchauvon

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Commits on Jul 26, 2024

• Separate RAW and WAW process to fix CVXIF with Superscalar (#2395)

  Gchauvon

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Commits on Jul 12, 2024

• CVXIF 1.0.0 (#2340)

  Gchauvon

  authored
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Commits on Jul 5, 2024

• Fix benchmark.sh with correct GCC options and order (#2313)

  Gchauvon

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Commits on Jun 28, 2024

• Fix typo on Bitmanip comment (#2300)

  Gchauvon

  authored
  ced13a5

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Commits on Jun 4, 2024

• Add support for cv32a65x dedicated synthesis (#2178)

  Gchauvon

  authored
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Commits on Apr 26, 2024

• Fix DV_OPTS by adding UVM_VERBOSITY flag (#2080)

  Gchauvon

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• Add support for waveform in vcs-testharness (#2079)

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Commits on Mar 29, 2024

• Add debug_disable=1 to match default configuration of cva6.py (#1977)

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Commits on Jan 25, 2024

• Parameterize TVAL to reduce size in embedded (#1784)

  Gchauvon

  authored
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• Check that User mode is enable to set MPP to U-mode (fix #1756) (#1781)

  Gchauvon

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  13a4a09

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Commits on Jan 24, 2024

• Fix path for vcs init_testharness.do (#1780)

  Gchauvon

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Commits on Jan 11, 2024

• Check that loaded elf segment does not overlap on last loaded address (#1755)

  Gchauvon

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Commits on Dec 11, 2023

• Set StallRandom I/O to 0 to gain performance on vcs-testharness bench (#1695)

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Commits on Aug 9, 2023

• Add CVXIF chapter in user's guide (#1289)

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Commits on Jul 17, 2023

• [HOTFIX CI] Make all jobs requiring Spike dependents on build_tools job

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  Gchauvon

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  JeanRochCoulon

  committed
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Commits on Jul 6, 2023

• [HOTFIX CI] Make all jobs requiring Spike dependents on build_tools job

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Commits on Jun 29, 2023

• Fix Spike artifacts

  Gchauvon

  committed
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Commits on Dec 15, 2022

• Change VCS option "Implicit wire no fanin" from WARNING to ERROR (#1020)

  Gchauvon

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Commits on Nov 8, 2022

• cva6.py: change isa for cv32a60x target to support custom BSP

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  Gchauvon

  committed
  3704812

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Commits on Nov 2, 2022

• Flist.cv32a60x: add example coprocessor to Flist (#986)

  Gchauvon

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  ec61b89

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