forked from stevehoover/LF-Building-a-RISC-V-CPU-Core
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathrisc-v-06-alu.tlv
132 lines (107 loc) · 5.01 KB
/
risc-v-06-alu.tlv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
\m4_TLV_version 1d: tl-x.org
\SV
// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/1d1023ccf8e7b0a8cf8e8fc4f0a823ebb61008e3/risc-v_defs.tlv'])
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
//---------------------------------------------------------------------------------
// /====================\
// | Sum 1 to 9 Program |
// \====================/
//
// Program to test RV32I
// Add 1,2,3,...,9 (in that order).
//
// Regs:
// x12 (a2): 10
// x13 (a3): 1..10
// x14 (a4): Sum
//
m4_asm(ADDI, x14, x0, 0) // Initialize sum register a4 with 0
m4_asm(ADDI, x12, x0, 1010) // Store count of 10 in register a2.
m4_asm(ADDI, x13, x0, 1) // Initialize loop count register a3 with 0
// Loop:
m4_asm(ADD, x14, x13, x14) // Incremental summation
m4_asm(ADDI, x13, x13, 1) // Increment loop count by 1
m4_asm(BLT, x13, x12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
// Test result value in x14, and set x31 to reflect pass/fail.
m4_asm(ADDI, x30, x14, 111111010100) // Subtract expected value of 44 to set x30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
m4_asm(BGE, x0, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
m4_asm_end()
m4_define(['M4_MAX_CYC'], 50)
//---------------------------------------------------------------------------------
\SV
m4_makerchip_module // (Expanded in Nav-TLV pane.)
/* verilator lint_on WIDTH */
\TLV
$reset = *reset;
$pc[31:0] = >>1$next_pc;
$next_pc[31:0] = $reset ? 0 : $pc + 4;
`READONLY_MEM($pc, $$instr[31:0]);
// Decode instruction type.
$is_u_instr = $instr[6:2] ==? 5'b0x101;
// This is equivalent to $intr[6:2] == 5'b00101 || $instr[6:2] == 5'b01101;
$is_i_instr = $instr[6:2] ==? 5'b0000x ||
$instr[6:2] ==? 5'b001x0 ||
$instr[6:2] ==? 5'b11001;
$is_r_instr = $instr[6:2] ==? 5'b01011 ||
$instr[6:2] ==? 5'b011x0 ||
$instr[6:2] ==? 5'b10100;
$is_s_instr = $instr[6:2] ==? 5'b0100x;
$is_b_instr = $instr[6:2] ==? 5'b11000;
$is_j_instr = $instr[6:2] ==? 5'b11011;
// Extract fields.
$funct7[6:0] = $instr[31:25];
$funct3[2:0] = $instr[14:12];
$rs1[4:0] = $instr[19:15]; // Source 1 register
$rs2[4:0] = $instr[24:20]; // Source 2 register
$rd[4:0] = $instr[11:7]; // Destination register
$opcode[6:0] = $instr[6:0];
$imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
$is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } :
$is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } :
$is_u_instr ? { $instr[31:12], 12'b0 } :
$is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0}:
32'b0 ;
// Signal whether the field is in use.
$funct7_valid = $is_r_instr;
$funct3_valid = $is_r_instr ||
$is_s_instr ||
$is_b_instr ||
$is_i_instr;
$rs1_valid = $is_r_instr ||
$is_s_instr ||
$is_b_instr ||
$is_i_instr;
$rs2_valid = $is_r_instr ||
$is_s_instr ||
$is_b_instr;
$rd_valid = $is_r_instr ||
$is_u_instr ||
$is_j_instr ||
$is_i_instr;
$imm_valid = ~$is_r_instr;
// Decode instructions
$dec_bits[10:0] = {$instr[30],$funct3,$opcode};
$is_beq = $dec_bits ==? 11'bx_000_1100011;
$is_bne = $dec_bits ==? 11'bx_001_1100011;
$is_blt = $dec_bits ==? 11'bx_100_1100011;
$is_bge = $dec_bits ==? 11'bx_101_1100011;
$is_bltu = $dec_bits ==? 11'bx_110_1100011;
$is_bgeu = $dec_bits ==? 11'bx_111_1100011;
$is_addi = $dec_bits ==? 11'bx_000_0010011;
$is_add = $dec_bits ==? 11'b0_000_0110011;
// ALU
$result[31:0] =
$is_addi ? $src1_value + $imm :
$is_add ? $src1_value + $src2_value :
32'b0;
`BOGUS_USE($rs1 $rs1_valid $rs2 $rs2_valid $funct3 $funct3_valid $funct7 $funct7_valid $imm $imm_valid $rd $rd_valid $opcode)
// `BOGUS_USE($is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
// Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC;
m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $result[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
m4+cpu_viz()
\SV
endmodule