From ee49ceb7229fc629d8ab48d9287e936c43558701 Mon Sep 17 00:00:00 2001 From: Bernd Beuster Date: Tue, 24 Dec 2019 15:53:22 +0100 Subject: [PATCH] Update --- README.md | 6 +++--- riscv-dbg | 2 +- soc/fpga/cyclone-v-gx/rtl/ibex_soc.sv | 10 +++++----- soc/fpga/cyclone-v-gx/syn/ibex_wb.sdc | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/README.md b/README.md index 6867c52..4e61016 100644 --- a/README.md +++ b/README.md @@ -42,17 +42,17 @@ Simulated with Synopsys VCS. | nettle-aes | 113482 | 63235 | 1.79 | | | | mean | 1.56 | -## FPGA Implentation +## FPGA Implementation ### Intel/Cyclone-V [Cyclone V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) -For Quartus 19.1 use branch `ibex/fpga_quartus`. +For Quartus 19.1 use branch `fpga_quartus` in submodules `common_cells`, `ibex` and`riscv-dbg`. ### Xilinx/Artix-7 [Arty A7-100T](https://www.xilinx.com/products/boards-and-kits/1-w51quh.html) -For Vivado 2019.2 use branch `ibex/master`. +For Vivado 2019.2 use branch `master` in all submodules. ## Recources - [Wishbone at opencores.org](https://opencores.org/howto/wishbone) diff --git a/riscv-dbg b/riscv-dbg index 64feb85..d306f90 160000 --- a/riscv-dbg +++ b/riscv-dbg @@ -1 +1 @@ -Subproject commit 64feb85d23ccd0078a5cc374557ec0015fb55937 +Subproject commit d306f90eb1d23d0520b2cc22faca65366d4a7935 diff --git a/soc/fpga/cyclone-v-gx/rtl/ibex_soc.sv b/soc/fpga/cyclone-v-gx/rtl/ibex_soc.sv index de85b99..af3cbfe 100644 --- a/soc/fpga/cyclone-v-gx/rtl/ibex_soc.sv +++ b/soc/fpga/cyclone-v-gx/rtl/ibex_soc.sv @@ -169,11 +169,11 @@ module ibex_soc logic tdo_oe; assign rst = ~rst_n; - assign tck = GPIO[0]; - assign trst_n = GPIO[1]; - assign tms = GPIO[19]; - assign tdi = GPIO[20]; - assign GPIO[21] = tdo_oe ? tdo : 1'bz; + assign tck = GPIO[2]; + assign trst_n = GPIO[20]; + assign tms = GPIO[1]; + assign tdi = GPIO[0]; + assign GPIO[19] = tdo_oe ? tdo : 1'bz; wb_if wbm[3](.*); wb_if wbs[3](.*); diff --git a/soc/fpga/cyclone-v-gx/syn/ibex_wb.sdc b/soc/fpga/cyclone-v-gx/syn/ibex_wb.sdc index 3e3be04..6274e78 100644 --- a/soc/fpga/cyclone-v-gx/syn/ibex_wb.sdc +++ b/soc/fpga/cyclone-v-gx/syn/ibex_wb.sdc @@ -41,7 +41,7 @@ set_time_format -unit ns -decimal_places 3 create_clock -name {SYS_CLK} -period 20.000 -waveform { 0.000 10.000 } [get_ports { CLOCK_50_B5B }] -create_clock -name {TCK} -period 100.000 -waveform { 0.000 50.000 } [get_ports { GPIO[0] }] +create_clock -name {TCK} -period 100.000 -waveform { 0.000 50.000 } [get_ports { GPIO[2] }] #************************************************************** @@ -74,7 +74,7 @@ set_clock_uncertainty -fall_from [get_clocks {SYS_CLK}] -fall_to [get_clocks {SY # Set Input Delay #************************************************************** -set_input_delay -clock_fall -clock [get_clocks TCK] 0.0 [get_ports {GPIO[1] GPIO[19] GPIO[20]}] +set_input_delay -clock_fall -clock [get_clocks TCK] 0.0 [get_ports {GPIO[0] GPIO[1] GPIO[20]}] @@ -82,7 +82,7 @@ set_input_delay -clock_fall -clock [get_clocks TCK] 0.0 [get_ports {GPIO[1] GPIO # Set Output Delay #************************************************************** -set_output_delay -clock [get_clocks TCK] 0.0 [get_ports {GPIO[21]}] +set_output_delay -clock [get_clocks TCK] 0.0 [get_ports {GPIO[19]}]