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Commits on Sep 14, 2023

• log: use XMR instead of boring utils for logging (OpenXiangShan#2302)

  Tang-Haojin

  authored
  e47ee55

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• add redirect latency stats, and use histogram for some old stats (OpenXiangShan#2299)

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  Lingrui98

  and

  chenguokai

  authored
  209a4ca

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• ftq: fix predecode redirect use RAS condition (OpenXiangShan#2300)

  eastonman

  authored
  f1267a1

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• bump CPL2: make sure pftRespQueue will never overflow (OpenXiangShan#2295)

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  Ivyfeather

  authored
  2e04129

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Commits on Sep 13, 2023

• ITTAGE: use ITTAGE result even when not confident (OpenXiangShan#2276)

  chenguokai

  authored
  bab3f1d

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• Frontend: timing optimization (OpenXiangShan#2291)

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  chenguokai

  authored
  330aad7

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• Add support for coverage-guided fuzzing (OpenXiangShan#2297)

  poemonsense

  authored
  806cf37

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• CSR: fix the writable mask of mie (OpenXiangShan#2296)

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  poemonsense

  authored
  51fb925

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Commits on Sep 12, 2023

• CSR: mstatus bits 0 and 4 are read-only zeros (OpenXiangShan#2294)

  poemonsense

  authored
  443741b

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Commits on Sep 11, 2023

• sms: fix evict condition (OpenXiangShan#2288)

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  happy-lx

  authored
  d7fb6da

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Commits on Sep 10, 2023

• Bump difftest for Chisel-generated interfaces (OpenXiangShan#2284)

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  poemonsense

  authored
  7d45a14

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Commits on Sep 6, 2023

• icache: change itlb port to no-blocked and new fdip (OpenXiangShan#2277)

  ssszwic

  authored
  cb6e5d3

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• ICache: shrink to 64K (OpenXiangShan#2282)

  chenguokai

  authored
  76b0dfe

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• L1 Prefetch (OpenXiangShan#2261)

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  6 peopleauthored
  0d32f71

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• FTB(timing): fix s2 target & fallthrough address (OpenXiangShan#2273)

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  eastonman

  authored
  47c003a

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Commits on Sep 5, 2023

• perf: add cpi and topdown rolling db (OpenXiangShan#2280)

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  Lemover

  authored
  839e551

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Commits on Sep 4, 2023

• Frontend: fix jalTarget unintended value when no jalFault (OpenXiangShan#2203)

  chenguokai

  authored
  d10ddd6

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Commits on Sep 3, 2023

• LDU: fix prefetch train valid logic (OpenXiangShan#2272)

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  cz4e

  authored
  f6f10be

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• bump CPL2: fix grantBuf (OpenXiangShan#2270)

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  Ivyfeather

  authored
  39b680d

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Commits on Sep 2, 2023

• Frontend: add basic instruction stream check (OpenXiangShan#2265)

  chenguokai

  authored
  5359309

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Commits on Sep 1, 2023

• LDU: fix l2l fwd (OpenXiangShan#2269)

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  cz4e

  authored
  c163075

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• ldu: add perf counter (OpenXiangShan#2268)

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  happy-lx

  authored
  a11e9ab

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Commits on Aug 30, 2023

• Support temporal prefetcher (disabled by default) (OpenXiangShan#2264)

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  wakafa1

  authored
  ffc9de5

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Commits on Aug 29, 2023

• fix s2_ldSsidAllocate/s2_stSsidAllocate (OpenXiangShan#2260)

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  cz4e

  authored
  11e10a0

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• wbq: fix wbq's FSM logic (OpenXiangShan#2259)

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  happy-lx

  authored
  9cb34a2

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Commits on Aug 26, 2023

• Difftest: emu explicitly pass seed to verilator with Verilated::randSeed (OpenXiangShan#2256)

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  klin02

  authored
  1de5a4a

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Commits on Aug 23, 2023

• FTB(timing): delay replacer update on read (OpenXiangShan#2227)

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  eastonman

  authored
  21bd600

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• icache: balance the pipeline to optimize timing (OpenXiangShan#2255)

  ssszwic

  authored
  0e8170d

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Commits on Aug 22, 2023

• bpu: duplicate most possible signal related to npc generation to address (OpenXiangShan#2254)

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  chenguokai

  and

  Lingrui98

  authored
  adc0b8d

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• fix stu feedback slow logic (OpenXiangShan#2252)

  cz4e

  authored
  87433ba

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Commits on Aug 19, 2023

• icache: fix bug that loses tlb access fault (OpenXiangShan#2251)

  pxk27

  authored
  4b2a95e

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• mq: remove usage of raw_data (OpenXiangShan#2249)

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  happy-lx

  authored
  9ebbb51

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Commits on Aug 18, 2023

• RAS: fix uninitialized top and write bypass entry (OpenXiangShan#2250)

  chenguokai

  authored
  8088cde

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Commits on Aug 17, 2023

• util: fix L2DB exists under FPGAPlatform (OpenXiangShan#2246)

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  Ivyfeather

  authored
  7b8f8f0

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• bump huancun (OpenXiangShan#2245)

  wakafa1

  authored
  7fce807

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