.gitignore

# Temporary and binary files
*~
*.py[cod]
*.so
*.cfg
!.isort.cfg
!setup.cfg
*.orig
*.log
*.pot
__pycache__/*
.cache/*
.*.swp
*/.ipynb_checkpoints/*
.DS_Store

# Project files
.ropeproject
.project
.pydevproject
.settings
.idea
.vscode
.dvt
tags

# Package files
*.egg
*.eggs/
.installed.cfg
*.egg-info
*.fsdb

# Unittest and coverage
htmlcov/*
.coverage
.coverage.*
.tox
junit*.xml
coverage.xml
.pytest_cache/

# Build and docs folder/files
build/*
dist/*
sdist/*
docs/api/*
docs/_rst/*
docs/_build/*
cover/*
MANIFEST

# Per-project virtualenvs
.venv*/
.conda*/
.python-version

# bender
.bender
#Bender.lock
#Bender.local
deps

# Auto generated sources
generated
#*.png
hw/test/jobs
test/*

# Vivado
scripts/vivado/add_sources.tcl
floonoc.xpr
vivado.jou
vivado_pid*
vivado_*
floonoc.sim
floonoc.runs
floonoc.ip_user_files
floonoc.hw
floonoc.cache
floonoc.runs
.Xil

# QuestaSim
work
work-vsim
modelsim.ini
transcript
vsim.wlf
scripts/compile_vsim.tcl

# VCS
scripts/compile_vcs.sh
AN.DB
simv.daidir
work-vcs
elabMhIdDidWork.txt
ucli.key
vc_hdrs.h
simv
work.lib++
verdi_config_file
verdiLog
.inter.fsdb.tbsim
inter.fsdb
inter.fsdb.*
floonoc.fsdb
floonoc.fsdb.*
novas.conf
novas.rc
simv.vdb
bin
logs
sysBusyPLog

# Fusion Compiler
fc_output.txt
synopsys.tcl
HDL_LIBRARIES

# Verible
verible*

# spyglass
scripts/spyglass/*

# Misc
*.csv
**/*.log
reviewdog

# Tmp
.vcs_checkpoint_shared_memory.*
floonoc_signal.rc
inter.fsdb.*
Makefile.Msimdepends
Makefile.Msimdepends.*
default-*.svf
*.rc