msr: Ice Lake Xeon CPUs: incorrect DRAM power limit lock bit, no clamping bit

[connorimes]

The April 2021 Intel Software Developer's Manual Volume 4 adds Table 2-47 in Section 2.17.6 with new information on the MSR_DRAM_POWER_LIMIT register for Ice Lake Xeon CPUs (0x6A and 0x6C). Per the combined volume Section 14.10.5, bit 31 is the standard lock bit, but this particular Ice Lake documentation says it's at bit 63.

Additionally, there does not appear to be a clamping bit (bit 16 is now Reserved).

It would be really nice if somebody could confirm the correct behavior, since I don't have any Ice Lake Xeon CPUs to test.