FlexPRET is a 5-stage, fine-grained multithreaded RISC-V processor designed specifically for mixed-criticality (real-time embedded) systems and written in Chisel. A hardware thread scheduler decides which hardware thread to start executing each cycle, regulated by configuration and status registers. Each hardware thread is either classified as a hard real-time thread (HRTT) or soft real-time thread (SRTT): HRTTs are only scheduled at a constant rate for hardware-based isolation and predictability (enabling independent formal verification), and SRTTs share remaining cycles (including when a HRTT doesn't need prescribed cycles) for efficient processor utilization. For comparison purposes, both single-threaded and round-robin multithreaded 5-stage RISC-V processors can also be generated. FlexPRET was developed at UC Berkeley as part of the PRET project.
Note: the porting is not complete for the privileged RISC-V 2.0 ISA, so some tests are disabled.
For more information on the processor architecture:
- Michael Zimmer, "Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O," Ph.D. Dissertation, EECS Department, University of California, Berkeley, UCB/EECS-2015-181, 2015.
- Michael Zimmer, David Broman, Chris Shaver, Edward A. Lee. "FlexPRET: A Processor Platform for Mixed-Criticality Systems. Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), April, 2014.
We use the Newlib installation of the rv32i-4.0.0. Download and extract it to a convenient location on the PATH.
We use the verilator toolchain for running emulations of the core. Install it and check that the version is greater than 4.038.
sudo apt install verilator
verilator --version
If you intend to run FlexPRET on a Xilinx FPGA, you will need to install Vivado. Refer to Xilinx installation guides.
After cloning the repository, update submodules with:
git submodule update --init --recursive
To run all unit tests for FlexPRET:
sbt test
To run a specific unit test (e.g. SimpleCoreTest):
sbt 'testOnly flexpret.core.test.SimpleCoreTest'
Unit tests are found under src/test/scala/core/.
To build the emulator with a default configuration and run all C tests:
make clean emulator
make -C programs/tests all
Software can both be run on an emulator and a Field-Programmable Gate Array (FPGA). Running on an FPGA requires quite a lot of setup - we recommend running on an emulator to start. Either way, you will need to install the RISC-V compiler (in particular, riscv32-unknown-elf-*).
Note that software compiled for the emulator and FPGA are not compatible. Software is by default compiled for the emulator; to compile software for FPGA, see Running on FPGA.
THREADS=[1-8]Specify number of hardware threadsFLEXPRET=[true/false]Use flexible thread schedulingISPM_KBYTES=[]Size of instruction scratchpad memory (32 bit words)DSPM_KBYTES=[]Size of instruction scratchpad memory (32 bit words)SUFFIX=[min,ex,ti,all]min: base RV32Iex:min+ exceptions (necessary)ti:ex+ timing instructionsall:ti+ all exception causes and stats
Not all combinations are valid.
To override the configuration, either edit the variables directly in ./Makefile or override them through the command line, like so:
make clean emulator THREADS=4 ISPM_KBYTES=128
The built configuration is available to software through a number of generated files. The configuration files are:
./hwconfig.mk./swconfig.mk(not generated)./programs/lib/include/flexpret_hwconfig.h./programs/lib/include/flexpret_swconfig.h./programs/lib/linker/flexpret_swconfig.ld./programs/lib/linker/flexpret_swconfig.ld
The use case for this is:
#include <flexpret_hwconfig.h>
#include <flexpret_thread.h>
fp_thread_t tid[NUM_THREADS-1];
for (int i = 0; i < NUM_THREADS-1; i++) {
fp_thread_create(HRTT, &tid[i], fnc, NULL);
}Which will start all threads for any number of threads available on the built FlexPRET. See the tests for more example use cases.
We use verilator for emulation. Note that a modern version of Verilator is required (e.g. Verilator 4.038+).
To build the emulator, run make emulator in the root directory. This will build the default configuration. See the instructions printed after running the above, or read them in emulator/emulator.mk on how to use the simulator.
To run a basic Fibonnaci example in simulation, run:
# cd into the fib directory
cd programs/tests/c-tests/fib/
# Delete old program and compile again
make clean compile
# Run the simulation.
make run
Which should print out:
[0]: fib(16) is 987
[0]: fib(20) is 6765
[0]: ../../../..//programs/lib/syscalls/syscalls.c: 49: Finish
To set pins on the FlexPRET (e.g., to emulate external interrupts or communication protocols), refer to the emulator client README.md.
To run a C regression test for the current processor configurations
cd programs/tests/
make
This will run all single-threaded test cases if the FlexPRET configuration has a single hardware thread, and both the single-threaded and multi-threaded test cases otherwise.
Magnus: To be written. Will be done on fpga branch.
Ensure all git submodules are initialized and up-to-date.
git submodule update --init --recursive
build/Temporary folder used as part of the buildprograms/C and assembly programs and test suiteslib/Libraries, linker scripts, and startup scriptstests/C test cases
scripts/Various scriptsc/Scripts for compiling C programshdl/Scripts for processing HDL programsfpga/Scripts for configuring programs on an FPGA
src/main/scala/RTL source filesCore/FlexPRET processor (and baseline processors) in Chiseluart/Verilog code for UART
src/test/scala/Unit teststest/Unit testing scripts
We use Chisel version 3.5.5.
To learn more about Chisel, visit its website and particularly the documentation section.
- Michael Zimmer ([email protected])
- Chris Shaver ([email protected])
- Hokeun Kim ([email protected])
- David Broman ([email protected])
- Edward Wang ([email protected])
- Shaokai Lin ([email protected])
- Erling Jellum ([email protected])
- Martin Schoeberl ([email protected])
- Samuel Berkun ([email protected])
- Magnus Mæhlum ([email protected])