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hal_halmac.c
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/******************************************************************************
*
* Copyright(c) 2015 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_HALMAC_C_
#include <drv_types.h> /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
#include <hal_data.h> /* efuse, PHAL_DATA_TYPE and etc. */
#include "hal_halmac.h" /* dvobj_to_halmac() and ect. */
/*
* HALMAC take return value 0 for fail and 1 for success to replace
* _FALSE/_TRUE after V1_04_09
*/
#define RTW_HALMAC_FAIL 0
#define RTW_HALMAC_SUCCESS 1
#define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */
#define MSG_PREFIX "[HALMAC]"
#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX
#define RTW_HALMAC_FILTER_DRV_C2H /* Block C2H owner=driver */
/*
* Driver API for HALMAC operations
*/
#ifdef CONFIG_SDIO_HCI
#include <rtw_sdio.h>
static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)
{
#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)
struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;
u32 mac_reg_offset = 0;
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
return _TRUE;
if (pwrpriv->lps_level == LPS_NORMAL)
return _TRUE;
if (pwrpriv->rpwm >= PS_STATE_S2)
return _TRUE;
if (offset & (WLAN_IOREG_DEVICE_ID << 13)) { /*WLAN_IOREG_OFFSET*/
mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;
if (mac_reg_offset < 0x100) {
RTW_ERR(FUNC_ADPT_FMT
"access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n",
FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,
pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);
rtw_warn_on(1);
return _FALSE;
}
}
#endif
return _TRUE;
}
static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
{
struct dvobj_priv *d;
u8 val;
u8 ret;
d = (struct dvobj_priv *)p;
_halmac_mac_reg_page0_chk(__func__, d, offset);
ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
if (_FAIL == ret) {
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
return SDIO_ERR_VAL8;
}
return val;
}
static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
{
struct dvobj_priv *d;
u8 ret;
d = (struct dvobj_priv *)p;
_halmac_mac_reg_page0_chk(__func__, d, offset);
ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
if (_FAIL == ret)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
{
struct dvobj_priv *d;
u8 *pbuf;
u8 val;
u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL8;
_halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(1);
if (!pbuf)
return val;
ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);
if (ret == _FAIL) {
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
val = *pbuf;
exit:
rtw_mfree(pbuf, 1);
return val;
}
static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
{
struct dvobj_priv *d;
u8 *pbuf;
u16 val;
u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL16;
_halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(2);
if (!pbuf)
return val;
ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);
if (ret == _FAIL) {
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
val = le16_to_cpu(*(u16 *)pbuf);
exit:
rtw_mfree(pbuf, 2);
return val;
}
static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
{
struct dvobj_priv *d;
u8 *pbuf;
u32 val;
u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL32;
_halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(4);
if (!pbuf)
return val;
ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);
if (ret == _FAIL) {
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
val = le32_to_cpu(*(u32 *)pbuf);
exit:
rtw_mfree(pbuf, 4);
return val;
}
static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
{
struct dvobj_priv *d = (struct dvobj_priv *)p;
u8 *pbuf;
u8 ret;
u8 rst = RTW_HALMAC_FAIL;
u32 sdio_read_size;
if (!data)
return rst;
sdio_read_size = RND4(size);
sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
pbuf = rtw_zmalloc(sdio_read_size);
if (!pbuf)
return rst;
ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
if (ret == _FAIL) {
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
_rtw_memcpy(data, pbuf, size);
rst = RTW_HALMAC_SUCCESS;
exit:
rtw_mfree(pbuf, sdio_read_size);
return rst;
}
static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
{
struct dvobj_priv *d;
u8 *pbuf;
u8 ret;
d = (struct dvobj_priv *)p;
_halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(1);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 1);
ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);
if (ret == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 1);
}
static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
{
struct dvobj_priv *d;
u8 *pbuf;
u8 ret;
d = (struct dvobj_priv *)p;
_halmac_mac_reg_page0_chk(__func__, d, offset);
val = cpu_to_le16(val);
pbuf = rtw_zmalloc(2);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 2);
ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);
if (ret == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 2);
}
static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
{
struct dvobj_priv *d;
u8 *pbuf;
u8 ret;
d = (struct dvobj_priv *)p;
_halmac_mac_reg_page0_chk(__func__, d, offset);
val = cpu_to_le32(val);
pbuf = rtw_zmalloc(4);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 4);
ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);
if (ret == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 4);
}
static u8 _halmac_sdio_read_cia(void *p, u32 offset)
{
struct dvobj_priv *d;
u8 data = 0;
u8 ret;
d = (struct dvobj_priv *)p;
ret = rtw_sdio_f0_read(d, offset, &data, 1);
if (ret == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
return data;
}
#else /* !CONFIG_SDIO_HCI */
static u8 _halmac_reg_read_8(void *p, u32 offset)
{
struct dvobj_priv *d;
PADAPTER adapter;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return _rtw_read8(adapter, offset);
}
static u16 _halmac_reg_read_16(void *p, u32 offset)
{
struct dvobj_priv *d;
PADAPTER adapter;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return _rtw_read16(adapter, offset);
}
static u32 _halmac_reg_read_32(void *p, u32 offset)
{
struct dvobj_priv *d;
PADAPTER adapter;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return _rtw_read32(adapter, offset);
}
static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
{
struct dvobj_priv *d;
PADAPTER adapter;
int err;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = _rtw_write8(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
{
struct dvobj_priv *d;
PADAPTER adapter;
int err;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = _rtw_write16(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
{
struct dvobj_priv *d;
PADAPTER adapter;
int err;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = _rtw_write32(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
#endif /* !CONFIG_SDIO_HCI */
#ifdef DBG_IO
static void _halmac_reg_read_monitor(void *p, u32 addr, u32 len, u32 val
, const char *caller, const u32 line)
{
struct dvobj_priv *d = (struct dvobj_priv *)p;
_adapter *adapter = dvobj_get_primary_adapter(d);
dbg_rtw_reg_read_monitor(adapter, addr, len, val, caller, line);
}
static void _halmac_reg_write_monitor(void *p, u32 addr, u32 len, u32 val
, const char *caller, const u32 line)
{
struct dvobj_priv *d = (struct dvobj_priv *)p;
_adapter *adapter = dvobj_get_primary_adapter(d);
dbg_rtw_reg_write_monitor(adapter, addr, len, val, caller, line);
}
#endif
static u8 _halmac_mfree(void *p, void *buffer, u32 size)
{
rtw_mfree(buffer, size);
return RTW_HALMAC_SUCCESS;
}
static void *_halmac_malloc(void *p, u32 size)
{
return rtw_zmalloc(size);
}
static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
{
_rtw_memcpy(dest, src, size);
return RTW_HALMAC_SUCCESS;
}
static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
{
_rtw_memset(addr, value, size);
return RTW_HALMAC_SUCCESS;
}
static void _halmac_udelay(void *p, u32 us)
{
/* Most hardware polling wait time < 50us) */
if (us <= 50)
rtw_udelay_os(us);
else if (us <= 1000)
rtw_usleep_os(us);
else
rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));
}
static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
{
_rtw_mutex_init(pMutex);
return RTW_HALMAC_SUCCESS;
}
static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
{
_rtw_mutex_free(pMutex);
return RTW_HALMAC_SUCCESS;
}
static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
{
int err;
err = _enter_critical_mutex(pMutex, NULL);
if (err)
return RTW_HALMAC_FAIL;
return RTW_HALMAC_SUCCESS;
}
static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
{
_exit_critical_mutex(pMutex, NULL);
return RTW_HALMAC_SUCCESS;
}
#ifndef CONFIG_SDIO_HCI
#define DBG_MSG_FILTER
#endif
#ifdef DBG_MSG_FILTER
static u8 is_msg_allowed(uint drv_lv, u8 msg_lv)
{
switch (drv_lv) {
case _DRV_NONE_:
return _FALSE;
case _DRV_ALWAYS_:
if (msg_lv > HALMAC_DBG_ALWAYS)
return _FALSE;
break;
case _DRV_ERR_:
if (msg_lv > HALMAC_DBG_ERR)
return _FALSE;
break;
case _DRV_WARNING_:
if (msg_lv > HALMAC_DBG_WARN)
return _FALSE;
break;
case _DRV_INFO_:
if (msg_lv >= HALMAC_DBG_TRACE)
return _FALSE;
break;
}
return _TRUE;
}
#endif /* DBG_MSG_FILTER */
static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
{
#define MSG_LEN 100
va_list args;
u8 str[MSG_LEN] = {0};
#ifdef DBG_MSG_FILTER
uint drv_level = _DRV_NONE_;
#endif
int err;
u8 ret = RTW_HALMAC_SUCCESS;
#ifdef DBG_MSG_FILTER
#ifdef CONFIG_RTW_DEBUG
drv_level = rtw_drv_log_level;
#endif
if (is_msg_allowed(drv_level, msg_level) == _FALSE)
return ret;
#endif
str[0] = '\n';
va_start(args, fmt);
err = vsnprintf(str, MSG_LEN, fmt, args);
va_end(args);
/* An output error is encountered */
if (err < 0)
return RTW_HALMAC_FAIL;
/* Output may be truncated due to size limit */
if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
ret = RTW_HALMAC_FAIL;
if (msg_level == HALMAC_DBG_ALWAYS)
RTW_PRINT(MSG_PREFIX "%s", str);
else if (msg_level <= HALMAC_DBG_ERR)
RTW_ERR(MSG_PREFIX "%s", str);
else if (msg_level <= HALMAC_DBG_WARN)
RTW_WARN(MSG_PREFIX "%s", str);
else
RTW_DBG(MSG_PREFIX "%s", str);
return ret;
}
static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
{
if (msg_level <= HALMAC_DBG_WARN)
RTW_INFO_DUMP(MSG_PREFIX, buf, size);
else
RTW_DBG_DUMP(MSG_PREFIX, buf, size);
return RTW_HALMAC_SUCCESS;
}
const char *const RTW_HALMAC_FEATURE_NAME[] = {
"HALMAC_FEATURE_CFG_PARA",
"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK",
"HALMAC_FEATURE_UPDATE_PACKET",
"HALMAC_FEATURE_SEND_SCAN_PACKET",
"HALMAC_FEATURE_DROP_SCAN_PACKET",
"HALMAC_FEATURE_UPDATE_DATAPACK",
"HALMAC_FEATURE_RUN_DATAPACK",
"HALMAC_FEATURE_CHANNEL_SWITCH",
"HALMAC_FEATURE_IQK",
"HALMAC_FEATURE_POWER_TRACKING",
"HALMAC_FEATURE_PSD",
"HALMAC_FEATURE_FW_SNDING",
"HALMAC_FEATURE_DPK",
"HALMAC_FEATURE_ALL"
};
static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)
{
switch (id) {
case HALMAC_FEATURE_CFG_PARA:
RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
if (HALMAC_CMD_PROCESS_DONE != status)
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
break;
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
if (HALMAC_CMD_PROCESS_DONE != status)
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
break;
case HALMAC_FEATURE_UPDATE_PACKET:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
if (status != HALMAC_CMD_PROCESS_DONE)
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
break;
case HALMAC_FEATURE_UPDATE_DATAPACK:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_RUN_DATAPACK:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_CHANNEL_SWITCH:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
if ((status != HALMAC_CMD_PROCESS_DONE) && (status != HALMAC_CMD_PROCESS_RCVD))
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
if (status == HALMAC_CMD_PROCESS_DONE)
return _FALSE;
break;
case HALMAC_FEATURE_IQK:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_POWER_TRACKING:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_PSD:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_FW_SNDING:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_DPK:
if (status == HALMAC_CMD_PROCESS_RCVD)
return _FALSE;
if ((status != HALMAC_CMD_PROCESS_DONE)
|| (status != HALMAC_CMD_PROCESS_ERROR))
RTW_WARN("%s: %s unexpected status(0x%x)!\n",
__FUNCTION__, RTW_HALMAC_FEATURE_NAME[id],
status);
break;
case HALMAC_FEATURE_ALL:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
default:
RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id);
return _FALSE;
}
return _TRUE;
}
static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)
{
struct submit_ctx *sctx;
if (!d->hmpriv.indicator[id].sctx) {
sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));
if (!sctx)
return -1;
} else {
RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
sctx = d->hmpriv.indicator[id].sctx;
d->hmpriv.indicator[id].sctx = NULL;
}
rtw_sctx_init(sctx, time);
d->hmpriv.indicator[id].buffer = buf;
d->hmpriv.indicator[id].buf_size = size;
d->hmpriv.indicator[id].ret_size = 0;
d->hmpriv.indicator[id].status = 0;
/* fill sctx at least to sure other variables are all ready! */
d->hmpriv.indicator[id].sctx = sctx;
return 0;
}
static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)
{
return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
}
static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
{
struct submit_ctx *sctx;
if (!d->hmpriv.indicator[id].sctx)
return;
sctx = d->hmpriv.indicator[id].sctx;
d->hmpriv.indicator[id].sctx = NULL;
rtw_mfree((u8 *)sctx, sizeof(*sctx));
}
static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
{
struct halmac_adapter *mac;
struct halmac_api *api;
struct submit_ctx *sctx;
int status;
int ret;
sctx = d->hmpriv.indicator[id].sctx;
if (!sctx)
return -1;
ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);
status = sctx->status;
free_halmac_event(d, id);
if (_SUCCESS == ret)
return 0;
/* If no one change sctx->status, it is timeout case */
if (status == 0)
status = RTW_SCTX_DONE_TIMEOUT;
RTW_ERR("%s: id(%d, %s) status=0x%x ! Reset HALMAC state!\n",
__FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id], status);
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
api->halmac_reset_feature(mac, id);
return -1;
}
/*
* Return:
* Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.
*/
static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id,
enum halmac_cmd_process_status process_status,
u8 *buf, u32 size)
{
struct dvobj_priv *d;
PADAPTER adapter;
PHAL_DATA_TYPE hal;
struct halmac_indicator *tbl, *indicator;
struct submit_ctx *sctx;
u32 cpsz;
u8 ret;
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
hal = GET_HAL_DATA(adapter);
tbl = d->hmpriv.indicator;
/* Filter(Skip) middle status indication */
ret = is_valid_id_status(feature_id, process_status);
if (_FALSE == ret)
goto exit;
indicator = &tbl[feature_id];
indicator->status = process_status;
indicator->ret_size = size;
if (!indicator->sctx) {
RTW_WARN("%s: id(%d, %s) is not waiting!!\n", __FUNCTION__,
feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
goto exit;
}
sctx = indicator->sctx;
if (HALMAC_CMD_PROCESS_ERROR == process_status) {
RTW_ERR("%s: id(%d, %s) Something wrong!!\n", __FUNCTION__,
feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
if ((size == 1) && buf)
RTW_ERR("%s: error code=0x%x\n", __FUNCTION__, *buf);
rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
goto exit;
}
if (size > indicator->buf_size) {
RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), "
"and data will be truncated!\n",
__FUNCTION__,
feature_id, RTW_HALMAC_FEATURE_NAME[feature_id],
indicator->buf_size, size);
cpsz = indicator->buf_size;
} else {
cpsz = size;
}
if (cpsz && indicator->buffer)
_rtw_memcpy(indicator->buffer, buf, cpsz);
rtw_sctx_done(&sctx);
exit:
return RTW_HALMAC_SUCCESS;
}
struct halmac_platform_api rtw_halmac_platform_api = {
/* R/W register */
#ifdef CONFIG_SDIO_HCI
.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
.SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
#endif /* CONFIG_SDIO_HCI */
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
.REG_READ_8 = _halmac_reg_read_8,
.REG_READ_16 = _halmac_reg_read_16,
.REG_READ_32 = _halmac_reg_read_32,
.REG_WRITE_8 = _halmac_reg_write_8,
.REG_WRITE_16 = _halmac_reg_write_16,
.REG_WRITE_32 = _halmac_reg_write_32,
#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
#ifdef DBG_IO
.READ_MONITOR = _halmac_reg_read_monitor,
.WRITE_MONITOR = _halmac_reg_write_monitor,
#endif
/* Write data */
#if 0
/* impletement in HAL-IC level */
.SEND_RSVD_PAGE = sdio_write_data_rsvd_page,
.SEND_H2C_PKT = sdio_write_data_h2c,
#endif
/* Memory allocate */
.RTL_FREE = _halmac_mfree,
.RTL_MALLOC = _halmac_malloc,
.RTL_MEMCPY = _halmac_memcpy,
.RTL_MEMSET = _halmac_memset,
/* Sleep */
.RTL_DELAY_US = _halmac_udelay,
/* Process Synchronization */
.MUTEX_INIT = _halmac_mutex_init,
.MUTEX_DEINIT = _halmac_mutex_deinit,
.MUTEX_LOCK = _halmac_mutex_lock,
.MUTEX_UNLOCK = _halmac_mutex_unlock,
.MSG_PRINT = _halmac_msg_print,
.BUFF_PRINT = _halmac_buff_print,
.EVENT_INDICATION = _halmac_event_indication,
};
u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
{
struct halmac_adapter *mac;
struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
mac = dvobj_to_halmac(pintfhdl->pintf_dev);
api = HALMAC_GET_API(mac);
return api->halmac_reg_read_8(mac, addr);
}
u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
{
struct halmac_adapter *mac;
struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
mac = dvobj_to_halmac(pintfhdl->pintf_dev);
api = HALMAC_GET_API(mac);
return api->halmac_reg_read_16(mac, addr);
}
u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
{
struct halmac_adapter *mac;
struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
mac = dvobj_to_halmac(pintfhdl->pintf_dev);
api = HALMAC_GET_API(mac);
return api->halmac_reg_read_32(mac, addr);
}
static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
{
#if 1
struct _ADAPTER *a;
u32 i, n;
u16 val16;
u32 val32;
a = dvobj_get_primary_adapter(d);
i = addr & 0x3;
/* Handle address not start from 4 bytes alignment case */
if (i) {
val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));
n = 4 - i;
_rtw_memcpy(buf, ((u8 *)&val32) + i, n);
i = n;
cnt -= n;
}
while (cnt) {
if (cnt >= 4)
n = 4;
else if (cnt >= 2)
n = 2;
else
n = 1;
cnt -= n;
switch (n) {
case 1:
buf[i] = rtw_read8(a, addr+i);
i++;
break;
case 2:
val16 = cpu_to_le16(rtw_read16(a, addr+i));
_rtw_memcpy(&buf[i], &val16, 2);
i += 2;
break;
case 4:
val32 = cpu_to_le32(rtw_read32(a, addr+i));
_rtw_memcpy(&buf[i], &val32, 4);
i += 4;
break;
}
}
#else
struct _ADAPTER *a;
u32 i;
a = dvobj_get_primary_adapter(d);
for (i = 0; i < cnt; i++)
buf[i] = rtw_read8(a, addr + i);
#endif
}
#ifdef CONFIG_SDIO_HCI
static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
if (buf == NULL)
return -1;
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);
if (status != HALMAC_RET_SUCCESS) {
RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n",
__FUNCTION__, addr, cnt, status);
return -1;
}
return 0;
}
#endif /* CONFIG_SDIO_HCI */
void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
{
struct dvobj_priv *d;
if (pmem == NULL) {
RTW_ERR("pmem is NULL\n");
return;
}
d = pintfhdl->pintf_dev;
#ifdef CONFIG_SDIO_HCI
if (addr & 0xFFFF0000) {
int err = 0;
err = _sdio_read_local(d, addr, cnt, pmem);
if (!err)
return;
}
#endif /* CONFIG_SDIO_HCI */
_read_register(d, addr, cnt, pmem);
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
{
struct halmac_adapter *mac;
struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
mac = dvobj_to_halmac(pintfhdl->pintf_dev);
api = HALMAC_GET_API(mac);
/*return api->halmac_reg_read_indirect_8(mac, addr);*/
return api->halmac_reg_read_8(mac, addr);
}