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这是WHU武汉大学2023-2024学年 计卓班 计算机组成与设计 RISC-V CPU 流水线设计，包括Modelsim仿真测试，vivado下FPGA(NEXYS A7)测试。
多周期流水25条基础MIPS指令CPU实现。测试环境：vivado。编写语言：verilog。必选书籍：《自己动手写CPU》
Using Verilog and based on vivado, I design a 5-level pipeline CPU and a VGA module to display the information of CPU.