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Commits on Dec 19, 2024

• Merge pull request #250 from rust-embedded/crs-write-unsafe

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  romancardenas

  authored
  fe6da17

Commits on Dec 18, 2024

• Merge pull request #249 from rmsyn/register/mstatush-csr-macro

  Show description for 433366f
  romancardenas

  authored
  433366f

• Simplify register macros

  romancardenas

  committed
  2dd1b65

• riscv: add basic unit tests for mstatush

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  rmsyn

  committed
  ed2a9ea

• riscv: define mstatush CSR with macro helpers

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  rmsyn

  committed
  25511f7

Commits on Dec 17, 2024

• Merge pull request #246 from rust-embedded/asm

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  romancardenas

  authored
  60800c1

• Merge pull request #245 from rmsyn/riscv/mstatus-csr-macro

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  romancardenas

  authored
  b3a42fd

Commits on Dec 14, 2024

• riscv: only define SXL/UXL setters for RV64

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  rmsyn

  and

  romancardenas

  committed
  906b027

• riscv: recommend Mstatush for mbe + sbe

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  rmsyn

  and

  romancardenas

  committed
  d28cd3e

Commits on Dec 12, 2024

• Merge pull request #243 from rust-embedded/rv32e-compat-asm

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  romancardenas

  authored
  3cd758b

Commits on Dec 11, 2024

• enforce 16-byte alignment

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  committed
  da3b8ac

Commits on Dec 7, 2024

• align riscv::asm with cortex-m

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  committed
  2ba1abf

Commits on Dec 5, 2024

• riscv: add more mstatus field tests

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  rmsyn

  committed
  43170a6

• riscv: add CSR test macro enum arm

  Show description for 5fad9f6
  rmsyn

  committed
  5fad9f6

• riscv: define mstatus CSR with macro helpers

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  rmsyn

  and

  romancardenas

  committed
  bb302b3

Commits on Dec 4, 2024

• Adjust stack alignment to 4-byte for E base ISAs

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  committed
  aee2106

Commits on Dec 3, 2024

• riscv: allow clippy::eq_op lint

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  rmsyn

  committed
  f8c9c84

• riscv: add field docs for CSR enum macro

  Show description for 171746b
  rmsyn

  committed
  171746b

Commits on Nov 28, 2024

• In case of collision, prioritize riscvi over riscve

  romancardenas

  committed
  ef18149

• Cleaner implementation of LLVM patch and changelog

  romancardenas

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  7815cd7

Commits on Nov 27, 2024

• Use environment variables for finding out the base ISA on riscv_rt_macros

  romancardenas

  committed
  fb14952

• Merge pull request #242 from rmsyn/riscv/mip-csr-macro

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  romancardenas

  authored
  ca4850a

Commits on Nov 26, 2024

• riscv: add mip unit tests

  Show description for 803a68c
  rmsyn

  committed
  803a68c

• riscv: define mip using CSR macros

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  rmsyn

  committed
  ffe20a5

Commits on Nov 20, 2024

• Merge pull request #244 from rmsyn/riscv/misa-csr-macro

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  romancardenas

  authored
  517d52b

Commits on Nov 19, 2024

• Use conditional dependencies in riscv-rt depending on base extension

  romancardenas

  committed
  1e71338

Commits on Nov 18, 2024

• Add riscv-target-parser crate

  romancardenas

  committed
  289206a

Commits on Nov 13, 2024

• riscv: add misa unit tests

  Show description for 100b6a1
  rmsyn

  committed
  100b6a1

• riscv: define misa using CSR macros

  Show description for 8b66b17
  rmsyn

  committed
  8b66b17

• riscv: remove unused field range for CSR field enum

  Show description for 6da32e7
  rmsyn

  committed
  6da32e7

Commits on Nov 9, 2024

• compatibility with RV32E

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  committed
  d6365e0

Commits on Nov 8, 2024

• Merge pull request #236 from rust-embedded/clean_linker_file

  Show description for fdc3bb6
  romancardenas

  authored
  fdc3bb6

• Merge pull request #241 from rmsyn/riscv/mimpid-csr-macro

  Show description for afc3efb
  romancardenas

  authored
  afc3efb

• riscv: define mimpid using CSR macros

  Show description for 630c91c
  rmsyn

  committed
  630c91c

Commits on Nov 7, 2024

• Merge pull request #240 from rmsyn/riscv/mie-csr-macro

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  romancardenas

  authored
  4605597

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