/*!
@defgroup targets Targets
@brief The complete set of experiments used in the uArch Leakage study.

@tableofcontents

# Target Platforms

*A list of candidate/realised devices and platforms on which to perform these
experiments*

---

## Implemented Platforms

- @ref targets-lpc812m101
- @ref targets-lpc1114fn28
- @ref targets-lpc1313fbd48
- @ref targets-sakurax-mb3
- @ref targets-sakurax-mb5
- @ref targets-sakurax-mb8
- @ref targets-sakurax-picorv32
- @ref targets-cw308-stm32f0
- @ref targets-cw308-stm32f1
- @ref targets-cw308-stm32f2
- @ref targets-cw308-stm32f3
- @ref targets-cw308-stm32f4

Each target platform can be identified in experiment code via the
`TARGET` pre-processor symbol which is passed via the command line:

Target Name  | Description  | `TARGET` Value
-------------|--------------|---------------------------------------
`scale_lpc812m101  ` | SCALE ARM M0+ Board / lpc812m101        | `1`
`scale_lpc1114fn28 ` | SCALE ARM M0 Board / lpc1114fn28        | `2`
`scale_lpc1313fbd48` | SCALE ARM M3 Board / lpc1313fbd48       | `3`
`sakurax_mb3       ` | SAKURA-X Microblaze 3-stage softcore    | `4`
`sakurax_mb5       ` | SAKURA-X Microblaze 5-stage softcore    | `5`
`sakurax_mb8       ` | SAKURA-X Microblaze 8-stage softcore    | `6`
`sakurax_picorv32  ` | SAKURA-X PicoRV32 multi-cycle softcore  | `7`
`cw308_stm32f0     ` | ST Mico ARM M0 Board / STM32-F0         | `9`
`cw308_stm32f1     ` | ST Mico ARM M3 Board / STM32-F1         | `10`
`cw308_stm32f2     ` | ST Mico ARM M3 Board / STM32-F2         | `11`
`cw308_stm32f3     ` | ST Mico ARM M4 Board / STM32-F3         | `12`
`cw308_stm32f4     ` | ST Mico ARM M4 Board / STM32-F3         | `13`
`intel_d2000       ` | Intel D2000 x86 Microcontroller         | `14`
`nxp_lpc1115fbd48  ` | NXP ARM M0 LPC1115FBD48                 | `15`

## Candidate Platforms

Notes on platforms that were initially considered as targets:

**FPGA + Xilinx Microblaze:**
- Use the Sasebo FPGA platform
- Use Xilinx own Microblaze configurable CPU.
- The CPU has a *configurable* pipeline depth, and it's micro-architecture
  is documented in 
  [Xilinx UG984](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug984-vivado-microblaze-ref.pdf).
  - Pipeline length: 3/5/8
- We can configure the surrounding AXI interconnect as well to add register
  stages to the memory busess.

**SCALE Boards:**

- ARM M0/3/4 core support.
- Possibly RISC-V support?
- Represent real world systems.
- Mostly un-documented internals of the CPUs themselves, some clues
  about pipeline information.


Note:
- According to [1], the M3 NOP instruction is actually killed in the
  decode stage, and does not affect later pipeline registers.
  This sort of effect is *extremely* important to identify.

**SiFive HiFive board:**

- Rocket chip based microcontroller
- Would need to mod it to get a scope onto the power trace.

**FPGA + PicoRV32:**

- A multi-cycle micro-architecture CPU.
- Interesting to run the same benchmarks on a multi-cycle machine and
  see what the differences are.

**FPGA + SCARV in house CPU:**

- 5 Stage pipeline
- Total control over internal micro-architecture.
- Very useful for logic gating experiments.
- Will eventually be used as host for pipeline XCrypto implementation,
  so useful to profile as a baseline anyway.

---

**References:**

1. Microarchitectural power simulator for leakage assessment of cryptographic
   software on ARM Cortex-M3 Processors. Yan Le Corre, Johann GroBschadl and
   Daniel Dinu.

*/