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elfload.c
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/* This is the Linux kernel elf-loading code, ported into user space */
#include "qemu/osdep.h"
#include <sys/param.h>
#include <sys/resource.h>
#include <sys/shm.h>
#include "qemu.h"
#include "disas/disas.h"
#include "qemu/bitops.h"
#include "qemu/path.h"
#include "qemu/queue.h"
#include "qemu/guest-random.h"
#include "qemu/units.h"
#include "qemu/selfmap.h"
#include "qapi/error.h"
#ifdef _ARCH_PPC64
#undef ARCH_DLINFO
#undef ELF_PLATFORM
#undef ELF_HWCAP
#undef ELF_HWCAP2
#undef ELF_CLASS
#undef ELF_DATA
#undef ELF_ARCH
#endif
#define ELF_OSABI ELFOSABI_SYSV
/* from personality.h */
/*
* Flags for bug emulation.
*
* These occupy the top three bytes.
*/
enum {
ADDR_NO_RANDOMIZE = 0x0040000, /* disable randomization of VA space */
FDPIC_FUNCPTRS = 0x0080000, /* userspace function ptrs point to
descriptors (signal handling) */
MMAP_PAGE_ZERO = 0x0100000,
ADDR_COMPAT_LAYOUT = 0x0200000,
READ_IMPLIES_EXEC = 0x0400000,
ADDR_LIMIT_32BIT = 0x0800000,
SHORT_INODE = 0x1000000,
WHOLE_SECONDS = 0x2000000,
STICKY_TIMEOUTS = 0x4000000,
ADDR_LIMIT_3GB = 0x8000000,
};
/*
* Personality types.
*
* These go in the low byte. Avoid using the top bit, it will
* conflict with error returns.
*/
enum {
PER_LINUX = 0x0000,
PER_LINUX_32BIT = 0x0000 | ADDR_LIMIT_32BIT,
PER_LINUX_FDPIC = 0x0000 | FDPIC_FUNCPTRS,
PER_SVR4 = 0x0001 | STICKY_TIMEOUTS | MMAP_PAGE_ZERO,
PER_SVR3 = 0x0002 | STICKY_TIMEOUTS | SHORT_INODE,
PER_SCOSVR3 = 0x0003 | STICKY_TIMEOUTS | WHOLE_SECONDS | SHORT_INODE,
PER_OSR5 = 0x0003 | STICKY_TIMEOUTS | WHOLE_SECONDS,
PER_WYSEV386 = 0x0004 | STICKY_TIMEOUTS | SHORT_INODE,
PER_ISCR4 = 0x0005 | STICKY_TIMEOUTS,
PER_BSD = 0x0006,
PER_SUNOS = 0x0006 | STICKY_TIMEOUTS,
PER_XENIX = 0x0007 | STICKY_TIMEOUTS | SHORT_INODE,
PER_LINUX32 = 0x0008,
PER_LINUX32_3GB = 0x0008 | ADDR_LIMIT_3GB,
PER_IRIX32 = 0x0009 | STICKY_TIMEOUTS,/* IRIX5 32-bit */
PER_IRIXN32 = 0x000a | STICKY_TIMEOUTS,/* IRIX6 new 32-bit */
PER_IRIX64 = 0x000b | STICKY_TIMEOUTS,/* IRIX6 64-bit */
PER_RISCOS = 0x000c,
PER_SOLARIS = 0x000d | STICKY_TIMEOUTS,
PER_UW7 = 0x000e | STICKY_TIMEOUTS | MMAP_PAGE_ZERO,
PER_OSF4 = 0x000f, /* OSF/1 v4 */
PER_HPUX = 0x0010,
PER_MASK = 0x00ff,
};
/*
* Return the base personality without flags.
*/
#define personality(pers) (pers & PER_MASK)
int info_is_fdpic(struct image_info *info)
{
return info->personality == PER_LINUX_FDPIC;
}
/* this flag is uneffective under linux too, should be deleted */
#ifndef MAP_DENYWRITE
#define MAP_DENYWRITE 0
#endif
/* should probably go in elf.h */
#ifndef ELIBBAD
#define ELIBBAD 80
#endif
#ifdef TARGET_WORDS_BIGENDIAN
#define ELF_DATA ELFDATA2MSB
#else
#define ELF_DATA ELFDATA2LSB
#endif
#ifdef TARGET_ABI_MIPSN32
typedef abi_ullong target_elf_greg_t;
#define tswapreg(ptr) tswap64(ptr)
#else
typedef abi_ulong target_elf_greg_t;
#define tswapreg(ptr) tswapal(ptr)
#endif
#ifdef USE_UID16
typedef abi_ushort target_uid_t;
typedef abi_ushort target_gid_t;
#else
typedef abi_uint target_uid_t;
typedef abi_uint target_gid_t;
#endif
typedef abi_int target_pid_t;
#ifdef TARGET_I386
#define ELF_PLATFORM get_elf_platform()
static const char *get_elf_platform(void)
{
static char elf_platform[] = "i386";
int family = object_property_get_int(OBJECT(thread_cpu), "family", NULL);
if (family > 6)
family = 6;
if (family >= 3)
elf_platform[1] = '0' + family;
return elf_platform;
}
#define ELF_HWCAP get_elf_hwcap()
static uint32_t get_elf_hwcap(void)
{
X86CPU *cpu = X86_CPU(thread_cpu);
return cpu->env.features[FEAT_1_EDX];
}
#ifdef TARGET_X86_64
#define ELF_START_MMAP 0x2aaaaab000ULL
#define ELF_CLASS ELFCLASS64
#define ELF_ARCH EM_X86_64
static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop)
{
regs->rax = 0;
regs->rsp = infop->start_stack;
regs->rip = infop->entry;
}
#define ELF_NREG 27
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
/*
* Note that ELF_NREG should be 29 as there should be place for
* TRAPNO and ERR "registers" as well but linux doesn't dump
* those.
*
* See linux kernel: arch/x86/include/asm/elf.h
*/
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
{
(*regs)[0] = tswapreg(env->regs[15]);
(*regs)[1] = tswapreg(env->regs[14]);
(*regs)[2] = tswapreg(env->regs[13]);
(*regs)[3] = tswapreg(env->regs[12]);
(*regs)[4] = tswapreg(env->regs[R_EBP]);
(*regs)[5] = tswapreg(env->regs[R_EBX]);
(*regs)[6] = tswapreg(env->regs[11]);
(*regs)[7] = tswapreg(env->regs[10]);
(*regs)[8] = tswapreg(env->regs[9]);
(*regs)[9] = tswapreg(env->regs[8]);
(*regs)[10] = tswapreg(env->regs[R_EAX]);
(*regs)[11] = tswapreg(env->regs[R_ECX]);
(*regs)[12] = tswapreg(env->regs[R_EDX]);
(*regs)[13] = tswapreg(env->regs[R_ESI]);
(*regs)[14] = tswapreg(env->regs[R_EDI]);
(*regs)[15] = tswapreg(env->regs[R_EAX]); /* XXX */
(*regs)[16] = tswapreg(env->eip);
(*regs)[17] = tswapreg(env->segs[R_CS].selector & 0xffff);
(*regs)[18] = tswapreg(env->eflags);
(*regs)[19] = tswapreg(env->regs[R_ESP]);
(*regs)[20] = tswapreg(env->segs[R_SS].selector & 0xffff);
(*regs)[21] = tswapreg(env->segs[R_FS].selector & 0xffff);
(*regs)[22] = tswapreg(env->segs[R_GS].selector & 0xffff);
(*regs)[23] = tswapreg(env->segs[R_DS].selector & 0xffff);
(*regs)[24] = tswapreg(env->segs[R_ES].selector & 0xffff);
(*regs)[25] = tswapreg(env->segs[R_FS].selector & 0xffff);
(*regs)[26] = tswapreg(env->segs[R_GS].selector & 0xffff);
}
#else
#define ELF_START_MMAP 0x80000000
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ( ((x) == EM_386) || ((x) == EM_486) )
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_ARCH EM_386
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
regs->esp = infop->start_stack;
regs->eip = infop->entry;
/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
starts %edx contains a pointer to a function which might be
registered using `atexit'. This provides a mean for the
dynamic linker to call DT_FINI functions for shared libraries
that have been loaded before the code runs.
A value of 0 tells we have no such handler. */
regs->edx = 0;
}
#define ELF_NREG 17
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
/*
* Note that ELF_NREG should be 19 as there should be place for
* TRAPNO and ERR "registers" as well but linux doesn't dump
* those.
*
* See linux kernel: arch/x86/include/asm/elf.h
*/
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
{
(*regs)[0] = tswapreg(env->regs[R_EBX]);
(*regs)[1] = tswapreg(env->regs[R_ECX]);
(*regs)[2] = tswapreg(env->regs[R_EDX]);
(*regs)[3] = tswapreg(env->regs[R_ESI]);
(*regs)[4] = tswapreg(env->regs[R_EDI]);
(*regs)[5] = tswapreg(env->regs[R_EBP]);
(*regs)[6] = tswapreg(env->regs[R_EAX]);
(*regs)[7] = tswapreg(env->segs[R_DS].selector & 0xffff);
(*regs)[8] = tswapreg(env->segs[R_ES].selector & 0xffff);
(*regs)[9] = tswapreg(env->segs[R_FS].selector & 0xffff);
(*regs)[10] = tswapreg(env->segs[R_GS].selector & 0xffff);
(*regs)[11] = tswapreg(env->regs[R_EAX]); /* XXX */
(*regs)[12] = tswapreg(env->eip);
(*regs)[13] = tswapreg(env->segs[R_CS].selector & 0xffff);
(*regs)[14] = tswapreg(env->eflags);
(*regs)[15] = tswapreg(env->regs[R_ESP]);
(*regs)[16] = tswapreg(env->segs[R_SS].selector & 0xffff);
}
#endif
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
#endif
#ifdef TARGET_ARM
#ifndef TARGET_AARCH64
/* 32 bit ARM definitions */
#define ELF_START_MMAP 0x80000000
#define ELF_ARCH EM_ARM
#define ELF_CLASS ELFCLASS32
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
abi_long stack = infop->start_stack;
memset(regs, 0, sizeof(*regs));
regs->uregs[16] = ARM_CPU_MODE_USR;
if (infop->entry & 1) {
regs->uregs[16] |= CPSR_T;
}
regs->uregs[15] = infop->entry & 0xfffffffe;
regs->uregs[13] = infop->start_stack;
/* FIXME - what to for failure of get_user()? */
get_user_ual(regs->uregs[2], stack + 8); /* envp */
get_user_ual(regs->uregs[1], stack + 4); /* envp */
/* XXX: it seems that r0 is zeroed after ! */
regs->uregs[0] = 0;
/* For uClinux PIC binaries. */
/* XXX: Linux does this only on ARM with no MMU (do we care ?) */
regs->uregs[10] = infop->start_data;
/* Support ARM FDPIC. */
if (info_is_fdpic(infop)) {
/* As described in the ABI document, r7 points to the loadmap info
* prepared by the kernel. If an interpreter is needed, r8 points
* to the interpreter loadmap and r9 points to the interpreter
* PT_DYNAMIC info. If no interpreter is needed, r8 is zero, and
* r9 points to the main program PT_DYNAMIC info.
*/
regs->uregs[7] = infop->loadmap_addr;
if (infop->interpreter_loadmap_addr) {
/* Executable is dynamically loaded. */
regs->uregs[8] = infop->interpreter_loadmap_addr;
regs->uregs[9] = infop->interpreter_pt_dynamic_addr;
} else {
regs->uregs[8] = 0;
regs->uregs[9] = infop->pt_dynamic_addr;
}
}
}
#define ELF_NREG 18
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUARMState *env)
{
(*regs)[0] = tswapreg(env->regs[0]);
(*regs)[1] = tswapreg(env->regs[1]);
(*regs)[2] = tswapreg(env->regs[2]);
(*regs)[3] = tswapreg(env->regs[3]);
(*regs)[4] = tswapreg(env->regs[4]);
(*regs)[5] = tswapreg(env->regs[5]);
(*regs)[6] = tswapreg(env->regs[6]);
(*regs)[7] = tswapreg(env->regs[7]);
(*regs)[8] = tswapreg(env->regs[8]);
(*regs)[9] = tswapreg(env->regs[9]);
(*regs)[10] = tswapreg(env->regs[10]);
(*regs)[11] = tswapreg(env->regs[11]);
(*regs)[12] = tswapreg(env->regs[12]);
(*regs)[13] = tswapreg(env->regs[13]);
(*regs)[14] = tswapreg(env->regs[14]);
(*regs)[15] = tswapreg(env->regs[15]);
(*regs)[16] = tswapreg(cpsr_read((CPUARMState *)env));
(*regs)[17] = tswapreg(env->regs[0]); /* XXX */
}
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
enum
{
ARM_HWCAP_ARM_SWP = 1 << 0,
ARM_HWCAP_ARM_HALF = 1 << 1,
ARM_HWCAP_ARM_THUMB = 1 << 2,
ARM_HWCAP_ARM_26BIT = 1 << 3,
ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
ARM_HWCAP_ARM_FPA = 1 << 5,
ARM_HWCAP_ARM_VFP = 1 << 6,
ARM_HWCAP_ARM_EDSP = 1 << 7,
ARM_HWCAP_ARM_JAVA = 1 << 8,
ARM_HWCAP_ARM_IWMMXT = 1 << 9,
ARM_HWCAP_ARM_CRUNCH = 1 << 10,
ARM_HWCAP_ARM_THUMBEE = 1 << 11,
ARM_HWCAP_ARM_NEON = 1 << 12,
ARM_HWCAP_ARM_VFPv3 = 1 << 13,
ARM_HWCAP_ARM_VFPv3D16 = 1 << 14,
ARM_HWCAP_ARM_TLS = 1 << 15,
ARM_HWCAP_ARM_VFPv4 = 1 << 16,
ARM_HWCAP_ARM_IDIVA = 1 << 17,
ARM_HWCAP_ARM_IDIVT = 1 << 18,
ARM_HWCAP_ARM_VFPD32 = 1 << 19,
ARM_HWCAP_ARM_LPAE = 1 << 20,
ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
};
enum {
ARM_HWCAP2_ARM_AES = 1 << 0,
ARM_HWCAP2_ARM_PMULL = 1 << 1,
ARM_HWCAP2_ARM_SHA1 = 1 << 2,
ARM_HWCAP2_ARM_SHA2 = 1 << 3,
ARM_HWCAP2_ARM_CRC32 = 1 << 4,
};
/* The commpage only exists for 32 bit kernels */
#define ARM_COMMPAGE (intptr_t)0xffff0f00u
static bool init_guest_commpage(void)
{
void *want = g2h_untagged(ARM_COMMPAGE & -qemu_host_page_size);
void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE,
MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
if (addr == MAP_FAILED) {
perror("Allocating guest commpage");
exit(EXIT_FAILURE);
}
if (addr != want) {
return false;
}
/* Set kernel helper versions; rest of page is 0. */
__put_user(5, (uint32_t *)g2h_untagged(0xffff0ffcu));
if (mprotect(addr, qemu_host_page_size, PROT_READ)) {
perror("Protecting guest commpage");
exit(EXIT_FAILURE);
}
return true;
}
#define ELF_HWCAP get_elf_hwcap()
#define ELF_HWCAP2 get_elf_hwcap2()
static uint32_t get_elf_hwcap(void)
{
ARMCPU *cpu = ARM_CPU(thread_cpu);
uint32_t hwcaps = 0;
hwcaps |= ARM_HWCAP_ARM_SWP;
hwcaps |= ARM_HWCAP_ARM_HALF;
hwcaps |= ARM_HWCAP_ARM_THUMB;
hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
/* probe for the extra features */
#define GET_FEATURE(feat, hwcap) \
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
#define GET_FEATURE_ID(feat, hwcap) \
do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
cpu_isar_feature(aa32_fpdp_v3, cpu)) {
hwcaps |= ARM_HWCAP_ARM_VFPv3;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
hwcaps |= ARM_HWCAP_ARM_VFPD32;
} else {
hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
}
}
GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
return hwcaps;
}
static uint32_t get_elf_hwcap2(void)
{
ARMCPU *cpu = ARM_CPU(thread_cpu);
uint32_t hwcaps = 0;
GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES);
GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL);
GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
return hwcaps;
}
#undef GET_FEATURE
#undef GET_FEATURE_ID
#define ELF_PLATFORM get_elf_platform()
static const char *get_elf_platform(void)
{
CPUARMState *env = thread_cpu->env_ptr;
#ifdef TARGET_WORDS_BIGENDIAN
# define END "b"
#else
# define END "l"
#endif
if (arm_feature(env, ARM_FEATURE_V8)) {
return "v8" END;
} else if (arm_feature(env, ARM_FEATURE_V7)) {
if (arm_feature(env, ARM_FEATURE_M)) {
return "v7m" END;
} else {
return "v7" END;
}
} else if (arm_feature(env, ARM_FEATURE_V6)) {
return "v6" END;
} else if (arm_feature(env, ARM_FEATURE_V5)) {
return "v5" END;
} else {
return "v4" END;
}
#undef END
}
#else
/* 64 bit ARM definitions */
#define ELF_START_MMAP 0x80000000
#define ELF_ARCH EM_AARCH64
#define ELF_CLASS ELFCLASS64
#ifdef TARGET_WORDS_BIGENDIAN
# define ELF_PLATFORM "aarch64_be"
#else
# define ELF_PLATFORM "aarch64"
#endif
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
abi_long stack = infop->start_stack;
memset(regs, 0, sizeof(*regs));
regs->pc = infop->entry & ~0x3ULL;
regs->sp = stack;
}
#define ELF_NREG 34
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
static void elf_core_copy_regs(target_elf_gregset_t *regs,
const CPUARMState *env)
{
int i;
for (i = 0; i < 32; i++) {
(*regs)[i] = tswapreg(env->xregs[i]);
}
(*regs)[32] = tswapreg(env->pc);
(*regs)[33] = tswapreg(pstate_read((CPUARMState *)env));
}
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
enum {
ARM_HWCAP_A64_FP = 1 << 0,
ARM_HWCAP_A64_ASIMD = 1 << 1,
ARM_HWCAP_A64_EVTSTRM = 1 << 2,
ARM_HWCAP_A64_AES = 1 << 3,
ARM_HWCAP_A64_PMULL = 1 << 4,
ARM_HWCAP_A64_SHA1 = 1 << 5,
ARM_HWCAP_A64_SHA2 = 1 << 6,
ARM_HWCAP_A64_CRC32 = 1 << 7,
ARM_HWCAP_A64_ATOMICS = 1 << 8,
ARM_HWCAP_A64_FPHP = 1 << 9,
ARM_HWCAP_A64_ASIMDHP = 1 << 10,
ARM_HWCAP_A64_CPUID = 1 << 11,
ARM_HWCAP_A64_ASIMDRDM = 1 << 12,
ARM_HWCAP_A64_JSCVT = 1 << 13,
ARM_HWCAP_A64_FCMA = 1 << 14,
ARM_HWCAP_A64_LRCPC = 1 << 15,
ARM_HWCAP_A64_DCPOP = 1 << 16,
ARM_HWCAP_A64_SHA3 = 1 << 17,
ARM_HWCAP_A64_SM3 = 1 << 18,
ARM_HWCAP_A64_SM4 = 1 << 19,
ARM_HWCAP_A64_ASIMDDP = 1 << 20,
ARM_HWCAP_A64_SHA512 = 1 << 21,
ARM_HWCAP_A64_SVE = 1 << 22,
ARM_HWCAP_A64_ASIMDFHM = 1 << 23,
ARM_HWCAP_A64_DIT = 1 << 24,
ARM_HWCAP_A64_USCAT = 1 << 25,
ARM_HWCAP_A64_ILRCPC = 1 << 26,
ARM_HWCAP_A64_FLAGM = 1 << 27,
ARM_HWCAP_A64_SSBS = 1 << 28,
ARM_HWCAP_A64_SB = 1 << 29,
ARM_HWCAP_A64_PACA = 1 << 30,
ARM_HWCAP_A64_PACG = 1UL << 31,
ARM_HWCAP2_A64_DCPODP = 1 << 0,
ARM_HWCAP2_A64_SVE2 = 1 << 1,
ARM_HWCAP2_A64_SVEAES = 1 << 2,
ARM_HWCAP2_A64_SVEPMULL = 1 << 3,
ARM_HWCAP2_A64_SVEBITPERM = 1 << 4,
ARM_HWCAP2_A64_SVESHA3 = 1 << 5,
ARM_HWCAP2_A64_SVESM4 = 1 << 6,
ARM_HWCAP2_A64_FLAGM2 = 1 << 7,
ARM_HWCAP2_A64_FRINT = 1 << 8,
ARM_HWCAP2_A64_SVEI8MM = 1 << 9,
ARM_HWCAP2_A64_SVEF32MM = 1 << 10,
ARM_HWCAP2_A64_SVEF64MM = 1 << 11,
ARM_HWCAP2_A64_SVEBF16 = 1 << 12,
ARM_HWCAP2_A64_I8MM = 1 << 13,
ARM_HWCAP2_A64_BF16 = 1 << 14,
ARM_HWCAP2_A64_DGH = 1 << 15,
ARM_HWCAP2_A64_RNG = 1 << 16,
ARM_HWCAP2_A64_BTI = 1 << 17,
ARM_HWCAP2_A64_MTE = 1 << 18,
};
#define ELF_HWCAP get_elf_hwcap()
#define ELF_HWCAP2 get_elf_hwcap2()
#define GET_FEATURE_ID(feat, hwcap) \
do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
static uint32_t get_elf_hwcap(void)
{
ARMCPU *cpu = ARM_CPU(thread_cpu);
uint32_t hwcaps = 0;
hwcaps |= ARM_HWCAP_A64_FP;
hwcaps |= ARM_HWCAP_A64_ASIMD;
hwcaps |= ARM_HWCAP_A64_CPUID;
/* probe for the extra features */
GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES);
GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL);
GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1);
GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2);
GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512);
GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32);
GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
return hwcaps;
}
static uint32_t get_elf_hwcap2(void)
{
ARMCPU *cpu = ARM_CPU(thread_cpu);
uint32_t hwcaps = 0;
GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2);
GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES);
GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL);
GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM);
GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3);
GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4);
GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM);
GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM);
GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM);
GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16);
GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM);
GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16);
GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
return hwcaps;
}
#undef GET_FEATURE_ID
#endif /* not TARGET_AARCH64 */
#endif /* TARGET_ARM */
#ifdef TARGET_SPARC
#ifdef TARGET_SPARC64
#define ELF_START_MMAP 0x80000000
#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \
| HWCAP_SPARC_MULDIV | HWCAP_SPARC_V9)
#ifndef TARGET_ABI32
#define elf_check_arch(x) ( (x) == EM_SPARCV9 || (x) == EM_SPARC32PLUS )
#else
#define elf_check_arch(x) ( (x) == EM_SPARC32PLUS || (x) == EM_SPARC )
#endif
#define ELF_CLASS ELFCLASS64
#define ELF_ARCH EM_SPARCV9
#else
#define ELF_START_MMAP 0x80000000
#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \
| HWCAP_SPARC_MULDIV)
#define ELF_CLASS ELFCLASS32
#define ELF_ARCH EM_SPARC
#endif /* TARGET_SPARC64 */
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
/* Note that target_cpu_copy_regs does not read psr/tstate. */
regs->pc = infop->entry;
regs->npc = regs->pc + 4;
regs->y = 0;
regs->u_regs[14] = (infop->start_stack - 16 * sizeof(abi_ulong)
- TARGET_STACK_BIAS);
}
#endif /* TARGET_SPARC */
#ifdef TARGET_PPC
#define ELF_MACHINE PPC_ELF_MACHINE
#define ELF_START_MMAP 0x80000000
#if defined(TARGET_PPC64) && !defined(TARGET_ABI32)
#define elf_check_arch(x) ( (x) == EM_PPC64 )
#define ELF_CLASS ELFCLASS64
#else
#define ELF_CLASS ELFCLASS32
#endif
#define ELF_ARCH EM_PPC
/* Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP).
See arch/powerpc/include/asm/cputable.h. */
enum {
QEMU_PPC_FEATURE_32 = 0x80000000,
QEMU_PPC_FEATURE_64 = 0x40000000,
QEMU_PPC_FEATURE_601_INSTR = 0x20000000,
QEMU_PPC_FEATURE_HAS_ALTIVEC = 0x10000000,
QEMU_PPC_FEATURE_HAS_FPU = 0x08000000,
QEMU_PPC_FEATURE_HAS_MMU = 0x04000000,
QEMU_PPC_FEATURE_HAS_4xxMAC = 0x02000000,
QEMU_PPC_FEATURE_UNIFIED_CACHE = 0x01000000,
QEMU_PPC_FEATURE_HAS_SPE = 0x00800000,
QEMU_PPC_FEATURE_HAS_EFP_SINGLE = 0x00400000,
QEMU_PPC_FEATURE_HAS_EFP_DOUBLE = 0x00200000,
QEMU_PPC_FEATURE_NO_TB = 0x00100000,
QEMU_PPC_FEATURE_POWER4 = 0x00080000,
QEMU_PPC_FEATURE_POWER5 = 0x00040000,
QEMU_PPC_FEATURE_POWER5_PLUS = 0x00020000,
QEMU_PPC_FEATURE_CELL = 0x00010000,
QEMU_PPC_FEATURE_BOOKE = 0x00008000,
QEMU_PPC_FEATURE_SMT = 0x00004000,
QEMU_PPC_FEATURE_ICACHE_SNOOP = 0x00002000,
QEMU_PPC_FEATURE_ARCH_2_05 = 0x00001000,
QEMU_PPC_FEATURE_PA6T = 0x00000800,
QEMU_PPC_FEATURE_HAS_DFP = 0x00000400,
QEMU_PPC_FEATURE_POWER6_EXT = 0x00000200,
QEMU_PPC_FEATURE_ARCH_2_06 = 0x00000100,
QEMU_PPC_FEATURE_HAS_VSX = 0x00000080,
QEMU_PPC_FEATURE_PSERIES_PERFMON_COMPAT = 0x00000040,
QEMU_PPC_FEATURE_TRUE_LE = 0x00000002,
QEMU_PPC_FEATURE_PPC_LE = 0x00000001,
/* Feature definitions in AT_HWCAP2. */
QEMU_PPC_FEATURE2_ARCH_2_07 = 0x80000000, /* ISA 2.07 */
QEMU_PPC_FEATURE2_HAS_HTM = 0x40000000, /* Hardware Transactional Memory */
QEMU_PPC_FEATURE2_HAS_DSCR = 0x20000000, /* Data Stream Control Register */
QEMU_PPC_FEATURE2_HAS_EBB = 0x10000000, /* Event Base Branching */
QEMU_PPC_FEATURE2_HAS_ISEL = 0x08000000, /* Integer Select */
QEMU_PPC_FEATURE2_HAS_TAR = 0x04000000, /* Target Address Register */
QEMU_PPC_FEATURE2_VEC_CRYPTO = 0x02000000,
QEMU_PPC_FEATURE2_HTM_NOSC = 0x01000000,
QEMU_PPC_FEATURE2_ARCH_3_00 = 0x00800000, /* ISA 3.00 */
QEMU_PPC_FEATURE2_HAS_IEEE128 = 0x00400000, /* VSX IEEE Bin Float 128-bit */
QEMU_PPC_FEATURE2_DARN = 0x00200000, /* darn random number insn */
QEMU_PPC_FEATURE2_SCV = 0x00100000, /* scv syscall */
QEMU_PPC_FEATURE2_HTM_NO_SUSPEND = 0x00080000, /* TM w/o suspended state */
};
#define ELF_HWCAP get_elf_hwcap()
static uint32_t get_elf_hwcap(void)
{
PowerPCCPU *cpu = POWERPC_CPU(thread_cpu);
uint32_t features = 0;
/* We don't have to be terribly complete here; the high points are
Altivec/FP/SPE support. Anything else is just a bonus. */
#define GET_FEATURE(flag, feature) \
do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0)
#define GET_FEATURE2(flags, feature) \
do { \
if ((cpu->env.insns_flags2 & flags) == flags) { \
features |= feature; \
} \
} while (0)
GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64);
GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU);
GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC);
GET_FEATURE(PPC_SPE, QEMU_PPC_FEATURE_HAS_SPE);
GET_FEATURE(PPC_SPE_SINGLE, QEMU_PPC_FEATURE_HAS_EFP_SINGLE);
GET_FEATURE(PPC_SPE_DOUBLE, QEMU_PPC_FEATURE_HAS_EFP_DOUBLE);
GET_FEATURE(PPC_BOOKE, QEMU_PPC_FEATURE_BOOKE);
GET_FEATURE(PPC_405_MAC, QEMU_PPC_FEATURE_HAS_4xxMAC);
GET_FEATURE2(PPC2_DFP, QEMU_PPC_FEATURE_HAS_DFP);
GET_FEATURE2(PPC2_VSX, QEMU_PPC_FEATURE_HAS_VSX);
GET_FEATURE2((PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 |
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206),
QEMU_PPC_FEATURE_ARCH_2_06);
#undef GET_FEATURE
#undef GET_FEATURE2
return features;
}
#define ELF_HWCAP2 get_elf_hwcap2()
static uint32_t get_elf_hwcap2(void)
{
PowerPCCPU *cpu = POWERPC_CPU(thread_cpu);
uint32_t features = 0;
#define GET_FEATURE(flag, feature) \
do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0)
#define GET_FEATURE2(flag, feature) \
do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR);
GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 |
QEMU_PPC_FEATURE2_VEC_CRYPTO);
GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
#undef GET_FEATURE
#undef GET_FEATURE2
return features;
}
/*
* The requirements here are:
* - keep the final alignment of sp (sp & 0xf)
* - make sure the 32-bit value at the first 16 byte aligned position of
* AUXV is greater than 16 for glibc compatibility.
* AT_IGNOREPPC is used for that.
* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
* even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
*/
#define DLINFO_ARCH_ITEMS 5
#define ARCH_DLINFO \
do { \
PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \
/* \
* Handle glibc compatibility: these magic entries must \
* be at the lowest addresses in the final auxv. \
*/ \
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \
NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \
NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \
} while (0)
static inline void init_thread(struct target_pt_regs *_regs, struct image_info *infop)
{
_regs->gpr[1] = infop->start_stack;
#if defined(TARGET_PPC64) && !defined(TARGET_ABI32)
if (get_ppc64_abi(infop) < 2) {
uint64_t val;
get_user_u64(val, infop->entry + 8);
_regs->gpr[2] = val + infop->load_bias;
get_user_u64(val, infop->entry);
infop->entry = val + infop->load_bias;
} else {
_regs->gpr[12] = infop->entry; /* r12 set to global entry address */
}
#endif
_regs->nip = infop->entry;
}
/* See linux kernel: arch/powerpc/include/asm/elf.h. */
#define ELF_NREG 48
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *env)
{
int i;
target_ulong ccr = 0;
for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
(*regs)[i] = tswapreg(env->gpr[i]);
}
(*regs)[32] = tswapreg(env->nip);
(*regs)[33] = tswapreg(env->msr);
(*regs)[35] = tswapreg(env->ctr);
(*regs)[36] = tswapreg(env->lr);
(*regs)[37] = tswapreg(env->xer);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
ccr |= env->crf[i] << (32 - ((i + 1) * 4));
}
(*regs)[38] = tswapreg(ccr);
}
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
#endif
#ifdef TARGET_MIPS
#define ELF_START_MMAP 0x80000000
#ifdef TARGET_MIPS64
#define ELF_CLASS ELFCLASS64
#else
#define ELF_CLASS ELFCLASS32
#endif
#define ELF_ARCH EM_MIPS
#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_NANOMIPS)
#ifdef TARGET_ABI_MIPSN32
#define elf_check_abi(x) ((x) & EF_MIPS_ABI2)
#else
#define elf_check_abi(x) (!((x) & EF_MIPS_ABI2))
#endif
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
regs->cp0_status = 2 << CP0St_KSU;
regs->cp0_epc = infop->entry;
regs->regs[29] = infop->start_stack;
}
/* See linux kernel: arch/mips/include/asm/elf.h. */
#define ELF_NREG 45
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
/* See linux kernel: arch/mips/include/asm/reg.h. */
enum {
#ifdef TARGET_MIPS64
TARGET_EF_R0 = 0,
#else
TARGET_EF_R0 = 6,
#endif
TARGET_EF_R26 = TARGET_EF_R0 + 26,
TARGET_EF_R27 = TARGET_EF_R0 + 27,
TARGET_EF_LO = TARGET_EF_R0 + 32,
TARGET_EF_HI = TARGET_EF_R0 + 33,
TARGET_EF_CP0_EPC = TARGET_EF_R0 + 34,
TARGET_EF_CP0_BADVADDR = TARGET_EF_R0 + 35,
TARGET_EF_CP0_STATUS = TARGET_EF_R0 + 36,
TARGET_EF_CP0_CAUSE = TARGET_EF_R0 + 37
};
/* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *env)
{
int i;
for (i = 0; i < TARGET_EF_R0; i++) {
(*regs)[i] = 0;
}
(*regs)[TARGET_EF_R0] = 0;
for (i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
(*regs)[TARGET_EF_R0 + i] = tswapreg(env->active_tc.gpr[i]);
}
(*regs)[TARGET_EF_R26] = 0;
(*regs)[TARGET_EF_R27] = 0;
(*regs)[TARGET_EF_LO] = tswapreg(env->active_tc.LO[0]);
(*regs)[TARGET_EF_HI] = tswapreg(env->active_tc.HI[0]);
(*regs)[TARGET_EF_CP0_EPC] = tswapreg(env->active_tc.PC);
(*regs)[TARGET_EF_CP0_BADVADDR] = tswapreg(env->CP0_BadVAddr);
(*regs)[TARGET_EF_CP0_STATUS] = tswapreg(env->CP0_Status);
(*regs)[TARGET_EF_CP0_CAUSE] = tswapreg(env->CP0_Cause);
}
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
/* See arch/mips/include/uapi/asm/hwcap.h. */
enum {
HWCAP_MIPS_R6 = (1 << 0),
HWCAP_MIPS_MSA = (1 << 1),
HWCAP_MIPS_CRC32 = (1 << 2),
HWCAP_MIPS_MIPS16 = (1 << 3),
HWCAP_MIPS_MDMX = (1 << 4),
HWCAP_MIPS_MIPS3D = (1 << 5),
HWCAP_MIPS_SMARTMIPS = (1 << 6),
HWCAP_MIPS_DSP = (1 << 7),
HWCAP_MIPS_DSP2 = (1 << 8),
HWCAP_MIPS_DSP3 = (1 << 9),
HWCAP_MIPS_MIPS16E2 = (1 << 10),
HWCAP_LOONGSON_MMI = (1 << 11),