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Commits on Dec 29, 2022

• Merge branch 'jerryz123-fix-ma_fetch'

  aswaterman

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• Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32

  jerryz123

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• Fix clean in isa/ with non-default compiler (riscv-software-src#443)

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  alexshpilkin

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Commits on Dec 27, 2022

• Merge pull request riscv-software-src#442 from riscv-software-src/ceasetest

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  timsifive

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Commits on Dec 15, 2022

• debug: Add CeaseRunTest

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• debug: Add CeaseStepiTest.

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• debug: Create CeaseMultiTest. (riscv-software-src#436)

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• debug: Remove unnecessary exit() functions. (riscv-software-src#437)

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Commits on Dec 9, 2022

• Fix regression in VcsSim introduced by riscv-software-src#334 (riscv-software-src#440)

  jerryz123

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Commits on Dec 8, 2022

• zicntr: separate cycle/instret accessibility test (riscv-software-src#439)

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  chihminchao

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Commits on Dec 1, 2022

• debug: Disassemble memory when a failure happens. (riscv-software-src#432)

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  timsifive

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• flush regs -> maintenance flush register-cache (riscv-software-src#431)

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  timsifive

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• debug: Park unused harts with a cease instruction. (riscv-software-src#434)

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• Share exit() among more tests. (riscv-software-src#433)

  timsifive

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Commits on Nov 10, 2022

• SvNNTest needs 32KB of RAM. (riscv-software-src#428)

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Commits on Nov 4, 2022

• Make MulticoreRegTest work with real hardware.

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Commits on Nov 3, 2022

• Fix PrivChange test address comparison. (riscv-software-src#427)

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Commits on Oct 26, 2022

• Specify trigger type=2 in trigger.S (riscv-software-src#425)

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  YenHaoChen

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  timsifive

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Commits on Oct 24, 2022

• Increase timeouts for multi-spike test. (riscv-software-src#423)

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Commits on Oct 21, 2022

• Change memory address used in debug tests. (riscv-software-src#422)

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Commits on Oct 20, 2022

• Merge pull request riscv-software-src#421 from riscv-software-src/pylint

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  timsifive

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• Merge pull request riscv-software-src#420 from riscv-software-src/test_fpr_progbuf

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  timsifive

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Commits on Oct 12, 2022

• Fix long line to make pylint happy.

  timsifive

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• Get coverage of progbuf FPR accesses.

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Commits on Oct 10, 2022

• Merge pull request riscv-software-src#417 from riscv-software-src/debug_server

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Commits on Oct 7, 2022

• debug: Add --debug_server arg to open gdb on OpenOCD

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Commits on Oct 6, 2022

• Merge pull request riscv-software-src#414 from YenHaoChen/pr-timestamp

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Commits on Oct 5, 2022

• Update testlib.py; remove ANSI escape sequences

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  YenHaoChen

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• update gdbserver.py; release tolerance value of MemorySampleTest()

  YenHaoChen

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Commits on Sep 27, 2022

• rv64ui test misaligned load/store data (riscv-software-src#410)

  ingallsj

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• zicboz: comment # (riscv-software-src#412)

  ingallsj

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Commits on Sep 26, 2022

• zicbo test zero (riscv-software-src#411)

  ingallsj

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Commits on Jul 25, 2022

• Ignore mip and time in DisconnectTest. (riscv-software-src#406)

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  timsifive

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Commits on Jul 22, 2022

• Fix string formatting in testlib.assertTrue()

  timsifive

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Commits on Jul 14, 2022

• Pylint fix. (riscv-software-src#405)

  timsifive

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