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DSi.cpp
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/*
Copyright 2016-2022 melonDS team
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include "NDS.h"
#include "DSi.h"
#include "ARM.h"
#include "GPU.h"
#include "NDSCart.h"
#include "SPI.h"
#include "DSi_SPI_TSC.h"
#include "Platform.h"
#ifdef JIT_ENABLED
#include "ARMJIT.h"
#include "ARMJIT_Memory.h"
#endif
#include "DSi_NDMA.h"
#include "DSi_I2C.h"
#include "DSi_SD.h"
#include "DSi_AES.h"
#include "DSi_NAND.h"
#include "DSi_DSP.h"
#include "DSi_Camera.h"
#include "tiny-AES-c/aes.hpp"
namespace DSi
{
u16 SCFG_BIOS;
u16 SCFG_Clock9;
u16 SCFG_Clock7;
u32 SCFG_EXT[2];
u32 SCFG_MC;
u16 SCFG_RST;
u8 ARM9iBIOS[0x10000];
u8 ARM7iBIOS[0x10000];
u32 MBK[2][9];
u8* NWRAM_A;
u8* NWRAM_B;
u8* NWRAM_C;
u8* NWRAMMap_A[2][4];
u8* NWRAMMap_B[3][8];
u8* NWRAMMap_C[3][8];
u32 NWRAMStart[2][3];
u32 NWRAMEnd[2][3];
u32 NWRAMMask[2][3];
u32 NDMACnt[2];
DSi_NDMA* NDMAs[8];
DSi_SDHost* SDMMC;
DSi_SDHost* SDIO;
u64 ConsoleID;
u8 eMMC_CID[16];
void Set_SCFG_Clock9(u16 val);
void Set_SCFG_MC(u32 val);
bool Init()
{
#ifndef JIT_ENABLED
NWRAM_A = new u8[NWRAMSize];
NWRAM_B = new u8[NWRAMSize];
NWRAM_C = new u8[NWRAMSize];
#endif
if (!DSi_I2C::Init()) return false;
if (!DSi_CamModule::Init()) return false;
if (!DSi_AES::Init()) return false;
if (!DSi_DSP::Init()) return false;
NDMAs[0] = new DSi_NDMA(0, 0);
NDMAs[1] = new DSi_NDMA(0, 1);
NDMAs[2] = new DSi_NDMA(0, 2);
NDMAs[3] = new DSi_NDMA(0, 3);
NDMAs[4] = new DSi_NDMA(1, 0);
NDMAs[5] = new DSi_NDMA(1, 1);
NDMAs[6] = new DSi_NDMA(1, 2);
NDMAs[7] = new DSi_NDMA(1, 3);
SDMMC = new DSi_SDHost(0);
SDIO = new DSi_SDHost(1);
return true;
}
void DeInit()
{
#ifndef JIT_ENABLED
delete[] NWRAM_A;
delete[] NWRAM_B;
delete[] NWRAM_C;
#endif
DSi_I2C::DeInit();
DSi_CamModule::DeInit();
DSi_AES::DeInit();
DSi_DSP::DeInit();
for (int i = 0; i < 8; i++) delete NDMAs[i];
delete SDMMC;
delete SDIO;
}
void Reset()
{
//NDS::ARM9->CP15Write(0x910, 0x0D00000A);
//NDS::ARM9->CP15Write(0x911, 0x00000020);
//NDS::ARM9->CP15Write(0x100, NDS::ARM9->CP15Read(0x100) | 0x00050000);
NDS::MapSharedWRAM(3);
NDMACnt[0] = 0; NDMACnt[1] = 0;
for (int i = 0; i < 8; i++) NDMAs[i]->Reset();
DSi_I2C::Reset();
DSi_CamModule::Reset();
DSi_DSP::Reset();
SDMMC->CloseHandles();
SDIO->CloseHandles();
LoadNAND();
SDMMC->Reset();
SDIO->Reset();
DSi_AES::Reset();
SCFG_BIOS = 0x0101; // TODO: should be zero when booting from BIOS
SCFG_Clock9 = 0x0187; // CHECKME
SCFG_Clock7 = 0x0187;
SCFG_EXT[0] = 0x8307F100;
SCFG_EXT[1] = 0x93FFFB06;
SCFG_MC = 0x0010 | (~((u32)NDSCart::CartInserted)&1);//0x0011;
SCFG_RST = 0;
DSi_DSP::SetRstLine(false);
// LCD init flag
GPU::DispStat[0] |= (1<<6);
GPU::DispStat[1] |= (1<<6);
}
void Stop()
{
DSi_CamModule::Stop();
}
void DoSavestate(Savestate* file)
{
file->Section("DSIG");
file->Var16(&SCFG_BIOS);
file->Var16(&SCFG_Clock9);
file->Var16(&SCFG_Clock7);
file->VarArray(&SCFG_EXT[0], sizeof(u32)*2);
file->Var32(&SCFG_MC);
file->Var16(&SCFG_RST);
//file->VarArray(ARM9iBIOS, 0x10000);
//file->VarArray(ARM7iBIOS, 0x10000);
if (file->Saving)
{
file->VarArray(&MBK[0][0], sizeof(u32)*8);
file->VarArray(&MBK[1][5], sizeof(u32)*3);
file->Var32(&MBK[0][8]);
}
else
{
Set_SCFG_Clock9(SCFG_Clock9);
Set_SCFG_MC(SCFG_MC);
DSi_DSP::SetRstLine(SCFG_RST & 0x0001);
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
file->VarArray(&mbk, sizeof(u32)*12);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
mbk[11] &= 0x00FFFF0F;
MBK[0][8] = mbk[11];
MBK[1][8] = mbk[11];
}
for (int i = 0; i < 8; i++)
NDMAs[i]->DoSavestate(file);
DSi_AES::DoSavestate(file);
DSi_CamModule::DoSavestate(file);
DSi_DSP::DoSavestate(file);
DSi_I2C::DoSavestate(file);
SDMMC->DoSavestate(file);
SDIO->DoSavestate(file);
}
void SetCartInserted(bool inserted)
{
if (inserted)
SCFG_MC &= ~1;
else
SCFG_MC |= 1;
}
void DecryptModcryptArea(u32 offset, u32 size, u8* iv)
{
AES_ctx ctx;
u8 key[16];
u8 tmp[16];
if ((offset == 0) || (size == 0))
return;
if ((NDSCart::Header.DSiCryptoFlags & (1<<4)) ||
(NDSCart::Header.AppFlags & (1<<7)))
{
// dev key
memcpy(key, &NDSCart::CartROM[0], 16);
}
else
{
u8 keyX[16], keyY[16];
*(u32*)&keyX[0] = 0x746E694E;
*(u32*)&keyX[4] = 0x6F646E65;
keyX[8] = NDSCart::Header.GameCode[0];
keyX[9] = NDSCart::Header.GameCode[1];
keyX[10] = NDSCart::Header.GameCode[2];
keyX[11] = NDSCart::Header.GameCode[3];
keyX[12] = NDSCart::Header.GameCode[3];
keyX[13] = NDSCart::Header.GameCode[2];
keyX[14] = NDSCart::Header.GameCode[1];
keyX[15] = NDSCart::Header.GameCode[0];
memcpy(keyY, NDSCart::Header.DSiARM9iHash, 16);
DSi_AES::DeriveNormalKey(keyX, keyY, tmp);
}
DSi_AES::Swap16(key, tmp);
DSi_AES::Swap16(tmp, iv);
AES_init_ctx_iv(&ctx, key, tmp);
// find a matching binary area
u32 binaryaddr, binarysize;
u32 roundedsize = (size + 0xF) & ~0xF;
// CHECKME: GBAtek says the modcrypt area should be the same size, or bigger,
// than the binary area being considered
// but I have seen modcrypt areas smaller than the ARM9i binary
#define BINARY_GOOD(name) \
((offset >= NDSCart::Header.name##ROMOffset) && \
(offset+roundedsize) <= (NDSCart::Header.name##ROMOffset + ((NDSCart::Header.name##Size + 0xF) & ~0xF)))
if (BINARY_GOOD(ARM9))
{
binaryaddr = NDSCart::Header.ARM9RAMAddress;
binarysize = NDSCart::Header.ARM9Size;
}
else if (BINARY_GOOD(ARM7))
{
binaryaddr = NDSCart::Header.ARM7RAMAddress;
binarysize = NDSCart::Header.ARM7Size;
}
else if (BINARY_GOOD(DSiARM9i))
{
binaryaddr = NDSCart::Header.DSiARM9iRAMAddress;
binarysize = NDSCart::Header.DSiARM9iSize;
}
else if (BINARY_GOOD(DSiARM7i))
{
binaryaddr = NDSCart::Header.DSiARM7iRAMAddress;
binarysize = NDSCart::Header.DSiARM7iSize;
}
else
return;
#undef BINARY_GOOD
for (u32 i = 0; i < size; i+=16)
{
u8 data[16];
*(u32*)&data[0] = ARM9Read32(binaryaddr+i);
*(u32*)&data[4] = ARM9Read32(binaryaddr+i+4);
*(u32*)&data[8] = ARM9Read32(binaryaddr+i+8);
*(u32*)&data[12] = ARM9Read32(binaryaddr+i+12);
DSi_AES::Swap16(tmp, data);
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
DSi_AES::Swap16(data, tmp);
ARM9Write32(binaryaddr+i, *(u32*)&data[0]);
ARM9Write32(binaryaddr+i+4, *(u32*)&data[4]);
ARM9Write32(binaryaddr+i+8, *(u32*)&data[8]);
ARM9Write32(binaryaddr+i+12, *(u32*)&data[12]);
}
}
void SetupDirectBoot()
{
bool dsmode = false;
// TODO: add controls for forcing DS or DSi mode?
if (!(NDSCart::Header.UnitCode & 0x02))
dsmode = true;
if (dsmode)
{
SCFG_BIOS = 0x0303;
// no NWRAM Mapping
for (int i = 0; i < 4; i++)
MapNWRAM_A(i, 0);
for (int i = 0; i < 8; i++)
MapNWRAM_B(i, 0);
for (int i = 0; i < 8; i++)
MapNWRAM_C(i, 0);
// No NWRAM Window
for (int i = 0; i < 3; i++)
{
MapNWRAMRange(0, i, 0);
MapNWRAMRange(1, i, 0);
}
NDS::MapSharedWRAM(3);
DSi_SPI_TSC::SetMode(0x00);
Set_SCFG_Clock9(0x0000);
}
else
{
SCFG_BIOS = 0x0101;
// WRAM mapping
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
memcpy(mbk, &NDSCart::CartROM[0x180], 12*4);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
MBK[0][8] = mbk[11] & 0x00FFFF0F;
MBK[1][8] = mbk[11] & 0x00FFFF0F;
NDS::MapSharedWRAM(mbk[11] >> 24);
if (!(NDSCart::Header.AppFlags & (1<<0)))
DSi_SPI_TSC::SetMode(0x00);
}
// setup main RAM data
// TODO: verify what changes when loading a DS-mode ROM
if (dsmode)
{
for (u32 i = 0; i < 0x170; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[i];
ARM9Write32(0x027FFE00+i, tmp);
}
ARM9Write32(0x027FF800, NDSCart::CartID);
ARM9Write32(0x027FF804, NDSCart::CartID);
ARM9Write16(0x027FF808, NDSCart::Header.HeaderCRC16);
ARM9Write16(0x027FF80A, NDSCart::Header.SecureAreaCRC16);
ARM9Write16(0x027FF850, 0x5835);
ARM9Write32(0x027FFC00, NDSCart::CartID);
ARM9Write32(0x027FFC04, NDSCart::CartID);
ARM9Write16(0x027FFC08, NDSCart::Header.HeaderCRC16);
ARM9Write16(0x027FFC0A, NDSCart::Header.SecureAreaCRC16);
ARM9Write16(0x027FFC10, 0x5835);
ARM9Write16(0x027FFC30, 0xFFFF);
ARM9Write16(0x027FFC40, 0x0001);
}
else
{
// CHECKME: some of these are 'only for NDS ROM', presumably
// only for when loading a cart? (as opposed to DSiWare)
for (u32 i = 0; i < 0x160; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[i];
ARM9Write32(0x02FFFA80+i, tmp);
ARM9Write32(0x02FFFE00+i, tmp);
}
for (u32 i = 0; i < 0x1000; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[i];
ARM9Write32(0x02FFC000+i, tmp);
ARM9Write32(0x02FFE000+i, tmp);
}
if (DSi_NAND::Init(&DSi::ARM7iBIOS[0x8308]))
{
u8 userdata[0x1B0];
DSi_NAND::ReadUserData(userdata);
for (u32 i = 0; i < 0x128; i+=4)
ARM9Write32(0x02000400+i, *(u32*)&userdata[0x88+i]);
u8 hwinfoS[0xA4];
u8 hwinfoN[0x9C];
DSi_NAND::ReadHardwareInfo(hwinfoS, hwinfoN);
for (u32 i = 0; i < 0x14; i+=4)
ARM9Write32(0x02000600+i, *(u32*)&hwinfoN[0x88+i]);
for (u32 i = 0; i < 0x18; i+=4)
ARM9Write32(0x02FFFD68+i, *(u32*)&hwinfoS[0x88+i]);
DSi_NAND::DeInit();
}
u8 nwifiver = SPI_Firmware::GetNWifiVersion();
ARM9Write8(0x020005E0, nwifiver);
// TODO: these should be taken from the wifi firmware in NAND
// but, hey, this works too.
if (nwifiver == 1)
{
ARM9Write16(0x020005E2, 0xB57E);
ARM9Write32(0x020005E4, 0x00500400);
ARM9Write32(0x020005E8, 0x00500000);
ARM9Write32(0x020005EC, 0x0002E000);
}
else
{
ARM9Write16(0x020005E2, 0x5BCA);
ARM9Write32(0x020005E4, 0x00520000);
ARM9Write32(0x020005E8, 0x00520000);
ARM9Write32(0x020005EC, 0x00020000);
}
// TODO: the shit at 02FFD7B0..02FFDC00
// and some other extra shit?
ARM9Write32(0x02FFFC00, NDSCart::CartID);
ARM9Write16(0x02FFFC40, 0x0001); // boot indicator
ARM9Write8(0x02FFFDFA, DSi_BPTWL::GetBootFlag() | 0x80);
ARM9Write8(0x02FFFDFB, 0x01);
}
// TODO: for DS-mode ROMs, switch RAM size here
u32 arm9start = 0;
// load the ARM9 secure area
if (NDSCart::Header.ARM9ROMOffset >= 0x4000 && NDSCart::Header.ARM9ROMOffset < 0x8000)
{
u8 securearea[0x800];
NDSCart::DecryptSecureArea(securearea);
for (u32 i = 0; i < 0x800; i+=4)
{
ARM9Write32(NDSCart::Header.ARM9RAMAddress+i, *(u32*)&securearea[i]);
arm9start += 4;
}
}
for (u32 i = arm9start; i < NDSCart::Header.ARM9Size; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[NDSCart::Header.ARM9ROMOffset+i];
ARM9Write32(NDSCart::Header.ARM9RAMAddress+i, tmp);
}
for (u32 i = 0; i < NDSCart::Header.ARM7Size; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[NDSCart::Header.ARM7ROMOffset+i];
ARM7Write32(NDSCart::Header.ARM7RAMAddress+i, tmp);
}
if ((!dsmode) && (NDSCart::Header.DSiCryptoFlags & (1<<0)))
{
// load DSi-specific regions
for (u32 i = 0; i < NDSCart::Header.DSiARM9iSize; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[NDSCart::Header.DSiARM9iROMOffset+i];
ARM9Write32(NDSCart::Header.DSiARM9iRAMAddress+i, tmp);
}
for (u32 i = 0; i < NDSCart::Header.DSiARM7iSize; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[NDSCart::Header.DSiARM7iROMOffset+i];
ARM7Write32(NDSCart::Header.DSiARM7iRAMAddress+i, tmp);
}
// decrypt any modcrypt areas
if (NDSCart::Header.DSiCryptoFlags & (1<<1))
{
DecryptModcryptArea(NDSCart::Header.DSiModcrypt1Offset,
NDSCart::Header.DSiModcrypt1Size,
NDSCart::Header.DSiARM9Hash);
DecryptModcryptArea(NDSCart::Header.DSiModcrypt2Offset,
NDSCart::Header.DSiModcrypt2Size,
NDSCart::Header.DSiARM7Hash);
}
}
NDS::ARM7BIOSProt = 0x20;
SPI_Firmware::SetupDirectBoot(true);
NDS::ARM9->CP15Write(0x100, 0x00056078);
NDS::ARM9->CP15Write(0x200, 0x0000004A);
NDS::ARM9->CP15Write(0x201, 0x0000004A);
NDS::ARM9->CP15Write(0x300, 0x0000000A);
NDS::ARM9->CP15Write(0x502, 0x15111011);
NDS::ARM9->CP15Write(0x503, 0x05101011);
NDS::ARM9->CP15Write(0x600, 0x04000033);
NDS::ARM9->CP15Write(0x601, 0x04000033);
NDS::ARM9->CP15Write(0x610, 0x02000031);
NDS::ARM9->CP15Write(0x611, 0x02000031);
NDS::ARM9->CP15Write(0x620, 0x00000000);
NDS::ARM9->CP15Write(0x621, 0x00000000);
NDS::ARM9->CP15Write(0x630, 0x08000033);
NDS::ARM9->CP15Write(0x631, 0x08000033);
NDS::ARM9->CP15Write(0x640, 0x0E00001B);
NDS::ARM9->CP15Write(0x641, 0x0E00001B);
NDS::ARM9->CP15Write(0x650, 0x00000000);
NDS::ARM9->CP15Write(0x651, 0x00000000);
NDS::ARM9->CP15Write(0x660, 0xFFFF001D);
NDS::ARM9->CP15Write(0x661, 0xFFFF001D);
NDS::ARM9->CP15Write(0x670, 0x02FFC01B);
NDS::ARM9->CP15Write(0x671, 0x02FFC01B);
NDS::ARM9->CP15Write(0x910, 0x0E00000A);
NDS::ARM9->CP15Write(0x911, 0x00000020);
}
void SoftReset()
{
// TODO: check exactly what is reset
// presumably, main RAM isn't reset, since the DSi can be told
// to boot a specific title this way
// BPTWL state wouldn't be reset either since BPTWL[0x70] is
// the warmboot flag
// also, BPTWL[0x70] could be abused to quickly boot specific titles
#ifdef JIT_ENABLED
ARMJIT_Memory::Reset();
ARMJIT::CheckAndInvalidateITCM();
#endif
NDS::ARM9->Reset();
NDS::ARM7->Reset();
NDS::ARM9->CP15Reset();
NDS::MapSharedWRAM(3);
// TODO: does the DSP get reset? NWRAM doesn't, so I'm assuming no
// *HOWEVER*, the bootrom (which does get rerun) does remap NWRAM, and thus
// the DSP most likely gets reset
DSi_DSP::Reset();
SDMMC->CloseHandles();
SDIO->CloseHandles();
LoadNAND();
SDMMC->Reset();
SDIO->Reset();
DSi_AES::Reset();
SCFG_BIOS = 0x0101; // TODO: should be zero when booting from BIOS
SCFG_Clock9 = 0x0187; // CHECKME
SCFG_Clock7 = 0x0187;
SCFG_EXT[0] = 0x8307F100;
SCFG_EXT[1] = 0x93FFFB06;
SCFG_MC = 0x0010;//0x0011;
// TODO: is this actually reset?
SCFG_RST = 0;
DSi_DSP::SetRstLine(false);
// LCD init flag
GPU::DispStat[0] |= (1<<6);
GPU::DispStat[1] |= (1<<6);
}
bool LoadBIOS()
{
FILE* f;
u32 i;
memset(ARM9iBIOS, 0, 0x10000);
memset(ARM7iBIOS, 0, 0x10000);
f = Platform::OpenLocalFile(Platform::GetConfigString(Platform::DSi_BIOS9Path), "rb");
if (!f)
{
printf("ARM9i BIOS not found\n");
for (i = 0; i < 16; i++)
((u32*)ARM9iBIOS)[i] = 0xE7FFDEFF;
}
else
{
fseek(f, 0, SEEK_SET);
fread(ARM9iBIOS, 0x10000, 1, f);
printf("ARM9i BIOS loaded\n");
fclose(f);
}
f = Platform::OpenLocalFile(Platform::GetConfigString(Platform::DSi_BIOS7Path), "rb");
if (!f)
{
printf("ARM7i BIOS not found\n");
for (i = 0; i < 16; i++)
((u32*)ARM7iBIOS)[i] = 0xE7FFDEFF;
}
else
{
// TODO: check if the first 32 bytes are crapoed
fseek(f, 0, SEEK_SET);
fread(ARM7iBIOS, 0x10000, 1, f);
printf("ARM7i BIOS loaded\n");
fclose(f);
}
// herp
*(u32*)&ARM9iBIOS[0] = 0xEAFFFFFE;
*(u32*)&ARM7iBIOS[0] = 0xEAFFFFFE;
// TODO!!!!
// hax the upper 32K out of the goddamn DSi
return true;
}
bool LoadNAND()
{
printf("Loading DSi NAND\n");
if (!DSi_NAND::Init(&DSi::ARM7iBIOS[0x8308]))
{
printf("Failed to load DSi NAND\n");
return false;
}
FILE* nand = DSi_NAND::GetFile();
// Make sure NWRAM is accessible.
// The Bits are set to the startup values in Reset() and we might
// still have them on default (0) or some bits cleared by the previous
// run.
SCFG_EXT[0] |= (1 << 25);
SCFG_EXT[1] |= (1 << 25);
memset(NWRAM_A, 0, NWRAMSize);
memset(NWRAM_B, 0, NWRAMSize);
memset(NWRAM_C, 0, NWRAMSize);
memset(MBK, 0, sizeof(MBK));
memset(NWRAMMap_A, 0, sizeof(NWRAMMap_A));
memset(NWRAMMap_B, 0, sizeof(NWRAMMap_B));
memset(NWRAMMap_C, 0, sizeof(NWRAMMap_C));
memset(NWRAMStart, 0, sizeof(NWRAMStart));
memset(NWRAMEnd, 0, sizeof(NWRAMEnd));
memset(NWRAMMask, 0, sizeof(NWRAMMask));
u32 bootparams[8];
fseek(nand, 0x220, SEEK_SET);
fread(bootparams, 4, 8, nand);
printf("ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
printf("ARM7: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
bootparams[4], bootparams[5], bootparams[6], bootparams[7]);
// read and apply new-WRAM settings
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
fseek(nand, 0x380, SEEK_SET);
fread(mbk, 4, 12, nand);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
// TODO: find out why it is 0xFF000000
mbk[11] &= 0x00FFFF0F;
MBK[0][8] = mbk[11];
MBK[1][8] = mbk[11];
// load boot2 binaries
AES_ctx ctx;
const u8 boot2key[16] = {0xAD, 0x34, 0xEC, 0xF9, 0x62, 0x6E, 0xC2, 0x3A, 0xF6, 0xB4, 0x6C, 0x00, 0x80, 0x80, 0xEE, 0x98};
u8 boot2iv[16];
u8 tmp[16];
u32 dstaddr;
*(u32*)&tmp[0] = bootparams[3];
*(u32*)&tmp[4] = -bootparams[3];
*(u32*)&tmp[8] = ~bootparams[3];
*(u32*)&tmp[12] = 0;
for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
fseek(nand, bootparams[0], SEEK_SET);
dstaddr = bootparams[2];
for (u32 i = 0; i < bootparams[3]; i += 16)
{
u8 data[16];
fread(data, 16, 1, nand);
for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
ARM9Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
ARM9Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
ARM9Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
ARM9Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
}
*(u32*)&tmp[0] = bootparams[7];
*(u32*)&tmp[4] = -bootparams[7];
*(u32*)&tmp[8] = ~bootparams[7];
*(u32*)&tmp[12] = 0;
for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
fseek(nand, bootparams[4], SEEK_SET);
dstaddr = bootparams[6];
for (u32 i = 0; i < bootparams[7]; i += 16)
{
u8 data[16];
fread(data, 16, 1, nand);
for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
ARM7Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
ARM7Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
ARM7Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
ARM7Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
}
#define printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); }
#define printhex_rev(str, size) { for (int z = (size)-1; z >= 0; z--) printf("%02X", (str)[z]); printf("\n"); }
DSi_NAND::GetIDs(eMMC_CID, ConsoleID);
printf("eMMC CID: "); printhex(eMMC_CID, 16);
printf("Console ID: %" PRIx64 "\n", ConsoleID);
u32 eaddr = 0x03FFE6E4;
ARM7Write32(eaddr+0x00, *(u32*)&eMMC_CID[0]);
ARM7Write32(eaddr+0x04, *(u32*)&eMMC_CID[4]);
ARM7Write32(eaddr+0x08, *(u32*)&eMMC_CID[8]);
ARM7Write32(eaddr+0x0C, *(u32*)&eMMC_CID[12]);
ARM7Write16(eaddr+0x2C, 0x0001);
ARM7Write16(eaddr+0x2E, 0x0001);
ARM7Write16(eaddr+0x3C, 0x0100);
ARM7Write16(eaddr+0x3E, 0x40E0);
ARM7Write16(eaddr+0x42, 0x0001);
memcpy(&NDS::ARM9->ITCM[0x4400], &ARM9iBIOS[0x87F4], 0x400);
memcpy(&NDS::ARM9->ITCM[0x4800], &ARM9iBIOS[0x9920], 0x80);
memcpy(&NDS::ARM9->ITCM[0x4894], &ARM9iBIOS[0x99A0], 0x1048);
memcpy(&NDS::ARM9->ITCM[0x58DC], &ARM9iBIOS[0xA9E8], 0x1048);
u8 ARM7Init[0x3C00];
memset(ARM7Init, 0, 0x3C00);
memcpy(&ARM7Init[0x0000], &ARM7iBIOS[0x8188], 0x200);
memcpy(&ARM7Init[0x0200], &ARM7iBIOS[0xB5D8], 0x40);
memcpy(&ARM7Init[0x0254], &ARM7iBIOS[0xC6D0], 0x1048);
memcpy(&ARM7Init[0x129C], &ARM7iBIOS[0xD718], 0x1048);
for (u32 i = 0; i < 0x3C00; i+=4)
ARM7Write32(0x03FFC400+i, *(u32*)&ARM7Init[i]);
// repoint the CPUs to the boot2 binaries
NDS::ARM9->JumpTo(bootparams[2]);
NDS::ARM7->JumpTo(bootparams[6]);
DSi_NAND::PatchUserData();
DSi_NAND::DeInit();
return true;
}
void RunNDMAs(u32 cpu)
{
// TODO: round-robin mode (requires DMA channels to have a subblock delay set)
if (cpu == 0)
{
if (NDS::ARM9Timestamp >= NDS::ARM9Target) return;
if (!(NDS::CPUStop & 0x80000000)) NDMAs[0]->Run();
if (!(NDS::CPUStop & 0x80000000)) NDMAs[1]->Run();
if (!(NDS::CPUStop & 0x80000000)) NDMAs[2]->Run();
if (!(NDS::CPUStop & 0x80000000)) NDMAs[3]->Run();
}
else
{
if (NDS::ARM7Timestamp >= NDS::ARM7Target) return;
NDMAs[4]->Run();
NDMAs[5]->Run();
NDMAs[6]->Run();
NDMAs[7]->Run();
}
}
void StallNDMAs()
{
// TODO
}
bool NDMAsInMode(u32 cpu, u32 mode)
{
cpu <<= 2;
if (NDMAs[cpu+0]->IsInMode(mode)) return true;
if (NDMAs[cpu+1]->IsInMode(mode)) return true;
if (NDMAs[cpu+2]->IsInMode(mode)) return true;
if (NDMAs[cpu+3]->IsInMode(mode)) return true;
return false;
}
bool NDMAsRunning(u32 cpu)
{
cpu <<= 2;
if (NDMAs[cpu+0]->IsRunning()) return true;
if (NDMAs[cpu+1]->IsRunning()) return true;
if (NDMAs[cpu+2]->IsRunning()) return true;
if (NDMAs[cpu+3]->IsRunning()) return true;
return false;
}
void CheckNDMAs(u32 cpu, u32 mode)
{
cpu <<= 2;
NDMAs[cpu+0]->StartIfNeeded(mode);
NDMAs[cpu+1]->StartIfNeeded(mode);
NDMAs[cpu+2]->StartIfNeeded(mode);
NDMAs[cpu+3]->StartIfNeeded(mode);
}
void StopNDMAs(u32 cpu, u32 mode)
{
cpu <<= 2;
NDMAs[cpu+0]->StopIfNeeded(mode);
NDMAs[cpu+1]->StopIfNeeded(mode);
NDMAs[cpu+2]->StopIfNeeded(mode);
NDMAs[cpu+3]->StopIfNeeded(mode);
}
// new WRAM mapping
// TODO: find out what happens upon overlapping slots!!
void MapNWRAM_A(u32 num, u8 val)
{
// NWRAM Bank A does not allow all bits to be set