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Starred repositories

3 results for source starred repositories written in Verilog
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Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Verilog 284 47 Updated Apr 11, 2023

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Verilog 83 18 Updated Nov 6, 2023

This is the verilog code for the various FPGA in the OpenHPSDR Radios

Verilog 25 18 Updated Jan 16, 2025