Patent Timesaving Automatic Helpful Apparatus

Test suites on FIRRTL specifications

Python-based Hardware Design Processing Toolkit for Verilog HDL

Utopia: a High-Level Synthesis framework

Verilog designs and their synthesized netlists

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

RISC-V nML is a specification of ISA RISC-V in nML architecture decription language.

Test suites on Verilog and SystemVerilog standards

Fork for the STACCATO project of University of Michigan

Automatic markdown to docx converter that follows the Ispras proceedings design requirements

C++ parsing library for simple formats used in logic synthesis and formal verification

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Inverse Discrete Cosine Transform (IDCT) algorithm implementations are written in languages for High-Level Synthesis (HLS) and Hardware Construction (HC) tools.

MicroTESK: Specification-Based Framework for Developing Test Program Generators

ILAng documentation

Benchmarks for Yosys development

Collection of test cases for Yosys

MicroTESK: Specification-Based Framework for Developing Test Program Generators

Collection of digital hardware modules & projects (benchmarks)

RISC-V Architecture Verification Suite (AVS)