FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

BaseJump STL: A Standard Template Library for SystemVerilog

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Project F brings FPGAs to life with exciting open-source designs you can build on.

A hardware component library developed with ROHD.

IBM Analog Hardware Acceleration Kit

Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

32-bit RISC-V CPU in ~800 lines of C89

🤘 TT-NN operator library, and TT-Metalium low level kernel programming model.

A powerful Smart Watch based on STM32, FreeRTOS, LVGL.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

Chisel: A Modern Hardware Design Language

nextpnr portable FPGA place and route tool

LiteX boards files

VHDL 2008/93/87 simulator

A minimal GPU design in Verilog to learn how GPUs work from the ground up

BlackParrot on Zynq

mflowgen -- A Modular ASIC/FPGA Flow Generator

Hardware Description Languages

Simple software tools for encoding and decoding dumps of NAND memory chips using implemented error correcting codes (ECC)

Learning FPGA, yosys, nextpnr, and RISC-V