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[X86] More additions to the load folding tables based on the autogenerated tables.
Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334898 91177308-0d34-0410-b5e6-96231b3b80d8
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6 files changed

+820
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‎lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 22 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1959,7 +1959,7 @@ multiclass WriteFVarBlendask<bits<8> opc, string OpcodeStr,
19591959
(ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
19601960
!strconcat(OpcodeStr,
19611961
"\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1962-
[]>, EVEX_4V, EVEX_KZ, Sched<[sched]>;
1962+
[]>, EVEX_4V, EVEX_KZ, Sched<[sched]>, NotMemoryFoldable;
19631963
let mayLoad = 1 in {
19641964
def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
19651965
(ins _.RC:$src1, _.MemOp:$src2),
@@ -1978,7 +1978,7 @@ multiclass WriteFVarBlendask<bits<8> opc, string OpcodeStr,
19781978
!strconcat(OpcodeStr,
19791979
"\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
19801980
[]>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>,
1981-
Sched<[sched.Folded, ReadAfterLd]>;
1981+
Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable;
19821982
}
19831983
}
19841984
}
@@ -1999,7 +1999,7 @@ multiclass WriteFVarBlendask_rmb<bits<8> opc, string OpcodeStr,
19991999
"\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}} {z}|",
20002000
"$dst {${mask}} {z}, $src1, ${src2}", _.BroadcastStr, "}"), []>,
20012001
EVEX_4V, EVEX_KZ, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>,
2002-
Sched<[sched.Folded, ReadAfterLd]>;
2002+
Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable;
20032003

20042004
def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
20052005
(ins _.RC:$src1, _.ScalarMemOp:$src2),
@@ -2097,22 +2097,22 @@ multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd,
20972097
(ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
20982098
"vcmp"#_.Suffix,
20992099
"$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V,
2100-
Sched<[sched]>;
2100+
Sched<[sched]>, NotMemoryFoldable;
21012101
let mayLoad = 1 in
21022102
defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
21032103
(outs _.KRC:$dst),
21042104
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
21052105
"vcmp"#_.Suffix,
21062106
"$cc, $src2, $src1", "$src1, $src2, $cc">,
21072107
EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>,
2108-
Sched<[sched.Folded, ReadAfterLd]>;
2108+
Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable;
21092109

21102110
defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
21112111
(outs _.KRC:$dst),
21122112
(ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
21132113
"vcmp"#_.Suffix,
21142114
"$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc">,
2115-
EVEX_4V, EVEX_B, Sched<[sched]>;
2115+
EVEX_4V, EVEX_B, Sched<[sched]>, NotMemoryFoldable;
21162116
}// let isAsmParserOnly = 1, hasSideEffects = 0
21172117

21182118
let isCodeGenOnly = 1 in {
@@ -2334,28 +2334,29 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
23342334
(outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
23352335
!strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
23362336
"$dst, $src1, $src2, $cc}"), []>,
2337-
EVEX_4V, Sched<[sched]>;
2337+
EVEX_4V, Sched<[sched]>, NotMemoryFoldable;
23382338
let mayLoad = 1 in
23392339
def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
23402340
(outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
23412341
!strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
23422342
"$dst, $src1, $src2, $cc}"), []>,
2343-
EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>;
2343+
EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable;
23442344
def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
23452345
(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
23462346
u8imm:$cc),
23472347
!strconcat("vpcmp", Suffix,
23482348
"\t{$cc, $src2, $src1, $dst {${mask}}|",
23492349
"$dst {${mask}}, $src1, $src2, $cc}"), []>,
2350-
EVEX_4V, EVEX_K, Sched<[sched]>;
2350+
EVEX_4V, EVEX_K, Sched<[sched]>, NotMemoryFoldable;
23512351
let mayLoad = 1 in
23522352
def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
23532353
(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
23542354
u8imm:$cc),
23552355
!strconcat("vpcmp", Suffix,
23562356
"\t{$cc, $src2, $src1, $dst {${mask}}|",
23572357
"$dst {${mask}}, $src1, $src2, $cc}"), []>,
2358-
EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>;
2358+
EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>,
2359+
NotMemoryFoldable;
23592360
}
23602361

23612362
def : Pat<(OpNode (bitconvert (_.LdFrag addr:$src2)),
@@ -2404,14 +2405,16 @@ multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
24042405
!strconcat("vpcmp", Suffix,
24052406
"\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
24062407
"$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"), []>,
2407-
EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>;
2408+
EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>,
2409+
NotMemoryFoldable;
24082410
def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
24092411
(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
24102412
_.ScalarMemOp:$src2, u8imm:$cc),
24112413
!strconcat("vpcmp", Suffix,
24122414
"\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
24132415
"$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"), []>,
2414-
EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>;
2416+
EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>,
2417+
NotMemoryFoldable;
24152418
}
24162419

24172420
def : Pat<(OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
@@ -2523,23 +2526,25 @@ multiclass avx512_vcmp_common<X86FoldableSchedWrite sched, X86VectorVTInfo _,
25232526
(ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
25242527
"vcmp"#_.Suffix,
25252528
"$cc, $src2, $src1", "$src1, $src2, $cc">,
2526-
Sched<[sched]>;
2529+
Sched<[sched]>, NotMemoryFoldable;
25272530

25282531
let mayLoad = 1 in {
25292532
defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
25302533
(outs _.KRC:$dst),
25312534
(ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
25322535
"vcmp"#_.Suffix,
25332536
"$cc, $src2, $src1", "$src1, $src2, $cc">,
2534-
Sched<[sched.Folded, ReadAfterLd]>;
2537+
Sched<[sched.Folded, ReadAfterLd]>,
2538+
NotMemoryFoldable;
25352539

25362540
defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
25372541
(outs _.KRC:$dst),
25382542
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
25392543
"vcmp"#_.Suffix,
25402544
"$cc, ${src2}"##_.BroadcastStr##", $src1",
25412545
"$src1, ${src2}"##_.BroadcastStr##", $cc">,
2542-
EVEX_B, Sched<[sched.Folded, ReadAfterLd]>;
2546+
EVEX_B, Sched<[sched.Folded, ReadAfterLd]>,
2547+
NotMemoryFoldable;
25432548
}
25442549
}
25452550

@@ -2589,7 +2594,7 @@ multiclass avx512_vcmp_sae<X86FoldableSchedWrite sched, X86VectorVTInfo _> {
25892594
"vcmp"#_.Suffix,
25902595
"$cc, {sae}, $src2, $src1",
25912596
"$src1, $src2, {sae}, $cc">,
2592-
EVEX_B, Sched<[sched]>;
2597+
EVEX_B, Sched<[sched]>, NotMemoryFoldable;
25932598
}
25942599
}
25952600

@@ -6289,7 +6294,7 @@ def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
62896294
(ins VR128X:$src1, VR128X:$src2),
62906295
"vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
62916296
[(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))]>,
6292-
Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V;
6297+
Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V, NotMemoryFoldable;
62936298

62946299
//===----------------------------------------------------------------------===//
62956300
// VMOVHPS/PD VMOVLPS Instructions

‎lib/Target/X86/X86InstrExtension.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -95,17 +95,17 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
9595
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
9696
def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
9797
"movs{ww|x}\t{$src, $dst|$dst, $src}",
98-
[]>, TB, OpSize16, Sched<[WriteALU]>;
98+
[]>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
9999
def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
100100
"movz{ww|x}\t{$src, $dst|$dst, $src}",
101-
[]>, TB, OpSize16, Sched<[WriteALU]>;
101+
[]>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable;
102102
let mayLoad = 1 in {
103103
def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
104104
"movs{ww|x}\t{$src, $dst|$dst, $src}",
105-
[]>, OpSize16, TB, Sched<[WriteALULd]>;
105+
[]>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable;
106106
def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
107107
"movz{ww|x}\t{$src, $dst|$dst, $src}",
108-
[]>, TB, OpSize16, Sched<[WriteALULd]>;
108+
[]>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable;
109109
} // mayLoad = 1
110110
} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
111111

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