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AMDGPU/GlobalISel: RegBankSelect tbuffer load/store
These have the same operand structure as the non-t buffer operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372296 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1649,14 +1649,18 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
16491649
}
16501650
case Intrinsic::amdgcn_raw_buffer_load:
16511651
case Intrinsic::amdgcn_raw_buffer_load_format:
1652+
case Intrinsic::amdgcn_raw_tbuffer_load:
16521653
case Intrinsic::amdgcn_raw_buffer_store:
1653-
case Intrinsic::amdgcn_raw_buffer_store_format: {
1654+
case Intrinsic::amdgcn_raw_buffer_store_format:
1655+
case Intrinsic::amdgcn_raw_tbuffer_store: {
16541656
applyDefaultMapping(OpdMapper);
16551657
executeInWaterfallLoop(MI, MRI, {2, 4});
16561658
return;
16571659
}
16581660
case Intrinsic::amdgcn_struct_buffer_load:
1659-
case Intrinsic::amdgcn_struct_buffer_store: {
1661+
case Intrinsic::amdgcn_struct_buffer_store:
1662+
case Intrinsic::amdgcn_struct_tbuffer_load:
1663+
case Intrinsic::amdgcn_struct_tbuffer_store: {
16601664
applyDefaultMapping(OpdMapper);
16611665
executeInWaterfallLoop(MI, MRI, {2, 5});
16621666
return;
@@ -2602,7 +2606,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
26022606
OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
26032607
break;
26042608
}
2605-
case Intrinsic::amdgcn_raw_buffer_load: {
2609+
case Intrinsic::amdgcn_raw_buffer_load:
2610+
case Intrinsic::amdgcn_raw_tbuffer_load: {
26062611
// FIXME: Should make intrinsic ID the last operand of the instruction,
26072612
// then this would be the same as store
26082613
OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
@@ -2612,22 +2617,25 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
26122617
break;
26132618
}
26142619
case Intrinsic::amdgcn_raw_buffer_store:
2615-
case Intrinsic::amdgcn_raw_buffer_store_format: {
2620+
case Intrinsic::amdgcn_raw_buffer_store_format:
2621+
case Intrinsic::amdgcn_raw_tbuffer_store: {
26162622
OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
26172623
OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
26182624
OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
26192625
OpdsMapping[4] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
26202626
break;
26212627
}
2622-
case Intrinsic::amdgcn_struct_buffer_load: {
2628+
case Intrinsic::amdgcn_struct_buffer_load:
2629+
case Intrinsic::amdgcn_struct_tbuffer_load: {
26232630
OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
26242631
OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
26252632
OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
26262633
OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
26272634
OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
26282635
break;
26292636
}
2630-
case Intrinsic::amdgcn_struct_buffer_store: {
2637+
case Intrinsic::amdgcn_struct_buffer_store:
2638+
case Intrinsic::amdgcn_struct_tbuffer_store: {
26312639
OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
26322640
OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
26332641
OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);

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