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If a function needs a frame pointer, but r11 (aka fp) has not been used,
remove it from the list of unspilled registers. Otherwise the following attempt to keep the stack aligned by picking an extra GPR register to spill will not work as it picks up r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208129 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent d474181 commit b84f890

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6 files changed

+42
-36
lines changed

6 files changed

+42
-36
lines changed

‎lib/Target/ARM/ARMFrameLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1529,6 +1529,10 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
15291529

15301530
if (hasFP(MF)) {
15311531
MRI.setPhysRegUsed(FramePtr);
1532+
auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1533+
FramePtr);
1534+
if (FPPos != UnspilledCS1GPRs.end())
1535+
UnspilledCS1GPRs.erase(FPPos);
15321536
NumGPRSpills++;
15331537
}
15341538

‎test/CodeGen/ARM/debug-frame-vararg.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -75,12 +75,13 @@
7575
; CHECK-FP-ELIM: .cfi_startproc
7676
; CHECK-FP-ELIM: sub sp, sp, #16
7777
; CHECK-FP-ELIM: .cfi_def_cfa_offset 16
78-
; CHECK-FP-ELIM: push {r4, r11, lr}
79-
; CHECK-FP-ELIM: .cfi_def_cfa_offset 28
78+
; CHECK-FP-ELIM: push {r4, r10, r11, lr}
79+
; CHECK-FP-ELIM: .cfi_def_cfa_offset 32
8080
; CHECK-FP-ELIM: .cfi_offset lr, -20
8181
; CHECK-FP-ELIM: .cfi_offset r11, -24
82-
; CHECK-FP-ELIM: .cfi_offset r4, -28
83-
; CHECK-FP-ELIM: add r11, sp, #4
82+
; CHECK-FP-ELIM: .cfi_offset r10, -28
83+
; CHECK-FP-ELIM: .cfi_offset r4, -32
84+
; CHECK-FP-ELIM: add r11, sp, #8
8485
; CHECK-FP-ELIM: .cfi_def_cfa r11, 24
8586

8687
; CHECK-THUMB-FP-LABEL: sum

‎test/CodeGen/ARM/debug-frame.ll‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -201,20 +201,21 @@ declare void @_ZSt9terminatev()
201201

202202
; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
203203
; CHECK-V7-FP: .cfi_startproc
204-
; CHECK-V7-FP: push {r4, r11, lr}
205-
; CHECK-V7-FP: .cfi_def_cfa_offset 12
204+
; CHECK-V7-FP: push {r4, r10, r11, lr}
205+
; CHECK-V7-FP: .cfi_def_cfa_offset 16
206206
; CHECK-V7-FP: .cfi_offset lr, -4
207207
; CHECK-V7-FP: .cfi_offset r11, -8
208-
; CHECK-V7-FP: .cfi_offset r4, -12
209-
; CHECK-V7-FP: add r11, sp, #4
208+
; CHECK-V7-FP: .cfi_offset r10, -12
209+
; CHECK-V7-FP: .cfi_offset r4, -16
210+
; CHECK-V7-FP: add r11, sp, #8
210211
; CHECK-V7-FP: .cfi_def_cfa r11, 8
211212
; CHECK-V7-FP: vpush {d8, d9, d10, d11, d12}
212213
; CHECK-V7-FP: .cfi_offset d12, -24
213214
; CHECK-V7-FP: .cfi_offset d11, -32
214215
; CHECK-V7-FP: .cfi_offset d10, -40
215216
; CHECK-V7-FP: .cfi_offset d9, -48
216217
; CHECK-V7-FP: .cfi_offset d8, -56
217-
; CHECK-V7-FP: sub sp, sp, #28
218+
; CHECK-V7-FP: sub sp, sp, #24
218219
; CHECK-V7-FP: .cfi_endproc
219220

220221
; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:

‎test/CodeGen/ARM/ehabi.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -148,14 +148,14 @@ declare void @_ZSt9terminatev()
148148

149149
; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
150150
; CHECK-V7-FP: .fnstart
151-
; CHECK-V7-FP: .save {r4, r11, lr}
152-
; CHECK-V7-FP: push {r4, r11, lr}
153-
; CHECK-V7-FP: .setfp r11, sp, #4
154-
; CHECK-V7-FP: add r11, sp, #4
151+
; CHECK-V7-FP: .save {r4, r10, r11, lr}
152+
; CHECK-V7-FP: push {r4, r10, r11, lr}
153+
; CHECK-V7-FP: .setfp r11, sp, #8
154+
; CHECK-V7-FP: add r11, sp, #8
155155
; CHECK-V7-FP: .vsave {d8, d9, d10, d11, d12}
156156
; CHECK-V7-FP: vpush {d8, d9, d10, d11, d12}
157-
; CHECK-V7-FP: .pad #28
158-
; CHECK-V7-FP: sub sp, sp, #28
157+
; CHECK-V7-FP: .pad #24
158+
; CHECK-V7-FP: sub sp, sp, #24
159159
; CHECK-V7-FP: .personality __gxx_personality_v0
160160
; CHECK-V7-FP: .handlerdata
161161
; CHECK-V7-FP: .fnend

‎test/CodeGen/ARM/interrupt-attr.ll‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,13 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
1212

1313
; Also need special function return setting pc and CPSR simultaneously.
1414
; CHECK-A-LABEL: irq_fn:
15-
; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr}
16-
; CHECK-A: add r11, sp, #16
17-
; CHECK-A: sub sp, sp, #{{[0-9]+}}
15+
; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
16+
; CHECK-A: add r11, sp, #20
17+
; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
1818
; CHECK-A: bic sp, sp, #7
1919
; CHECK-A: bl bar
20-
; CHECK-A: sub sp, r11, #16
21-
; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr}
20+
; CHECK-A: sub sp, r11, #20
21+
; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
2222
; CHECK-A: subs pc, lr, #4
2323

2424
; CHECK-A-THUMB-LABEL: irq_fn:
@@ -35,15 +35,15 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
3535
; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
3636
; appropriate sentinel so no special return needed).
3737
; CHECK-M-LABEL: irq_fn:
38-
; CHECK-M: push {r4, r7, lr}
39-
; CHECK-M: add r7, sp, #4
38+
; CHECK-M: push {r4, r6, r7, lr}
39+
; CHECK-M: add r7, sp, #8
4040
; CHECK-M: mov r4, sp
4141
; CHECK-M: bic r4, r4, #7
4242
; CHECK-M: mov sp, r4
4343
; CHECK-M: blx _bar
44-
; CHECK-M: subs r4, r7, #4
44+
; CHECK-M: sub.w r4, r7, #8
4545
; CHECK-M: mov sp, r4
46-
; CHECK-M: pop {r4, r7, pc}
46+
; CHECK-M: pop {r4, r6, r7, pc}
4747

4848
call arm_aapcscc void @bar()
4949
ret void
@@ -88,13 +88,13 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" {
8888

8989
define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" {
9090
; CHECK-A-LABEL: undef_fn:
91-
; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr}
92-
; CHECK-A: add r11, sp, #16
93-
; CHECK-A: sub sp, sp, #{{[0-9]+}}
91+
; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
92+
; CHECK-A: add r11, sp, #20
93+
; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
9494
; CHECK-A: bic sp, sp, #7
9595
; [...]
96-
; CHECK-A: sub sp, r11, #16
97-
; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr}
96+
; CHECK-A: sub sp, r11, #20
97+
; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
9898
; CHECK-A: subs pc, lr, #0
9999

100100
call void @bar()
@@ -103,13 +103,13 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" {
103103

104104
define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" {
105105
; CHECK-A-LABEL: abort_fn:
106-
; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr}
107-
; CHECK-A: add r11, sp, #16
108-
; CHECK-A: sub sp, sp, #{{[0-9]+}}
106+
; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}
107+
; CHECK-A: add r11, sp, #20
108+
; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}
109109
; CHECK-A: bic sp, sp, #7
110110
; [...]
111-
; CHECK-A: sub sp, r11, #16
112-
; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr}
111+
; CHECK-A: sub sp, r11, #20
112+
; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}
113113
; CHECK-A: subs pc, lr, #4
114114

115115
call void @bar()

‎test/CodeGen/ARM/segmented-stacks-dynamic.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ false:
2929
; ARM-linux-NEXT: cmp r4, r5
3030
; ARM-linux-NEXT: blo .LBB0_2
3131

32-
; ARM-linux: mov r4, #24
32+
; ARM-linux: mov r4, #16
3333
; ARM-linux-NEXT: mov r5, #0
3434
; ARM-linux-NEXT: stmdb sp!, {lr}
3535
; ARM-linux-NEXT: bl __morestack
@@ -49,7 +49,7 @@ false:
4949
; ARM-android-NEXT: cmp r4, r5
5050
; ARM-android-NEXT: blo .LBB0_2
5151

52-
; ARM-android: mov r4, #24
52+
; ARM-android: mov r4, #16
5353
; ARM-android-NEXT: mov r5, #0
5454
; ARM-android-NEXT: stmdb sp!, {lr}
5555
; ARM-android-NEXT: bl __morestack

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