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[mips] Fix 64-bit address loading in case of applying 32-bit mask to the result
If result of 64-bit address loading combines with 32-bit mask, LLVM tries to optimize the code and remove "redundant" loading of upper 32-bits of the address. It leads to incorrect code on MIPS64 targets. MIPS backend creates the following chain of commands to load 64-bit address in the `MipsTargetLowering::getAddrNonPICSym64` method: ``` (add (shl (add (shl (add %highest(sym), %higher(sym)), 16), %hi(sym)), 16), %lo(%sym)) ``` If the mask presents, LLVM decides to optimize the chain of commands. It really does not make sense to load upper 32-bits because the 0x0fffffff mask anyway clears them. After removing redundant commands we get this chain: ``` (add (shl (%hi(sym), 16), %lo(%sym)) ``` There is no patterns matched `(MipsHi (i64 symbol))`. Due a bug in `SYM_32` predicate definition, backend incorrectly selects a pattern for a 32-bit symbols and uses the `lui` instruction for loading `%hi(sym)`. As a result we get incorrect set of instructions with unnecessary 16-bit left shifting: ``` lui at,0x0 R_MIPS_HI16 foo dsll at,at,0x10 daddiu at,at,0 R_MIPS_LO16 foo ``` This patch resolves two problems: - Fix `SYM_32/SYM_64` predicates to prevent selection of patterns dedicated to 32-bit symbols in case of using N64 ABI. - Add missed patterns for 64-bit symbols for `%hi/%lo`. Fix PR42736. Differential Revision: https://reviews.llvm.org/D66228 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370268 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/Mips/Mips.td‎

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Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@ class PredicateControl {
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list<Predicate> GPRPredicates = [];
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// Predicates for the PTR size such as IsPTR64bit
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list<Predicate> PTRPredicates = [];
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// Predicates for a symbol's size such as hasSym32.
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list<Predicate> SYMPredicates = [];
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// Predicates for the FGR size and layout such as IsFP64bit
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list<Predicate> FGRPredicates = [];
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// Predicates for the instruction group membership such as ISA's.
@@ -38,6 +40,7 @@ class PredicateControl {
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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GPRPredicates,
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PTRPredicates,
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SYMPredicates,
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FGRPredicates,
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InsnPredicates,
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HardFloatPredicate,

‎lib/Target/Mips/Mips64InstrInfo.td‎

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@@ -682,6 +682,20 @@ let AdditionalPredicates = [NotInMicroMips] in {
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(DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
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(DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 texternalsym:$lo))),
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(DADDiu GPR64:$hi, texternalsym:$lo)>,
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ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsHi (i64 tglobaladdr:$in)),
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(DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsHi (i64 tblockaddress:$in)),
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(DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsHi (i64 tjumptable:$in)),
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(DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsHi (i64 tconstpool:$in)),
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(DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsHi (i64 texternalsym:$in)),
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(DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
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(DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
@@ -692,6 +706,23 @@ let AdditionalPredicates = [NotInMicroMips] in {
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(DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))),
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(DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsHi (i64 texternalsym:$lo))),
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(DADDiu GPR64:$hi, texternalsym:$lo)>,
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ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 tglobaladdr:$in)),
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(DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 tblockaddress:$in)),
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(DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 tjumptable:$in)),
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(DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 tconstpool:$in)),
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(DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 tglobaltlsaddr:$in)),
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(DADDiu ZERO_64, tglobaltlsaddr:$in)>,
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ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(MipsLo (i64 texternalsym:$in)),
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(DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
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(DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
@@ -705,6 +736,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
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(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64,
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SYM_64;
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def : MipsPat<(add GPR64:$hi, (MipsLo (i64 texternalsym:$lo))),
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(DADDiu GPR64:$hi, texternalsym:$lo)>,
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ISA_MIPS3, GPR_64, SYM_64;
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}
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// gp_rel relocs

‎lib/Target/Mips/MipsInstrInfo.td‎

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@@ -211,9 +211,9 @@ def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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AssemblerPredicate<"FeatureCnMips">;
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def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
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AssemblerPredicate<"!FeatureCnMips">;
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def IsSym32 : Predicate<"Subtarget->HasSym32()">,
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def IsSym32 : Predicate<"Subtarget->hasSym32()">,
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AssemblerPredicate<"FeatureSym32">;
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def IsSym64 : Predicate<"!Subtarget->HasSym32()">,
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def IsSym64 : Predicate<"!Subtarget->hasSym32()">,
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AssemblerPredicate<"!FeatureSym32">;
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def IsN64 : Predicate<"Subtarget->isABI_N64()">;
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def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">;

‎test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -74,20 +74,18 @@ define void @caller() {
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; N64-NEXT: daddiu $25, $1, %lo(callee)
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; N64-NEXT: jalr.hb $25
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; N64-NEXT: nop
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; N64-NEXT: daddiu $1, $zero, %higher(memset)
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; N64-NEXT: lui $2, %highest(memset)
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; N64-NEXT: daddu $1, $2, $1
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: lui $2, %hi(memset)
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; N64-NEXT: daddu $1, $1, $2
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: daddiu $25, $1, %lo(memset)
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; N64-NEXT: lui $1, %highest(val)
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; N64-NEXT: daddiu $1, $1, %higher(val)
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: daddiu $1, $1, %hi(val)
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: lui $2, %highest(memset)
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; N64-NEXT: daddiu $4, $1, %lo(val)
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; N64-NEXT: daddiu $1, $2, %higher(memset)
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: daddiu $1, $1, %hi(memset)
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: daddiu $25, $1, %lo(memset)
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; N64-NEXT: daddiu $5, $zero, 0
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; N64-NEXT: jalr.hb $25
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; N64-NEXT: daddiu $6, $zero, 80

‎test/CodeGen/Mips/long-calls.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,11 @@ define void @caller() {
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; ON64: daddiu $25, $1, %lo(callee)
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; ON64: jalr $25
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; ON64: daddiu $1, $zero, %higher(memset)
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; ON64: lui $2, %highest(memset)
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; ON64: lui $2, %hi(memset)
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; ON64: daddiu $1, $2, %higher(memset)
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; ON64: dsll $1, $1, 16
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; ON64: daddiu $1, $1, %hi(memset)
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; ON64: dsll $1, $1, 16
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; ON64: daddiu $25, $1, %lo(memset)
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; ON64: jalr $25
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‎test/CodeGen/Mips/pr42736.ll‎

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@@ -0,0 +1,28 @@
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; RUN: llc -mtriple=mips64-linux-gnuabi64 \
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; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
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; RUN: llc -mtriple=mips64-linux-gnuabi64 \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC
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define void @bar1() nounwind {
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entry:
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; PIC: lui $[[R0:[0-9]+]], 4095
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; PIC-NEXT: ori $[[R0]], $[[R0]], 65535
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; PIC-NEXT: ld $[[R1:[0-9]+]], %got_disp(foo)(${{[0-9]+}})
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; PIC-NEXT: and $[[R1]], $[[R1]], $[[R0]]
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; PIC-NEXT: sd $[[R1]]
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; STATIC: lui $[[R0:[0-9]+]], 4095
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; STATIC-NEXT: ori $[[R0]], $[[R0]], 65535
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; STATIC-NEXT: daddiu $[[R1:[0-9]+]], $zero, %hi(foo)
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; STATIC-NEXT: dsll $[[R1]], $[[R1]], 16
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; STATIC-NEXT: daddiu $[[R1]], $[[R1]], %lo(foo)
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; STATIC-NEXT: and $[[R0]], $[[R1]], $[[R0]]
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; STATIC-NEXT: sd $[[R0]]
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%val = alloca i64, align 8
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store i64 and (i64 ptrtoint (void ()* @foo to i64), i64 268435455), i64* %val, align 8
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%0 = load i64, i64* %val, align 8
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ret void
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}
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declare void @foo()

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