uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board

[at91rm9200]

Hello Sylvain,

it looks as if the directions of the signals uart_tx and uart_rx are swapped in the Verilog framework file for the ECPIX5 board.

module top(
  // basic
  output [11:0] leds,
`ifdef UART
  // uart
  output  uart_rx, // ?
  input   uart_tx, // ?
`endif

Regards, Bernd.

Edit:
this is confusing. According to the schematics of the board, uart_rx is indeed an output and uart_tx is an input.

But then, I don't understand the following declarations in the Verilog framework file:

M_main __main(
  .reset         (RST_q[0]),
  .in_run        (run_main),
  .out_leds      (__main_leds),
`ifdef UART
  .out_uart_tx  (uart_tx), // shouldn't this be then input?
  .in_uart_rx   (uart_rx), // shouldn't this be then output?
`endif

[sylefeb]

Hi Bernd, thanks for looking into this! I'm away from the board right now so cannot test, but I seem to remember being confused about this when doing the profile. (Might be a confusion with which side we look at, unsure what the convention is).