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cuda_fp16.hpp
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/*
* Copyright 1993-2019 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO LICENSEE:
*
* This source code and/or documentation ("Licensed Deliverables") are
* subject to NVIDIA intellectual property rights under U.S. and
* international Copyright laws.
*
* These Licensed Deliverables contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a form of NVIDIA software license agreement by and
* between NVIDIA and Licensee ("License Agreement") or electronically
* accepted by Licensee. Notwithstanding any terms or conditions to
* the contrary in the License Agreement, reproduction or disclosure
* of the Licensed Deliverables to any third party without the express
* written consent of NVIDIA is prohibited.
*
* NOTWITHSTANDING ANY TERMS OR CONDITIONS TO THE CONTRARY IN THE
* LICENSE AGREEMENT, NVIDIA MAKES NO REPRESENTATION ABOUT THE
* SUITABILITY OF THESE LICENSED DELIVERABLES FOR ANY PURPOSE. IT IS
* PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.
* NVIDIA DISCLAIMS ALL WARRANTIES WITH REGARD TO THESE LICENSED
* DELIVERABLES, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
* NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* NOTWITHSTANDING ANY TERMS OR CONDITIONS TO THE CONTRARY IN THE
* LICENSE AGREEMENT, IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY
* SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
* WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
* ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
* OF THESE LICENSED DELIVERABLES.
*
* U.S. Government End Users. These Licensed Deliverables are a
* "commercial item" as that term is defined at 48 C.F.R. 2.101 (OCT
* 1995), consisting of "commercial computer software" and "commercial
* computer software documentation" as such terms are used in 48
* C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Government
* only as a commercial end item. Consistent with 48 C.F.R.12.212 and
* 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), all
* U.S. Government End Users acquire the Licensed Deliverables with
* only those rights set forth herein.
*
* Any use of the Licensed Deliverables in individual and commercial
* software must include, in the user documentation and internal
* comments to the code, the above Disclaimer and U.S. Government End
* Users Notice.
*/
#if !defined(__CUDA_FP16_HPP__)
#define __CUDA_FP16_HPP__
/* C++11 header for std::move.
* In RTC mode, std::move is provided implicitly; don't include the header
*/
#if (__cplusplus >= 201103L) && !defined(__CUDACC_RTC__)
#include <utility>
#endif /* __cplusplus >= 201103L && !defined(__CUDACC_RTC__) */
/* C++ header for std::memcpy (used for type punning in host-side implementations).
* When compiling as a CUDA source file memcpy is provided implicitly.
* !defined(__CUDACC__) implies !defined(__CUDACC_RTC__).
*/
#if defined(__cplusplus) && !defined(__CUDACC__)
#include <cstring>
#endif /* defined(__cplusplus) && !defined(__CUDACC__) */
/* Set up function decorations */
#if defined(__CUDACC__)
#define __CUDA_FP16_DECL__ static __device__ __inline__
#define __CUDA_HOSTDEVICE_FP16_DECL__ static __host__ __device__ __inline__
#define __VECTOR_FUNCTIONS_DECL__ static __inline__ __host__ __device__
#define __CUDA_HOSTDEVICE__ __host__ __device__
#else /* !defined(__CUDACC__) */
#if defined(__GNUC__)
#define __CUDA_HOSTDEVICE_FP16_DECL__ static __attribute__ ((unused))
#else
#define __CUDA_HOSTDEVICE_FP16_DECL__ static
#endif /* defined(__GNUC__) */
#define __CUDA_HOSTDEVICE__
#endif /* defined(__CUDACC_) */
/* Set up structure-alignment attribute */
#if defined(__CUDACC__)
#define __CUDA_ALIGN__(align) __align__(align)
#else
/* Define alignment macro based on compiler type (cannot assume C11 "_Alignas" is available) */
#if __cplusplus >= 201103L
#define __CUDA_ALIGN__(n) alignas(n) /* C++11 kindly gives us a keyword for this */
#else /* !(__cplusplus >= 201103L)*/
#if defined(__GNUC__)
#define __CUDA_ALIGN__(n) __attribute__ ((aligned(n)))
#elif defined(_MSC_VER)
#define __CUDA_ALIGN__(n) __declspec(align(n))
#else
#define __CUDA_ALIGN__(n)
#endif /* defined(__GNUC__) */
#endif /* __cplusplus >= 201103L */
#endif /* defined(__CUDACC__) */
/* Macros to allow half & half2 to be used by inline assembly */
#define __HALF_TO_US(var) *(reinterpret_cast<unsigned short *>(&(var)))
#define __HALF_TO_CUS(var) *(reinterpret_cast<const unsigned short *>(&(var)))
#define __HALF2_TO_UI(var) *(reinterpret_cast<unsigned int *>(&(var)))
#define __HALF2_TO_CUI(var) *(reinterpret_cast<const unsigned int *>(&(var)))
/**
* Types which allow static initialization of "half" and "half2" until
* these become an actual builtin. Note this initialization is as a
* bitfield representation of "half", and not a conversion from short->half.
* Such a representation will be deprecated in a future version of CUDA.
* (Note these are visible to non-nvcc compilers, including C-only compilation)
*/
typedef struct __CUDA_ALIGN__(2) {
unsigned short x;
} __half_raw;
typedef struct __CUDA_ALIGN__(4) {
unsigned short x;
unsigned short y;
} __half2_raw;
/* All other definitions in this file are only visible to C++ compilers */
#if defined(__cplusplus)
/* Hide GCC member initialization list warnings because of host/device in-function init requirement */
#if defined(__GNUC__)
#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#pragma GCC diagnostic ignored "-Weffc++"
#endif /* __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) */
#endif /* defined(__GNUC__) */
/* class' : multiple assignment operators specified
The class has multiple assignment operators of a single type. This warning is informational */
#if defined(_MSC_VER) && _MSC_VER >= 1500
#pragma warning( push )
#pragma warning( disable:4522 )
#endif /* defined(__GNUC__) */
struct __CUDA_ALIGN__(2) __half {
protected:
unsigned short __x;
public:
#if __cplusplus >= 201103L
__half() = default;
#else
__CUDA_HOSTDEVICE__ __half() { }
#endif /* __cplusplus >= 201103L */
/* Convert to/from __half_raw */
__CUDA_HOSTDEVICE__ __half(const __half_raw &hr) : __x(hr.x) { }
__CUDA_HOSTDEVICE__ __half &operator=(const __half_raw &hr) { __x = hr.x; return *this; }
__CUDA_HOSTDEVICE__ volatile __half &operator=(const __half_raw &hr) volatile { __x = hr.x; return *this; }
__CUDA_HOSTDEVICE__ volatile __half &operator=(const volatile __half_raw &hr) volatile { __x = hr.x; return *this; }
__CUDA_HOSTDEVICE__ operator __half_raw() const { __half_raw ret; ret.x = __x; return ret; }
__CUDA_HOSTDEVICE__ operator __half_raw() const volatile { __half_raw ret; ret.x = __x; return ret; }
#if !defined(__CUDA_NO_HALF_CONVERSIONS__)
/* Construct from float/double */
__CUDA_HOSTDEVICE__ __half(const float f) { __x = __float2half(f).__x; }
__CUDA_HOSTDEVICE__ __half(const double f) { __x = __float2half(static_cast<float>(f)).__x; }
__CUDA_HOSTDEVICE__ operator float() const { return __half2float(*this); }
__CUDA_HOSTDEVICE__ __half &operator=(const float f) { __x = __float2half(f).__x; return *this; }
/* We omit "cast to double" operator, so as to not be ambiguous about up-cast */
__CUDA_HOSTDEVICE__ __half &operator=(const double f) { __x = __float2half(static_cast<float>(f)).__x; return *this; }
/* Member functions only available to nvcc compilation so far */
#if defined(__CUDACC__)
/* Allow automatic construction from types supported natively in hardware */
/* Note we do avoid constructor init-list because of special host/device compilation rules */
__device__ __half(short val) { __x = __short2half_rn(val).__x; }
__device__ __half(unsigned short val) { __x = __ushort2half_rn(val).__x; }
__device__ __half(int val) { __x = __int2half_rn(val).__x; }
__device__ __half(unsigned int val) { __x = __uint2half_rn(val).__x; }
__device__ __half(long long val) { __x = __ll2half_rn(val).__x; }
__device__ __half(unsigned long long val) { __x = __ull2half_rn(val).__x; }
/* Allow automatic casts to supported builtin types, matching all that are permitted with float */
__device__ operator short() const { return __half2short_rn(*this); }
__device__ __half &operator=(short val) { __x = __short2half_rn(val).__x; return *this; }
__device__ operator unsigned short() const { return __half2ushort_rn(*this); }
__device__ __half &operator=(unsigned short val) { __x = __ushort2half_rn(val).__x; return *this; }
__device__ operator int() const { return __half2int_rn(*this); }
__device__ __half &operator=(int val) { __x = __int2half_rn(val).__x; return *this; }
__device__ operator unsigned int() const { return __half2uint_rn(*this); }
__device__ __half &operator=(unsigned int val) { __x = __uint2half_rn(val).__x; return *this; }
__device__ operator long long() const { return __half2ll_rn(*this); }
__device__ __half &operator=(long long val) { __x = __ll2half_rn(val).__x; return *this; }
__device__ operator unsigned long long() const { return __half2ull_rn(*this); }
__device__ __half &operator=(unsigned long long val) { __x = __ull2half_rn(val).__x; return *this; }
/* Boolean conversion - note both 0 and -0 must return false */
__device__ operator bool() const { return (__x & 0x7FFF) != 0; }
#endif /* defined(__CUDACC__) */
#endif /* !defined(__CUDA_NO_HALF_CONVERSIONS__) */
};
/* Global-space operator functions are only available to nvcc compilation */
#if defined(__CUDACC__)
/* Arithmetic FP16 operations only supported on arch >= 5.3 */
#if __CUDA_ARCH__ >= 530 || !defined(__CUDA_ARCH__)
#if !defined(__CUDA_NO_HALF_OPERATORS__)
/* Some basic arithmetic operations expected of a builtin */
__device__ __forceinline__ __half operator+(const __half &lh, const __half &rh) { return __hadd(lh, rh); }
__device__ __forceinline__ __half operator-(const __half &lh, const __half &rh) { return __hsub(lh, rh); }
__device__ __forceinline__ __half operator*(const __half &lh, const __half &rh) { return __hmul(lh, rh); }
__device__ __forceinline__ __half operator/(const __half &lh, const __half &rh) { return __hdiv(lh, rh); }
__device__ __forceinline__ __half &operator+=(__half &lh, const __half &rh) { lh = __hadd(lh, rh); return lh; }
__device__ __forceinline__ __half &operator-=(__half &lh, const __half &rh) { lh = __hsub(lh, rh); return lh; }
__device__ __forceinline__ __half &operator*=(__half &lh, const __half &rh) { lh = __hmul(lh, rh); return lh; }
__device__ __forceinline__ __half &operator/=(__half &lh, const __half &rh) { lh = __hdiv(lh, rh); return lh; }
/* Note for increment and decrement we use the raw value 0x3C00 equating to half(1.0f), to avoid the extra conversion */
__device__ __forceinline__ __half &operator++(__half &h) { __half_raw one; one.x = 0x3C00; h += one; return h; }
__device__ __forceinline__ __half &operator--(__half &h) { __half_raw one; one.x = 0x3C00; h -= one; return h; }
__device__ __forceinline__ __half operator++(__half &h, int) { __half ret = h; __half_raw one; one.x = 0x3C00; h += one; return ret; }
__device__ __forceinline__ __half operator--(__half &h, int) { __half ret = h; __half_raw one; one.x = 0x3C00; h -= one; return ret; }
/* Unary plus and inverse operators */
__device__ __forceinline__ __half operator+(const __half &h) { return h; }
__device__ __forceinline__ __half operator-(const __half &h) { return __hneg(h); }
/* Some basic comparison operations to make it look like a builtin */
__device__ __forceinline__ bool operator==(const __half &lh, const __half &rh) { return __heq(lh, rh); }
__device__ __forceinline__ bool operator!=(const __half &lh, const __half &rh) { return __hne(lh, rh); }
__device__ __forceinline__ bool operator> (const __half &lh, const __half &rh) { return __hgt(lh, rh); }
__device__ __forceinline__ bool operator< (const __half &lh, const __half &rh) { return __hlt(lh, rh); }
__device__ __forceinline__ bool operator>=(const __half &lh, const __half &rh) { return __hge(lh, rh); }
__device__ __forceinline__ bool operator<=(const __half &lh, const __half &rh) { return __hle(lh, rh); }
#endif /* !defined(__CUDA_NO_HALF_OPERATORS__) */
#endif /* __CUDA_ARCH__ >= 530 || !defined(__CUDA_ARCH__) */
#endif /* defined(__CUDACC__) */
/* __half2 is visible to non-nvcc host compilers */
struct __CUDA_ALIGN__(4) __half2 {
__half x;
__half y;
// All construct/copy/assign/move
public:
#if __cplusplus >= 201103L
__half2() = default;
__CUDA_HOSTDEVICE__ __half2(__half2 &&src) { __HALF2_TO_UI(*this) = std::move(__HALF2_TO_CUI(src)); }
__CUDA_HOSTDEVICE__ __half2 &operator=(__half2 &&src) { __HALF2_TO_UI(*this) = std::move(__HALF2_TO_CUI(src)); return *this; }
#else
__CUDA_HOSTDEVICE__ __half2() { }
#endif /* __cplusplus >= 201103L */
__CUDA_HOSTDEVICE__ __half2(const __half &a, const __half &b) : x(a), y(b) { }
__CUDA_HOSTDEVICE__ __half2(const __half2 &src) { __HALF2_TO_UI(*this) = __HALF2_TO_CUI(src); }
__CUDA_HOSTDEVICE__ __half2 &operator=(const __half2 &src) { __HALF2_TO_UI(*this) = __HALF2_TO_CUI(src); return *this; }
/* Convert to/from __half2_raw */
__CUDA_HOSTDEVICE__ __half2(const __half2_raw &h2r ) { __HALF2_TO_UI(*this) = __HALF2_TO_CUI(h2r); }
__CUDA_HOSTDEVICE__ __half2 &operator=(const __half2_raw &h2r) { __HALF2_TO_UI(*this) = __HALF2_TO_CUI(h2r); return *this; }
__CUDA_HOSTDEVICE__ operator __half2_raw() const { __half2_raw ret; __HALF2_TO_UI(ret) = __HALF2_TO_CUI(*this); return ret; }
};
/* Global-space operator functions are only available to nvcc compilation */
#if defined(__CUDACC__)
/* Arithmetic FP16x2 operations only supported on arch >= 5.3 */
#if (__CUDA_ARCH__ >= 530 || !defined(__CUDA_ARCH__)) && !defined(__CUDA_NO_HALF2_OPERATORS__)
__device__ __forceinline__ __half2 operator+(const __half2 &lh, const __half2 &rh) { return __hadd2(lh, rh); }
__device__ __forceinline__ __half2 operator-(const __half2 &lh, const __half2 &rh) { return __hsub2(lh, rh); }
__device__ __forceinline__ __half2 operator*(const __half2 &lh, const __half2 &rh) { return __hmul2(lh, rh); }
__device__ __forceinline__ __half2 operator/(const __half2 &lh, const __half2 &rh) { return __h2div(lh, rh); }
__device__ __forceinline__ __half2& operator+=(__half2 &lh, const __half2 &rh) { lh = __hadd2(lh, rh); return lh; }
__device__ __forceinline__ __half2& operator-=(__half2 &lh, const __half2 &rh) { lh = __hsub2(lh, rh); return lh; }
__device__ __forceinline__ __half2& operator*=(__half2 &lh, const __half2 &rh) { lh = __hmul2(lh, rh); return lh; }
__device__ __forceinline__ __half2& operator/=(__half2 &lh, const __half2 &rh) { lh = __h2div(lh, rh); return lh; }
__device__ __forceinline__ __half2 &operator++(__half2 &h) { __half2_raw one; one.x = 0x3C00; one.y = 0x3C00; h = __hadd2(h, one); return h; }
__device__ __forceinline__ __half2 &operator--(__half2 &h) { __half2_raw one; one.x = 0x3C00; one.y = 0x3C00; h = __hsub2(h, one); return h; }
__device__ __forceinline__ __half2 operator++(__half2 &h, int) { __half2 ret = h; __half2_raw one; one.x = 0x3C00; one.y = 0x3C00; h = __hadd2(h, one); return ret; }
__device__ __forceinline__ __half2 operator--(__half2 &h, int) { __half2 ret = h; __half2_raw one; one.x = 0x3C00; one.y = 0x3C00; h = __hsub2(h, one); return ret; }
__device__ __forceinline__ __half2 operator+(const __half2 &h) { return h; }
__device__ __forceinline__ __half2 operator-(const __half2 &h) { return __hneg2(h); }
__device__ __forceinline__ bool operator==(const __half2 &lh, const __half2 &rh) { return __hbeq2(lh, rh); }
__device__ __forceinline__ bool operator!=(const __half2 &lh, const __half2 &rh) { return __hbne2(lh, rh); }
__device__ __forceinline__ bool operator>(const __half2 &lh, const __half2 &rh) { return __hbgt2(lh, rh); }
__device__ __forceinline__ bool operator<(const __half2 &lh, const __half2 &rh) { return __hblt2(lh, rh); }
__device__ __forceinline__ bool operator>=(const __half2 &lh, const __half2 &rh) { return __hbge2(lh, rh); }
__device__ __forceinline__ bool operator<=(const __half2 &lh, const __half2 &rh) { return __hble2(lh, rh); }
#endif /* __CUDA_ARCH__ >= 530 || !defined(__CUDA_ARCH__) */
#endif /* defined(__CUDACC__) */
/* Restore warning for multiple assignment operators */
#if defined(_MSC_VER) && _MSC_VER >= 1500
#pragma warning( pop )
#endif /* defined(_MSC_VER) && _MSC_VER >= 1500 */
/* Restore -Weffc++ warnings from here on */
#if defined(__GNUC__)
#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
#pragma GCC diagnostic pop
#endif /* __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) */
#endif /* defined(__GNUC__) */
#undef __CUDA_HOSTDEVICE__
#undef __CUDA_ALIGN__
#ifndef __CUDACC_RTC__ /* no host functions in NVRTC mode */
static unsigned short __internal_float2half(const float f, unsigned int &sign, unsigned int &remainder)
{
unsigned int x;
unsigned int u;
unsigned int result = 0U;
#if defined(__CUDACC__)
(void)memcpy(&x, &f, sizeof(f));
#else
(void)std::memcpy(&x, &f, sizeof(f));
#endif
u = (x & 0x7fffffffU);
sign = ((x >> 16U) & 0x8000U);
// NaN/+Inf/-Inf
if (u >= 0x7f800000U) {
remainder = 0U;
result = ((u == 0x7f800000U) ? (sign | 0x7c00U) : 0x7fffU);
} else if (u > 0x477fefffU) { // Overflows
remainder = 0x80000000U;
result = (sign | 0x7bffU);
} else if (u >= 0x38800000U) { // Normal numbers
remainder = u << 19U;
u -= 0x38000000U;
result = (sign | (u >> 13U));
} else if (u < 0x33000001U) { // +0/-0
remainder = u;
result = sign;
} else { // Denormal numbers
const unsigned int exponent = u >> 23U;
const unsigned int shift = 0x7eU - exponent;
unsigned int mantissa = (u & 0x7fffffU);
mantissa |= 0x800000U;
remainder = mantissa << (32U - shift);
result = (sign | (mantissa >> shift));
}
return static_cast<unsigned short>(result);
}
#endif /* #if !defined(__CUDACC_RTC__) */
__CUDA_HOSTDEVICE_FP16_DECL__ __half __float2half(const float a)
{
__half val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.rn.f16.f32 %0, %1;}\n" : "=h"(__HALF_TO_US(val)) : "f"(a));
#else
__half_raw r;
unsigned int sign;
unsigned int remainder;
r.x = __internal_float2half(a, sign, remainder);
if ((remainder > 0x80000000U) || ((remainder == 0x80000000U) && ((r.x & 0x1U) != 0U))) {
r.x++;
}
val = r;
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half __float2half_rn(const float a)
{
__half val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.rn.f16.f32 %0, %1;}\n" : "=h"(__HALF_TO_US(val)) : "f"(a));
#else
__half_raw r;
unsigned int sign;
unsigned int remainder;
r.x = __internal_float2half(a, sign, remainder);
if ((remainder > 0x80000000U) || ((remainder == 0x80000000U) && ((r.x & 0x1U) != 0U))) {
r.x++;
}
val = r;
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half __float2half_rz(const float a)
{
__half val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.rz.f16.f32 %0, %1;}\n" : "=h"(__HALF_TO_US(val)) : "f"(a));
#else
__half_raw r;
unsigned int sign;
unsigned int remainder;
r.x = __internal_float2half(a, sign, remainder);
val = r;
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half __float2half_rd(const float a)
{
__half val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.rm.f16.f32 %0, %1;}\n" : "=h"(__HALF_TO_US(val)) : "f"(a));
#else
__half_raw r;
unsigned int sign;
unsigned int remainder;
r.x = __internal_float2half(a, sign, remainder);
if ((remainder != 0U) && (sign != 0U)) {
r.x++;
}
val = r;
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half __float2half_ru(const float a)
{
__half val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.rp.f16.f32 %0, %1;}\n" : "=h"(__HALF_TO_US(val)) : "f"(a));
#else
__half_raw r;
unsigned int sign;
unsigned int remainder;
r.x = __internal_float2half(a, sign, remainder);
if ((remainder != 0U) && (sign == 0U)) {
r.x++;
}
val = r;
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half2 __float2half2_rn(const float a)
{
__half2 val;
#if defined(__CUDA_ARCH__)
asm("{.reg .f16 low;\n"
" cvt.rn.f16.f32 low, %1;\n"
" mov.b32 %0, {low,low};}\n" : "=r"(__HALF2_TO_UI(val)) : "f"(a));
#else
val = __half2(__float2half_rn(a), __float2half_rn(a));
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ __half2 __floats2half2_rn(const float a, const float b)
{
__half2 val;
#if defined(__CUDA_ARCH__)
asm("{.reg .f16 low,high;\n"
" cvt.rn.f16.f32 low, %1;\n"
" cvt.rn.f16.f32 high, %2;\n"
" mov.b32 %0, {low,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "f"(a), "f"(b));
#else
val = __half2(__float2half_rn(a), __float2half_rn(b));
#endif
return val;
}
#ifndef __CUDACC_RTC__ /* no host functions in NVRTC mode */
static float __internal_half2float(const unsigned short h)
{
unsigned int sign = ((static_cast<unsigned int>(h) >> 15U) & 1U);
unsigned int exponent = ((static_cast<unsigned int>(h) >> 10U) & 0x1fU);
unsigned int mantissa = ((static_cast<unsigned int>(h) & 0x3ffU) << 13U);
float f;
if (exponent == 0x1fU) { /* NaN or Inf */
sign = ((mantissa != 0U) ? 0U : sign);
mantissa = ((mantissa != 0U) ? 0x7fffffU : 0U);
exponent = 0xffU;
} else if (exponent == 0U) { /* Denorm or Zero */
if (mantissa != 0U) {
unsigned int msb;
exponent = 0x71U;
do {
msb = (mantissa & 0x400000U);
mantissa <<= 1U; /* normalize */
--exponent;
} while (msb == 0U);
mantissa &= 0x7fffffU; /* 1.mantissa is implicit */
}
} else {
exponent += 0x70U;
}
unsigned int u = ((sign << 31U) | (exponent << 23U) | mantissa);
#if defined(__CUDACC__)
(void)memcpy(&f, &u, sizeof(u));
#else
(void)std::memcpy(&f, &u, sizeof(u));
#endif
return f;
}
#endif /* !defined(__CUDACC_RTC__) */
__CUDA_HOSTDEVICE_FP16_DECL__ float __half2float(const __half a)
{
float val;
#if defined(__CUDA_ARCH__)
asm("{ cvt.f32.f16 %0, %1;}\n" : "=f"(val) : "h"(__HALF_TO_CUS(a)));
#else
val = __internal_half2float(static_cast<__half_raw>(a).x);
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ float __low2float(const __half2 a)
{
float val;
#if defined(__CUDA_ARCH__)
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high},%1;\n"
" cvt.f32.f16 %0, low;}\n" : "=f"(val) : "r"(__HALF2_TO_CUI(a)));
#else
val = __internal_half2float(static_cast<__half2_raw>(a).x);
#endif
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ float __high2float(const __half2 a)
{
float val;
#if defined(__CUDA_ARCH__)
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high},%1;\n"
" cvt.f32.f16 %0, high;}\n" : "=f"(val) : "r"(__HALF2_TO_CUI(a)));
#else
val = __internal_half2float(static_cast<__half2_raw>(a).y);
#endif
return val;
}
/* Intrinsic functions only available to nvcc compilers */
#if defined(__CUDACC__)
/* CUDA vector-types compatible vector creation function (note returns __half2, not half2) */
__VECTOR_FUNCTIONS_DECL__ __half2 make_half2(__half x, __half y)
{
__half2 t; t.x = x; t.y = y; return t;
}
#undef __VECTOR_FUNCTIONS_DECL__
/* Definitions of intrinsics */
__CUDA_HOSTDEVICE_FP16_DECL__ __half2 __float22half2_rn(const float2 f)
{
__half2 val = __floats2half2_rn(f.x, f.y);
return val;
}
__CUDA_HOSTDEVICE_FP16_DECL__ float2 __half22float2(const __half2 l)
{
float hi_float;
float lo_float;
#if defined(__CUDA_ARCH__)
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high},%1;\n"
" cvt.f32.f16 %0, low;}\n" : "=f"(lo_float) : "r"(__HALF2_TO_CUI(l)));
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high},%1;\n"
" cvt.f32.f16 %0, high;}\n" : "=f"(hi_float) : "r"(__HALF2_TO_CUI(l)));
#else
lo_float = __internal_half2float(((__half2_raw)l).x);
hi_float = __internal_half2float(((__half2_raw)l).y);
#endif
return make_float2(lo_float, hi_float);
}
__CUDA_FP16_DECL__ int __half2int_rn(__half h)
{
int i;
asm("cvt.rni.s32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ int __half2int_rz(__half h)
{
int i;
asm("cvt.rzi.s32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ int __half2int_rd(__half h)
{
int i;
asm("cvt.rmi.s32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ int __half2int_ru(__half h)
{
int i;
asm("cvt.rpi.s32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __int2half_rn(int i)
{
__half h;
asm("cvt.rn.f16.s32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __int2half_rz(int i)
{
__half h;
asm("cvt.rz.f16.s32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __int2half_rd(int i)
{
__half h;
asm("cvt.rm.f16.s32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __int2half_ru(int i)
{
__half h;
asm("cvt.rp.f16.s32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ short int __half2short_rn(__half h)
{
short int i;
asm("cvt.rni.s16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ short int __half2short_rz(__half h)
{
short int i;
asm("cvt.rzi.s16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ short int __half2short_rd(__half h)
{
short int i;
asm("cvt.rmi.s16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ short int __half2short_ru(__half h)
{
short int i;
asm("cvt.rpi.s16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __short2half_rn(short int i)
{
__half h;
asm("cvt.rn.f16.s16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __short2half_rz(short int i)
{
__half h;
asm("cvt.rz.f16.s16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __short2half_rd(short int i)
{
__half h;
asm("cvt.rm.f16.s16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __short2half_ru(short int i)
{
__half h;
asm("cvt.rp.f16.s16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ unsigned int __half2uint_rn(__half h)
{
unsigned int i;
asm("cvt.rni.u32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned int __half2uint_rz(__half h)
{
unsigned int i;
asm("cvt.rzi.u32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned int __half2uint_rd(__half h)
{
unsigned int i;
asm("cvt.rmi.u32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned int __half2uint_ru(__half h)
{
unsigned int i;
asm("cvt.rpi.u32.f16 %0, %1;" : "=r"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __uint2half_rn(unsigned int i)
{
__half h;
asm("cvt.rn.f16.u32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __uint2half_rz(unsigned int i)
{
__half h;
asm("cvt.rz.f16.u32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __uint2half_rd(unsigned int i)
{
__half h;
asm("cvt.rm.f16.u32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ __half __uint2half_ru(unsigned int i)
{
__half h;
asm("cvt.rp.f16.u32 %0, %1;" : "=h"(__HALF_TO_US(h)) : "r"(i));
return h;
}
__CUDA_FP16_DECL__ unsigned short int __half2ushort_rn(__half h)
{
unsigned short int i;
asm("cvt.rni.u16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned short int __half2ushort_rz(__half h)
{
unsigned short int i;
asm("cvt.rzi.u16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned short int __half2ushort_rd(__half h)
{
unsigned short int i;
asm("cvt.rmi.u16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned short int __half2ushort_ru(__half h)
{
unsigned short int i;
asm("cvt.rpi.u16.f16 %0, %1;" : "=h"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __ushort2half_rn(unsigned short int i)
{
__half h;
asm("cvt.rn.f16.u16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ushort2half_rz(unsigned short int i)
{
__half h;
asm("cvt.rz.f16.u16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ushort2half_rd(unsigned short int i)
{
__half h;
asm("cvt.rm.f16.u16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ushort2half_ru(unsigned short int i)
{
__half h;
asm("cvt.rp.f16.u16 %0, %1;" : "=h"(__HALF_TO_US(h)) : "h"(i));
return h;
}
__CUDA_FP16_DECL__ unsigned long long int __half2ull_rn(__half h)
{
unsigned long long int i;
asm("cvt.rni.u64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned long long int __half2ull_rz(__half h)
{
unsigned long long int i;
asm("cvt.rzi.u64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned long long int __half2ull_rd(__half h)
{
unsigned long long int i;
asm("cvt.rmi.u64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ unsigned long long int __half2ull_ru(__half h)
{
unsigned long long int i;
asm("cvt.rpi.u64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __ull2half_rn(unsigned long long int i)
{
__half h;
asm("cvt.rn.f16.u64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ull2half_rz(unsigned long long int i)
{
__half h;
asm("cvt.rz.f16.u64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ull2half_rd(unsigned long long int i)
{
__half h;
asm("cvt.rm.f16.u64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ull2half_ru(unsigned long long int i)
{
__half h;
asm("cvt.rp.f16.u64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ long long int __half2ll_rn(__half h)
{
long long int i;
asm("cvt.rni.s64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ long long int __half2ll_rz(__half h)
{
long long int i;
asm("cvt.rzi.s64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ long long int __half2ll_rd(__half h)
{
long long int i;
asm("cvt.rmi.s64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ long long int __half2ll_ru(__half h)
{
long long int i;
asm("cvt.rpi.s64.f16 %0, %1;" : "=l"(i) : "h"(__HALF_TO_US(h)));
return i;
}
__CUDA_FP16_DECL__ __half __ll2half_rn(long long int i)
{
__half h;
asm("cvt.rn.f16.s64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ll2half_rz(long long int i)
{
__half h;
asm("cvt.rz.f16.s64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ll2half_rd(long long int i)
{
__half h;
asm("cvt.rm.f16.s64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half __ll2half_ru(long long int i)
{
__half h;
asm("cvt.rp.f16.s64 %0, %1;" : "=h"(__HALF_TO_US(h)) : "l"(i));
return h;
}
__CUDA_FP16_DECL__ __half htrunc(const __half h)
{
__half r;
asm("cvt.rzi.f16.f16 %0, %1;" : "=h"(__HALF_TO_US(r)) : "h"(__HALF_TO_CUS(h)));
return r;
}
__CUDA_FP16_DECL__ __half hceil(const __half h)
{
__half r;
asm("cvt.rpi.f16.f16 %0, %1;" : "=h"(__HALF_TO_US(r)) : "h"(__HALF_TO_CUS(h)));
return r;
}
__CUDA_FP16_DECL__ __half hfloor(const __half h)
{
__half r;
asm("cvt.rmi.f16.f16 %0, %1;" : "=h"(__HALF_TO_US(r)) : "h"(__HALF_TO_CUS(h)));
return r;
}
__CUDA_FP16_DECL__ __half hrint(const __half h)
{
__half r;
asm("cvt.rni.f16.f16 %0, %1;" : "=h"(__HALF_TO_US(r)) : "h"(__HALF_TO_CUS(h)));
return r;
}
__CUDA_FP16_DECL__ __half2 h2trunc(const __half2 h)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" cvt.rzi.f16.f16 low, low;\n"
" cvt.rzi.f16.f16 high, high;\n"
" mov.b32 %0, {low,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 h2ceil(const __half2 h)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" cvt.rpi.f16.f16 low, low;\n"
" cvt.rpi.f16.f16 high, high;\n"
" mov.b32 %0, {low,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 h2floor(const __half2 h)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" cvt.rmi.f16.f16 low, low;\n"
" cvt.rmi.f16.f16 high, high;\n"
" mov.b32 %0, {low,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 h2rint(const __half2 h)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" cvt.rni.f16.f16 low, low;\n"
" cvt.rni.f16.f16 high, high;\n"
" mov.b32 %0, {low,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 __lows2half2(const __half2 l, const __half2 h)
{
__half2 val;
asm("{.reg .f16 alow,ahigh,blow,bhigh;\n"
" mov.b32 {alow,ahigh}, %1;\n"
" mov.b32 {blow,bhigh}, %2;\n"
" mov.b32 %0, {alow,blow};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(l)), "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 __highs2half2(const __half2 l, const __half2 h)
{
__half2 val;
asm("{.reg .f16 alow,ahigh,blow,bhigh;\n"
" mov.b32 {alow,ahigh}, %1;\n"
" mov.b32 {blow,bhigh}, %2;\n"
" mov.b32 %0, {ahigh,bhigh};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(l)), "r"(__HALF2_TO_CUI(h)));
return val;
}
__CUDA_FP16_DECL__ __half __low2half(const __half2 h)
{
__half ret;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" mov.b16 %0, low;}" : "=h"(__HALF_TO_US(ret)) : "r"(__HALF2_TO_CUI(h)));
return ret;
}
__CUDA_FP16_DECL__ int __hisinf(const __half a)
{
if (__HALF_TO_CUS(a) == 0xFC00) {
return -1;
}
if (__HALF_TO_CUS(a) == 0x7C00) {
return 1;
}
return 0;
}
__CUDA_FP16_DECL__ __half2 __low2half2(const __half2 l)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" mov.b32 %0, {low,low};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(l)));
return val;
}
__CUDA_FP16_DECL__ __half2 __high2half2(const __half2 l)
{
__half2 val;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" mov.b32 %0, {high,high};}\n" : "=r"(__HALF2_TO_UI(val)) : "r"(__HALF2_TO_CUI(l)));
return val;
}
__CUDA_FP16_DECL__ __half __high2half(const __half2 h)
{
__half ret;
asm("{.reg .f16 low,high;\n"
" mov.b32 {low,high}, %1;\n"
" mov.b16 %0, high;}" : "=h"(__HALF_TO_US(ret)) : "r"(__HALF2_TO_CUI(h)));
return ret;
}
__CUDA_FP16_DECL__ __half2 __halves2half2(const __half l, const __half h)
{
__half2 val;
asm("{ mov.b32 %0, {%1,%2};}\n"
: "=r"(__HALF2_TO_UI(val)) : "h"(__HALF_TO_CUS(l)), "h"(__HALF_TO_CUS(h)));
return val;
}
__CUDA_FP16_DECL__ __half2 __half2half2(const __half lh)
{