forked from google/XNNPACK
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathwasmrelaxedsimd_microkernels.bzl
465 lines (463 loc) · 32.3 KB
/
wasmrelaxedsimd_microkernels.bzl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
"""
Microkernel filenames lists for wasmrelaxedsimd.
Auto-generated file. Do not edit!
Generator: tools/update-microkernels.py
"""
ALL_WASMRELAXEDSIMD_MICROKERNEL_SRCS = [
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u32.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u32.c",
"src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-3p4c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-4p4c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-9p4c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-25p4c-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-fma-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-fma.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-wasmrelaxedsimd-fma.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u8.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u16.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u24.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u32.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemm/gen/f32-gemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-1x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-1x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-1x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-1x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-1x8s4-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemm/gen/f32-gemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-3x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-3x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-3x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-3x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-3x8s4-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-4x2c4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x2c4-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemm/gen/f32-gemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-4x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-4x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-4x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-4x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-4x8s4-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemm/gen/f32-gemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-5x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-5x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-5x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-5x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-5x8s4-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemm/gen/f32-gemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-6x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-6x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemm/gen/f32-gemm-6x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemm/gen/f32-gemm-6x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-gemm/gen/f32-gemm-6x8s4-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-ibilinear/gen/f32-ibilinear-wasmrelaxedsimd-c4.c",
"src/f32-ibilinear/gen/f32-ibilinear-wasmrelaxedsimd-c8.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-igemm/gen/f32-igemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-1x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-1x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-1x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-1x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-1x8s4-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-igemm/gen/f32-igemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-3x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-3x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-3x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-3x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-3x8s4-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-4x2c4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x2c4-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-igemm/gen/f32-igemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-4x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-4x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-4x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-4x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-4x8s4-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-igemm/gen/f32-igemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-5x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-5x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-5x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-5x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-5x8s4-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-igemm/gen/f32-igemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-6x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-6x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-igemm/gen/f32-igemm-6x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-igemm/gen/f32-igemm-6x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-igemm/gen/f32-igemm-6x8s4-wasmrelaxedsimd-fma.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x16.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x16.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x16.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x16.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x16.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x4.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x8.c",
"src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x16.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-loadsplat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-splat.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-relu-wasmrelaxedsimd-fma.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-wasmrelaxedsimd-fma.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u4.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u8-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u8.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12-acc3.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16-acc4.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20-acc5.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-arm-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-arm-pipelined.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-arm-x2.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-arm-x4.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-arm.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-x86-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-x86-pipelined.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-x86-x2.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-x86-x4.c",
"src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmrelaxedsimd-x86.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-arm-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-arm-pipelined.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-arm-x2.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-arm-x4.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-arm.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-x86-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-x86-pipelined.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-x86-x2.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-x86-x4.c",
"src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmrelaxedsimd-x86.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-arm-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-arm-pipelined.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-arm-x2.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-arm-x4.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-arm.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-x86-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-x86-pipelined.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-x86-x2.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-x86-x4.c",
"src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmrelaxedsimd-x86.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-arm-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-arm-pipelined.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-arm-x2.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-arm-x4.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-arm.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-x86-pipelined-x2.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-x86-pipelined.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-x86-x2.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-x86-x4.c",
"src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmrelaxedsimd-x86.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u4.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u8.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u12.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u16.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u20.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u24.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u4.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u8.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u12.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u16.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u20.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u24.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u4.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u8.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u12.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u16.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u20.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u24.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u4.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u8.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u12.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u16.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u20.c",
"src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u24.c",
"src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-u4.c",
"src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-u8.c",
"src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-u4.c",
"src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-u8.c",
"src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-2x.c",
"src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-fma-2x.c",
"src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-2x.c",
"src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-fma-2x.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u4.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u12.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u20.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u24.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c16-minmax-wasmsdot.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c16-minmax-wasmsdot.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c16-minmax-fp32-wasmsdot.c",
"src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u8.c",
"src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u16.c",
"src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u32.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-u16.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-u32.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u8.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u16.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u32.c",
"src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u8.c",
"src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u16.c",
"src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u32.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-u16.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-u32.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u8.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u16.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u32.c",
"src/x8-lut/gen/x8-lut-wasmpshufb-u16.c",
"src/x8-lut/gen/x8-lut-wasmpshufb-u32.c",
"src/x8-lut/gen/x8-lut-wasmpshufb-u48.c",
"src/x8-lut/gen/x8-lut-wasmpshufb-u64.c",
]