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Commits on Mar 27, 2019

• fixed typo

  vasimr

  committed
  0cff71e

• [Fixed] missing end tag

  vasimr

  committed
  3163318

• [Updated] W65C816 interface with timing diagram

  vasimr

  committed
  a91fc71

• [Added] W65C816 logic Interface module for the Gameduino (untested)

  vasimr

  committed
  bcae986

Commits on Mar 7, 2019

• [Updated] character map replaced with original C64 upper character map (all 256 with original index mapping)

  vasimr

  committed
  c12bc22

• [Added] C64 character map data for ASCII 0x20-0x5F; [Fixed] mistake in PLL generator which made the VGA interface run at 18 Hz instead of 72 Hz

  vasimr

  committed
  e556d97

Commits on Mar 6, 2019

• [Fixed] Mistake in the new gpalette register file; [Added] C64 color definition defaults for the gpalette; [WIP] Adding C64 font map to the character definitions (bit order is still incorrect)

  vasimr

  committed
  e1c8926

Commits on Mar 5, 2019

• [Updated] GPalette register file to be synthesizable on the version of ISE that supports the Spartan 3 - it did not like the bram inference VHDL

  vasimr

  committed
  b040a29

Commits on Mar 4, 2019

• [Added] Digital audio sample component (stripped from the original gameduino audio

  vasimr

  committed
  3ea2113

• [Completed] Character palette remap feature; [Tested] color palette remap feature; [Added] Dither control register, to disable VGA dithering

  vasimr

  committed
  e1bff4e

• Merge branch 'master' of https://github.com/vasimr/gameduino

  vasimr

  committed
  8b553aa

• [Updated] V2 block diagram; [Fixed] complation issues with the inferred sram files; [WIP] Implemented a global color palette mode, requires further debugging; [Added] dither enable register, which …

  Show description for eab982b
  vasimr

  committed
  eab982b

Commits on Mar 3, 2019

• Updated directory information

  vasimr

  authored
  739cca9

• [Added] new block diagram for the character color palette switcher modification; [WIP] started work on the character color palette switcher, including creation of two helper modules

  vasimr

  committed
  df12c9d

• [Fixed] Bug in the SID 8680 instantiation, it now instantiates correctly; [Rewrote] SID 8680 system verilog files into verilog (kept the system verilog copies); [Tested] Compilation of a single SID…

  Show description for 32f86da
  vasimr

  committed
  32f86da

• [Removed] Screenshot functionality; [Added] SID 8680 audio implementation (somehow LEs are lost by doing so - posisble bug, must be tested)

  vasimr

  committed
  1492e5a

• [Added] new concurrent file branch where the audio system was moved to a new module (interestingly this requires slightly more LEs).

  vasimr

  committed
  3c16b4c

Commits on Mar 2, 2019

• [Added] some development files for testing on the Nexys Video (for debug); [Updated] the SPI driver program to include more helpful functions / some macros, and upgraded to C++

  vasimr

  committed
  af02aad

Commits on Mar 1, 2019

• [Added] new sub-directory for gameduino modifications (version which works on the Spartan 6); [Added] utility c program for programing the MOD-VGA SPI PROM, and driving the gameduino via a FTDI 232H

  vasimr

  committed
  e0c72c9

Commits on Feb 26, 2019

• [Added] some bash utilities to convert Xilinx .mcs PROM files into .hex and .bin files to directly program an SPI flash memory.

  vasimr

  committed
  40c8c05

• [Added] gitignore file

  vasimr

  committed
  b6c9ac0

Commits on Feb 24, 2019

• Delete _vmake

  vasimr

  authored
  0f5346a

• Delete _lib1_17.qtl

  vasimr

  authored
  d95672c

• Delete _lib1_17.qpg

  vasimr

  authored
  323393e

• Delete _lib1_17.qdb

  vasimr

  authored
  3a0da68

• Delete LogicSim.mpf

  vasimr

  authored
  4c0e445

• Delete LogicSim.cr.mti

  vasimr

  authored
  b141196

• Delete transcript

  vasimr

  authored
  040c484

• Delete _lib.qdb

  vasimr

  authored
  b969742

• Delete _info

  vasimr

  authored
  68ddaaa

• Update README.md

  vasimr

  authored
  f303f77

• Update README.md

  vasimr

  authored
  463c8da

• [Updated] Created new block diagram to demonstrate a very simple second character bank implementation

  vasimr

  committed
  7af0ecc

• [Added] Generic synthesis inferable RAM block elements; [Updated] Optimized memory implementation to better fit the Altera Max 10 devices, results in a final M9K fit in the 10M08 without logic fit …

  Show description for 8b57920
  vasimr

  committed
  8b57920

Commits on Feb 23, 2019

• [Update] Optimized (combined) Memory modules to hopefully utilize fewer M9K blocks, result is still insufficient for implementation in the Max10 series

  vasimr

  committed
  8e63f8f

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