This repository contains the design examples which are essential for designing basic modules in High-Level synthesis.
Assignment-1: Design of 8bit X 8bit Multiplier using ap_none interface
Assignment-2:
- Design of 32bit X 32bit Multiplier
- Design of Multiplier using the arbitrary precision data type
- Design of32bit X 32bit Multiplier using HLS_stream interface
Assignment-3: Design of 32bit X 32bit Multiplier using HLS_stream interface and pipelining the module
Assignment-4: Design of basic integer ALU unit
Assignment-5: Designing a DUT for accessing and retrieving data from BRAM
Assignment-6: Implementing a 16-bit shift register
Assignment-7: Designing of basic FIR filter
Assignment-8: Designing of Cyclic Prefix removal in 5G NR.
Assignment-9: Zadoff-chu Sequence generator.